https://github.com/llvm/llvm-project/issues/62195#issuecomment-1770250844

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f030982cb815..fdc8987cb312 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1198,8 +1198,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                          ISD::VP_GATHER, ISD::VP_SCATTER, ISD::SRA, ISD::SRL,
                          ISD::SHL, ISD::STORE, ISD::SPLAT_VECTOR,
                          ISD::CONCAT_VECTORS});
-  if (Subtarget.hasVendorXTHeadMemPair())
-    setTargetDAGCombine({ISD::LOAD, ISD::STORE});
+  if (Subtarget.hasVendorXTHeadMemPair()) {
+    setTargetDAGCombine(ISD::LOAD);
+    setTargetDAGCombine(ISD::STORE);
+  }
   if (Subtarget.useRVVForFixedLengthVectors())
     setTargetDAGCombine(ISD::BITCAST);