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PICO: Adding tinyUSB library

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blckmn 2025-01-12 07:56:01 +11:00
parent 1774693395
commit 0109f50909
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150
lib/main/tinyUSB/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h Normal file
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/*
* FreeRTOS Kernel V10.0.0
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software. If you wish to use our Amazon
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
// skip if included from IAR assembler
#ifndef __IASMARM__
#include "fsl_device_registers.h"
#endif
/* Cortex M23/M33 port configuration. */
#define configENABLE_MPU 0
#define configENABLE_FPU 1
#define configENABLE_TRUSTZONE 0
#define configMINIMAL_SECURE_STACK_SIZE (1024)
#define configRUN_FREERTOS_SECURE_ONLY 1
#define configUSE_PREEMPTION 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#define configCPU_CLOCK_HZ SystemCoreClock
#define configTICK_RATE_HZ ( 1000 )
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( 128 )
#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
#define configMAX_TASK_NAME_LEN 16
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_COUNTING_SEMAPHORES 1
#define configQUEUE_REGISTRY_SIZE 4
#define configUSE_QUEUE_SETS 0
#define configUSE_TIME_SLICING 0
#define configUSE_NEWLIB_REENTRANT 0
#define configENABLE_BACKWARD_COMPATIBILITY 1
#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
#define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 0
/* Hook function related definitions. */
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configCHECK_HANDLER_INSTALLATION 0
/* Run time and task stats gathering related definitions. */
#define configGENERATE_RUN_TIME_STATS 0
#define configRECORD_STACK_HIGH_ADDRESS 1
#define configUSE_TRACE_FACILITY 1 // legacy trace
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES 2
/* Software timer related definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
#define configTIMER_QUEUE_LENGTH 32
#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
/* Optional functions - most linkers will remove unused functions anyway. */
#define INCLUDE_vTaskPrioritySet 0
#define INCLUDE_uxTaskPriorityGet 0
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
#define INCLUDE_xResumeFromISR 0
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 0
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
#define INCLUDE_pcTaskGetTaskName 0
#define INCLUDE_eTaskGetState 0
#define INCLUDE_xEventGroupSetBitFromISR 0
#define INCLUDE_xTimerPendFunctionCall 0
/* FreeRTOS hooks to NVIC vectors */
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
#define vPortSVCHandler SVC_Handler
//--------------------------------------------------------------------+
// Interrupt nesting behavior configuration.
//--------------------------------------------------------------------+
// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
#define configPRIO_BITS 3
/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1)
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
#endif

233
lib/main/tinyUSB/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld Normal file
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/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core0
** LPC55S69JBD64_cm33_core0
** LPC55S69JEV98_cm33_core0
**
** Compiler: GNU C Compiler
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b191008
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0;
/* Specify the memory areas */
MEMORY
{
m_interrupts (RX) : ORIGIN = 0x00010000, LENGTH = 0x00000200
m_text (RX) : ORIGIN = 0x00010200, LENGTH = 0x0007FE00
m_core1_image (RX) : ORIGIN = 0x00090000, LENGTH = 0x00008000
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00033000 - RPMSG_SHMEM_SIZE
rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE
m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000
}
/* Define output sections */
SECTIONS
{
/* section for storing the secondary core image */
.m0code :
{
. = ALIGN(4) ;
KEEP (*(.m0code))
*(.m0code*)
. = ALIGN(4) ;
} > m_core1_image
/* NOINIT section for rpmsg_sh_mem */
.noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
{
__RPMSG_SH_MEM_START__ = .;
*(.noinit.$rpmsg_sh_mem*)
. = ALIGN(4) ;
__RPMSG_SH_MEM_END__ = .;
} > rpmsg_sh_mem
/* The startup code goes first into internal flash */
.interrupts :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > m_interrupts
/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.ramfunc*) /* for functions in ram */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data
.stack :
{
. = ALIGN(8);
. += STACK_SIZE;
} > m_data
m_usb_bdt (NOLOAD) :
{
. = ALIGN(512);
*(m_usb_bdt)
} > m_usb_sram
m_usb_global (NOLOAD) :
{
*(m_usb_global)
} > m_usb_sram
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
}

19
lib/main/tinyUSB/hw/bsp/lpc55/boards/double_m33_express/board.cmake Normal file
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set(MCU_VARIANT LPC55S69)
set(MCU_CORE LPC55S69_cm33_core0)
set(JLINK_DEVICE LPC55S69)
set(PYOCD_TARGET LPC55S69)
set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
# Device port default to PORT1 Highspeed
if (NOT DEFINED PORT)
set(PORT 1)
endif()
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_LPC55S69JBD100_cm33_core0
)
endfunction()

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lib/main/tinyUSB/hw/bsp/lpc55/boards/double_m33_express/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// LED
#define LED_PORT 0
#define LED_PIN 1
#define LED_STATE_ON 1
// WAKE button
#define BUTTON_PORT 0
#define BUTTON_PIN 5
#define BUTTON_STATE_ACTIVE 0
// Number of neopixels
#define NEOPIXEL_NUMBER 2
#define NEOPIXEL_PORT 0
#define NEOPIXEL_PIN 27
#define NEOPIXEL_CH 6
#define NEOPIXEL_TYPE 0
// UART
#define UART_DEV USART0
#define UART_RX_PINMUX 0U, 29U, IOCON_PIO_DIG_FUNC1_EN
#define UART_TX_PINMUX 0U, 30U, IOCON_PIO_DIG_FUNC1_EN
// XTAL
#define XTAL0_CLK_HZ (16 * 1000 * 1000U)
#ifdef __cplusplus
}
#endif
#endif

12
lib/main/tinyUSB/hw/bsp/lpc55/boards/double_m33_express/board.mk Normal file
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MCU_VARIANT = LPC55S69
MCU_CORE = LPC55S69_cm33_core0
PORT ?= 1
CFLAGS += -DCPU_LPC55S69JBD100_cm33_core0
LD_FILE = $(BOARD_PATH)/LPC55S69_cm33_core0_uf2.ld
JLINK_DEVICE = LPC55S69
PYOCD_TARGET = LPC55S69
# flash using pyocd
flash: flash-pyocd

17
lib/main/tinyUSB/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake Normal file
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set(MCU_VARIANT LPC55S28)
set(MCU_CORE LPC55S28)
set(JLINK_DEVICE LPC55S28)
set(PYOCD_TARGET LPC55S28)
set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28)
# Device port default to PORT1 Highspeed
if (NOT DEFINED PORT)
set(PORT 1)
endif()
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_LPC55S28JBD100
)
endfunction()

56
lib/main/tinyUSB/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// LED
#define LED_PORT 1
#define LED_PIN 6
#define LED_STATE_ON 0
// WAKE button
#define BUTTON_PORT 1
#define BUTTON_PIN 18
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_DEV USART0
#define UART_RX_PINMUX 0, 29, IOCON_PIO_DIG_FUNC1_EN
#define UART_TX_PINMUX 0, 30, IOCON_PIO_DIG_FUNC1_EN
// XTAL
#define XTAL0_CLK_HZ (16 * 1000 * 1000U)
#ifdef __cplusplus
}
#endif
#endif

11
lib/main/tinyUSB/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk Normal file
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MCU_VARIANT = LPC55S28
MCU_CORE = LPC55S28
PORT ?= 1
CFLAGS += -DCPU_LPC55S28JBD100
JLINK_DEVICE = LPC55S28
PYOCD_TARGET = LPC55S28
# flash using pyocd
flash: flash-pyocd

17
lib/main/tinyUSB/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake Normal file
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set(MCU_VARIANT LPC55S69)
set(MCU_CORE LPC55S69_cm33_core0)
set(JLINK_DEVICE LPC55S69_M33_0)
set(PYOCD_TARGET LPC55S69)
set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
# Device port default to PORT1 Highspeed
if (NOT DEFINED PORT)
set(PORT 1)
endif()
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_LPC55S69JBD100_cm33_core0
)
endfunction()

56
lib/main/tinyUSB/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// LED
#define LED_PORT 1
#define LED_PIN 6
#define LED_STATE_ON 0
// WAKE button
#define BUTTON_PORT 1
#define BUTTON_PIN 18
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_DEV USART0
#define UART_RX_PINMUX 0, 29, IOCON_PIO_DIG_FUNC1_EN
#define UART_TX_PINMUX 0, 30, IOCON_PIO_DIG_FUNC1_EN
// XTAL
#define XTAL0_CLK_HZ (16 * 1000 * 1000U)
#ifdef __cplusplus
}
#endif
#endif

11
lib/main/tinyUSB/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk Normal file
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MCU_VARIANT = LPC55S69
MCU_CORE = LPC55S69_cm33_core0
PORT ?= 1
CFLAGS += -DCPU_LPC55S69JBD100_cm33_core0
JLINK_DEVICE = LPC55S69
PYOCD_TARGET = LPC55S69
# flash using pyocd
flash: flash-pyocd

14
lib/main/tinyUSB/hw/bsp/lpc55/boards/mcu_link/board.cmake Normal file
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set(MCU_VARIANT LPC55S69)
set(MCU_CORE LPC55S69_cm33_core0)
set(JLINK_DEVICE LPC55S69)
set(PYOCD_TARGET LPC55S69)
set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_LPC55S69JBD100_cm33_core0
# port 1 is highspeed
# BOARD_TUD_RHPORT=1
)
endfunction()

56
lib/main/tinyUSB/hw/bsp/lpc55/boards/mcu_link/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// LED
#define LED_PORT 0
#define LED_PIN 5
#define LED_STATE_ON 0
// WAKE button (Dummy, use unused pin
#define BUTTON_PORT 0
#define BUTTON_PIN 30
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_DEV USART0
#define UART_RX_PINMUX 0, 24, IOCON_PIO_DIG_FUNC1_EN
#define UART_TX_PINMUX 0, 25, IOCON_PIO_DIG_FUNC1_EN
// XTAL
#define XTAL0_CLK_HZ (16 * 1000 * 1000U)
#ifdef __cplusplus
}
#endif
#endif

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MCU_VARIANT = LPC55S69
MCU_CORE = LPC55S69_cm33_core0
PORT ?= 1
CFLAGS += -DCPU_LPC55S69JBD64_cm33_core0
JLINK_DEVICE = LPC55S69
PYOCD_TARGET = LPC55S69
# flash using pyocd
flash: flash-pyocd

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/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "bsp/board_api.h"
#include "board.h"
#include "fsl_device_registers.h"
#include "fsl_gpio.h"
#include "fsl_power.h"
#include "fsl_iocon.h"
#include "fsl_usart.h"
#ifdef NEOPIXEL_PIN
#include "fsl_sctimer.h"
#include "sct_neopixel.h"
#endif
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
// IOCON pin mux
#define IOCON_PIO_DIGITAL_EN 0x0100u // Enables digital function
#define IOCON_PIO_FUNC0 0x00u // Selects pin function 0
#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1
#define IOCON_PIO_FUNC4 0x04u // Selects pin function 4
#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7
#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted
#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function
#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled
#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled
#define IOCON_PIO_DIG_FUNC0_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC0) // Digital pin function 0 enabled
#define IOCON_PIO_DIG_FUNC1_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC1) // Digital pin function 1 enabled
#define IOCON_PIO_DIG_FUNC4_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC4) // Digital pin function 2 enabled
#define IOCON_PIO_DIG_FUNC7_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC7) // Digital pin function 2 enabled
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
void USB0_IRQHandler(void) {
tusb_int_handler(0, true);
}
void USB1_IRQHandler(void) {
tusb_int_handler(1, true);
}
/****************************************************************
name: BOARD_BootClockPLL100M
outputs:
- {id: System_clock.outFreq, value: 100 MHz}
settings:
- {id: PLL0_Mode, value: Normal}
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
- {id: ENABLE_CLKIN_ENA, value: Enabled}
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
sources:
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
******************************************************************/
void BOARD_BootClockPLL100M(void)
{
/*!< Set up the clock sources */
/*!< Configure FRO192M */
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
/*!< Configure XTAL32M */
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
/*!< Set up PLL */
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
const pll_setup_t pll0Setup = {
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
.pllndec = SYSCON_PLL0NDEC_NDIV(4U),
.pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
.pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
.pllRate = 100000000U,
.flags = PLL_SETUPFLAG_WAITLOCK
};
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
/*< Set SystemCoreClock variable. */
SystemCoreClock = 100000000U;
}
void board_init(void) {
// Enable IOCON clock
CLOCK_EnableClock(kCLOCK_Iocon);
// Init 100 MHz clock
BOARD_BootClockPLL100M();
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
// Explicitly disable systick to prevent its ISR runs before scheduler start
SysTick->CTRL &= ~1U;
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
#endif
// Init all GPIO ports
GPIO_PortInit(GPIO, 0);
GPIO_PortInit(GPIO, 1);
// LED
IOCON_PinMuxSet(IOCON, LED_PORT, LED_PIN, IOCON_PIO_DIG_FUNC0_EN);
gpio_pin_config_t const led_config = {kGPIO_DigitalOutput, 1};
GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
board_led_write(0);
#ifdef NEOPIXEL_PIN
// Neopixel
static uint32_t pixelData[NEOPIXEL_NUMBER];
IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
sctpix_init(NEOPIXEL_TYPE);
sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
sctpix_show();
#endif
// Button
IOCON_PinMuxSet(IOCON, BUTTON_PORT, BUTTON_PIN, IOCON_PIO_DIG_FUNC0_EN);
gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0};
GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
#ifdef UART_DEV
// UART
IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
// Enable UART when debug log is on
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
usart_config_t uart_config;
USART_GetDefaultConfig(&uart_config);
uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
uart_config.enableTx = true;
uart_config.enableRx = true;
USART_Init(UART_DEV, &uart_config, 12000000);
#endif
// USB VBUS
/* PORT0 PIN22 configured as USB0_VBUS */
IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0
// Port0 is Full Speed
/* Turn on USB0 Phy */
POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
/* reset the IP to make sure it's in reset state. */
RESET_PeripheralReset(kUSB0D_RST_SHIFT_RSTn);
RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn);
RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn);
// Enable USB Clock Adjustments to trim the FRO for the full speed controller
ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
/*According to reference manual, device mode setting has to be set by access usb host register */
CLOCK_EnableClock(kCLOCK_Usbhsl0); // enable usb0 host clock
USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
/* enable USB Device clock */
CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
#endif
#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1
// Port1 is High Speed
/* Turn on USB1 Phy */
POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
/* reset the IP to make sure it's in reset state. */
RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
/* According to reference manual, device mode setting has to be set by access usb host register */
CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock
/* enable USB Device clock */
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, XTAL0_CLK_HZ);
CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
CLOCK_EnableClock(kCLOCK_UsbRam1);
// Enable PHY support for Low speed device + LS via FS Hub
USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
// Enable all power for normal operation
USBPHY->PWD = 0;
USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK;
USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK;
// TX Timing
// uint32_t phytx = USBPHY->TX;
// phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
// phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
// USBPHY->TX = phytx;
ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer)
ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0));
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
#endif
}
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state) {
GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
#ifdef NEOPIXEL_PIN
if (state) {
sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
} else {
sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
}
sctpix_show();
#endif
}
uint32_t board_button_read(void) {
// active low
return BUTTON_STATE_ACTIVE == GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
}
int board_uart_read(uint8_t* buf, int len) {
(void) buf;
(void) len;
return 0;
}
int board_uart_write(void const* buf, int len) {
USART_WriteBlocking(UART_DEV, (uint8_t const*) buf, len);
return len;
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler(void) {
system_ticks++;
}
uint32_t board_millis(void) {
return system_ticks;
}
#endif
#ifndef __ICCARM__
// Implement _start() since we use linker flag '-nostartfiles'.
// Requires defined __STARTUP_CLEAR_BSS,
extern int main(void);
TU_ATTR_UNUSED void _start(void) {
// called by startup code
main();
while (1) {}
}
#ifdef __clang__
void _exit (int __status) {
while (1) {}
}
#endif
#endif

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lib/main/tinyUSB/hw/bsp/lpc55/family.cmake Normal file
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include_guard()
set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
# include board specific
include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS LPC55 CACHE INTERNAL "")
if (NOT DEFINED PORT)
set(PORT 0)
endif()
# Host port will be the other port if available
set(HOST_PORT $<NOT:${PORT}>)
#------------------------------------
# BOARD_TARGET
#------------------------------------
# only need to be built ONCE for all examples
function(add_board_target BOARD_TARGET)
if (TARGET ${BOARD_TARGET})
return()
endif()
if (NOT DEFINED LD_FILE_GNU)
set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
endif ()
set(LD_FILE_Clang ${LD_FILE_GNU})
if (NOT DEFINED STARTUP_FILE_GNU)
set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
endif ()
set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
add_library(${BOARD_TARGET} STATIC
${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
# driver
${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
${SDK_DIR}/drivers/common/fsl_common_arm.c
${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
${SDK_DIR}/drivers/flexcomm/fsl_usart.c
# mcu
${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
)
target_include_directories(${BOARD_TARGET} PUBLIC
${TOP}/lib/sct_neopixel
# driver
${SDK_DIR}/drivers/common
${SDK_DIR}/drivers/flexcomm
${SDK_DIR}/drivers/lpc_iocon
${SDK_DIR}/drivers/lpc_gpio
${SDK_DIR}/drivers/lpuart
${SDK_DIR}/drivers/sctimer
# mcu
${SDK_DIR}/devices/${MCU_VARIANT}
${SDK_DIR}/devices/${MCU_VARIANT}/drivers
${CMSIS_DIR}/CMSIS/Core/Include
)
target_compile_definitions(${BOARD_TARGET} PUBLIC
CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
BOARD_TUD_RHPORT=${PORT}
BOARD_TUH_RHPORT=${HOST_PORT}
__STARTUP_CLEAR_BSS
)
# Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
if (PORT EQUAL 1)
target_compile_definitions(${BOARD_TARGET} PUBLIC
BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
)
else ()
target_compile_definitions(${BOARD_TARGET} PUBLIC
BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
)
endif ()
update_board(${BOARD_TARGET})
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
target_link_options(${BOARD_TARGET} PUBLIC
"LINKER:--script=${LD_FILE_GNU}"
--specs=nosys.specs --specs=nano.specs
-nostartfiles
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
target_link_options(${BOARD_TARGET} PUBLIC
"LINKER:--script=${LD_FILE_Clang}"
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${BOARD_TARGET} PUBLIC
"LINKER:--config=${LD_FILE_IAR}"
)
endif ()
endfunction()
#------------------------------------
# Functions
#------------------------------------
function(family_configure_example TARGET RTOS)
family_configure_common(${TARGET} ${RTOS})
# Board target
add_board_target(board_${BOARD})
#---------- Port Specific ----------
# These files are built for each example since it depends on example's tusb_config.h
target_sources(${TARGET} PUBLIC
# BSP
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
# external driver
${TOP}/lib/sct_neopixel/sct_neopixel.c
)
# https://github.com/gsteiert/sct_neopixel/pull/1
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
set_source_files_properties(${TOP}/lib/sct_neopixel/sct_neopixel.c PROPERTIES
COMPILE_FLAGS "-Wno-unused-parameter")
endif ()
target_include_directories(${TARGET} PUBLIC
# family, hw, board
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
)
# Add TinyUSB target and port source
family_add_tinyusb(${TARGET} OPT_MCU_LPC55 ${RTOS})
target_sources(${TARGET}-tinyusb PUBLIC
${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
)
target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
# Link dependencies
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
#family_flash_pyocd(${TARGET})
endfunction()

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UF2_FAMILY_ID = 0x2abc77ec
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += lib/CMSIS_5 lib/sct_neopixel $(SDK_DIR)
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m33
MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
# Default to Highspeed PORT1
PORT ?= 1
CFLAGS += \
-flto \
-D__STARTUP_CLEAR_BSS \
-DCFG_TUSB_MCU=OPT_MCU_LPC55XX \
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
-DBOARD_TUD_RHPORT=$(PORT) \
ifeq ($(PORT), 1)
$(info "PORT1 High Speed")
CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
# LPC55 Highspeed Port1 can only write to USB_SRAM region
CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))'
else
$(info "PORT0 Full Speed")
endif
# mcu driver cause following warnings
CFLAGS += -Wno-error=unused-parameter -Wno-error=float-equal
LDFLAGS_GCC += \
-nostartfiles \
--specs=nosys.specs --specs=nano.specs \
# All source paths should be relative to the top level.
LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_CORE)_flash.ld
SRC_C += \
src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
$(MCU_DIR)/system_$(MCU_CORE).c \
$(MCU_DIR)/drivers/fsl_clock.c \
$(MCU_DIR)/drivers/fsl_power.c \
$(MCU_DIR)/drivers/fsl_reset.c \
$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
$(SDK_DIR)/drivers/common/fsl_common_arm.c \
$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
$(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
lib/sct_neopixel/sct_neopixel.c
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/lib/sct_neopixel \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
$(TOP)/$(MCU_DIR) \
$(TOP)/$(MCU_DIR)/drivers \
$(TOP)/$(SDK_DIR)/drivers/common \
$(TOP)/$(SDK_DIR)/drivers/flexcomm \
$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
$(TOP)/$(SDK_DIR)/drivers/lpc_gpio \
$(TOP)/$(SDK_DIR)/drivers/sctimer
SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a