diff --git a/src/main/drivers/at32/timer_at32f43x.c b/src/main/drivers/at32/timer_at32f43x.c index e30c6c3b2d..ebe129b9fc 100644 --- a/src/main/drivers/at32/timer_at32f43x.c +++ b/src/main/drivers/at32/timer_at32f43x.c @@ -72,8 +72,7 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = { DEF_TIM(TMR1, CH3, PA10, 0, 0, 0), DEF_TIM(TMR1, CH4, PA11, 0, 0, 0), -// Port B ORDER BY MUX 1 2 3 -//MUX1 +// PORTB MUX1 DEF_TIM(TMR1, CH2N, PB0, 0, 0, 0), DEF_TIM(TMR1, CH3N, PB1, 0, 0, 0), DEF_TIM(TMR2, CH4, PB2, 0, 0, 0), @@ -85,7 +84,8 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = { DEF_TIM(TMR1, CH1N, PB13, 0, 0, 0), DEF_TIM(TMR1, CH2N, PB14, 0, 0, 0), DEF_TIM(TMR1, CH3N, PB15, 0, 0, 0), -//MUX2 + +// PORTB MUX2 DEF_TIM(TMR3, CH3, PB0, 0, 0, 0), DEF_TIM(TMR3, CH4, PB1, 0, 0, 0), DEF_TIM(TMR20, CH1, PB2, 0, 0, 0), @@ -97,26 +97,94 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = { DEF_TIM(TMR4, CH4, PB9, 0, 10, 9), DEF_TIM(TMR5, CH4, PB11, 0, 0, 0), DEF_TIM(TMR5, CH1, PB12, 0, 0, 0), -//MUX3 +// PORTB MUX3 DEF_TIM(TMR8, CH2N, PB0, 0, 0, 0), DEF_TIM(TMR8, CH3N, PB1, 0, 0, 0), DEF_TIM(TMR8, CH2N, PB14, 0, 0, 0), DEF_TIM(TMR8, CH3N, PB15, 0, 0, 0), +// PORTB MUX9 + DEF_TIM(TMR12, CH1, PB14, 0, 0, 0), + DEF_TIM(TMR12, CH2, PB15, 0, 0, 0), -// Port C ORDER BY MUX 1 2 3 -//MUX2 +// PORTC MUX2 DEF_TIM(TMR20, CH2, PC2, 0, 0, 0), - DEF_TIM(TMR3, CH1, PC6, 0, 0, 12), + DEF_TIM(TMR3, CH1, PC6, 0, 0, 0), DEF_TIM(TMR3, CH2, PC7, 0, 0, 12), DEF_TIM(TMR3, CH3, PC8, 0, 0, 12), DEF_TIM(TMR3, CH4, PC9, 0, 0, 12), - DEF_TIM(TMR5, CH2, PC10, 0, 0, 0), + DEF_TIM(TMR5, CH2, PC10, 0, 0, 12), DEF_TIM(TMR5, CH3, PC11, 0, 0, 0), -//MUX 3 + +// PORTC MUX 3 DEF_TIM(TMR8, CH1, PC6, 0, 0, 0), DEF_TIM(TMR8, CH2, PC7, 0, 0, 0), DEF_TIM(TMR8, CH3, PC8, 0, 0, 0), DEF_TIM(TMR8, CH4, PC9, 0, 0, 0), + DEF_TIM(TMR11, CH1N, PC12, 0, 0, 0), + +// PORTD MUX 2 + DEF_TIM(TMR4, CH1, PD12, 0, 0, 0), + DEF_TIM(TMR4, CH2, PD13, 0, 0, 0), + DEF_TIM(TMR4, CH3, PD14, 0, 0, 0), + DEF_TIM(TMR4, CH4, PD15, 0, 0, 0), + +// PORTE MUX 1 + DEF_TIM(TMR1, CH2N, PE1, 0, 0, 0), + DEF_TIM(TMR1, CH1N, PE8, 0, 0, 0), + DEF_TIM(TMR1, CH1, PE9, 0, 0, 0), + DEF_TIM(TMR1, CH2N, PE10, 0, 0, 0), + DEF_TIM(TMR1, CH2, PE11, 0, 0, 0), + DEF_TIM(TMR1, CH3N, PE12, 0, 0, 0), + DEF_TIM(TMR1, CH3, PE13, 0, 0, 0), + DEF_TIM(TMR1, CH4, PE14, 0, 0, 0), + +// PORTE MUX 2 + DEF_TIM(TMR3, CH1, PE3, 0, 0, 0), + DEF_TIM(TMR3, CH2, PE4, 0, 0, 0), + DEF_TIM(TMR3, CH3, PE5, 0, 0, 0), + DEF_TIM(TMR3, CH4, PE6, 0, 0, 0), + +// PORTE MUX 3 + DEF_TIM(TMR9, CH1, PE5, 0, 0, 0), + DEF_TIM(TMR9, CH2, PE6, 0, 0, 0), + +// PORTE MUX 6 + DEF_TIM(TMR20, CH4, PE1, 0, 0, 0), + DEF_TIM(TMR20, CH1, PE2, 0, 0, 0), + DEF_TIM(TMR20, CH2, PE3, 0, 0, 0), + DEF_TIM(TMR20, CH1N, PE4, 0, 0, 0), + DEF_TIM(TMR20, CH2N, PE5, 0, 0, 0), + DEF_TIM(TMR20, CH3N, PE6, 0, 0, 0), + +// PORTF MUX 2 + DEF_TIM(TMR20, CH3, PF2, 0, 0, 0), + DEF_TIM(TMR20, CH4, PF3, 0, 0, 0), + DEF_TIM(TMR20, CH1N, PF4, 0, 0, 0), + DEF_TIM(TMR20, CH2N, PF5, 0, 0, 0), + DEF_TIM(TMR20, CH4, PF6, 0, 0, 0), + DEF_TIM(TMR20, CH1, PF12, 0, 0, 0), + DEF_TIM(TMR20, CH2, PF13, 0, 0, 0), + DEF_TIM(TMR20, CH3, PF14, 0, 0, 0), + DEF_TIM(TMR20, CH4, PF15, 0, 0, 0), + +// PORTF MUX 3 + DEF_TIM(TMR10, CH1, PF6, 0, 0, 0), + DEF_TIM(TMR11, CH1, PF7, 0, 0, 0), + +// PORTF MUX 9 + DEF_TIM(TMR13, CH1, PF8, 0, 0, 0), + DEF_TIM(TMR14, CH1, PF9, 0, 0, 0), + +// Port G ORDER BY MUX 1 2 3 +// MUX2 + DEF_TIM(TMR20, CH1N, PG0, 0, 0, 0), + DEF_TIM(TMR20, CH2N, PG1, 0, 0, 0), + DEF_TIM(TMR20, CH3N, PG2, 0, 0, 0), + +// Port H ORDER BY MUX 1 2 3 +// MUX2 + DEF_TIM(TMR5, CH1, PH2, 0, 0, 0), + DEF_TIM(TMR5, CH2, PH3, 0, 0, 0), }; #endif diff --git a/src/main/drivers/at32/timer_def.h b/src/main/drivers/at32/timer_def.h index 32a3514f84..42b58427eb 100644 --- a/src/main/drivers/at32/timer_def.h +++ b/src/main/drivers/at32/timer_def.h @@ -24,9 +24,9 @@ #include "platform.h" #include "common/utils.h" -#define USED_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(8) | BIT(20)) -#define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) |BIT(14) | BIT(20)) -#define FULL_TIMER_CHANNEL_COUNT 56 +#define USED_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(20) ) +#define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(8) | BIT(20) ) +#define FULL_TIMER_CHANNEL_COUNT 101 #define HARDWARE_TIMER_DEFINITION_COUNT 15 // allow conditional definition of DMA related members @@ -52,6 +52,8 @@ #define BTCH_TMR8_CH2N BTCH_TMR8_CH2 #define BTCH_TMR8_CH3N BTCH_TMR8_CH3 +#define BTCH_TMR11_CH1N BTCH_TMR11_CH1 + #define BTCH_TMR20_CH1N BTCH_TMR20_CH1 #define BTCH_TMR20_CH2N BTCH_TMR20_CH2 #define BTCH_TMR20_CH3N BTCH_TMR20_CH3 @@ -130,13 +132,13 @@ #define DEF_TIM_OUTPUT__D(chan_n, n_channel) PP_IIF(n_channel, TIMER_OUTPUT_N_CHANNEL, TIMER_OUTPUT_NONE) /* - DEF_TIM(tim, chan, pin, flags, out,dmaopt,upopt) - @tim,chan tmr & channel - @pin output pin - @flags usage for timer - @out 0 for normal 1 for N_Channel - @dmaopt dma channel index used for timer channel data transmit - @upopt USE_DSHOT_DMAR timeup dma channel index + DEF_TIM(tim, chan, pin, flags, out, dmaopt, upopt) + @tim, + @chan tmr & channel + @pin output pin + @out 0 for normal 1 for N_Channel + @dmaopt dma channel index used for timer channel data transmit + @upopt USE_DSHOT_DMAR timeup dma channel index */ #define DEF_TIM(tim, chan, pin, out, dmaopt, upopt) { \ tim, \ @@ -212,12 +214,23 @@ #define DEF_TIM_DMA__BTCH_TMR8_CH3 DEF_TIM_DMA_FULL #define DEF_TIM_DMA__BTCH_TMR8_CH4 DEF_TIM_DMA_FULL -#define DEF_TIM_DMA__BTCH_TMR15_CH1 DEF_TIM_DMA_FULL +#define DEF_TIM_DMA__BTCH_TMR9_CH1 NONE +#define DEF_TIM_DMA__BTCH_TMR9_CH2 NONE + +#define DEF_TIM_DMA__BTCH_TMR10_CH1 NONE + +#define DEF_TIM_DMA__BTCH_TMR11_CH1 NONE +#define DEF_TIM_DMA__BTCH_TMR12_CH1 NONE +#define DEF_TIM_DMA__BTCH_TMR12_CH2 NONE + +#define DEF_TIM_DMA__BTCH_TMR13_CH1 NONE +#define DEF_TIM_DMA__BTCH_TMR14_CH1 NONE + +#define DEF_TIM_DMA__BTCH_TMR15_CH1 NONE #define DEF_TIM_DMA__BTCH_TMR15_CH2 NONE -#define DEF_TIM_DMA__BTCH_TMR16_CH1 DEF_TIM_DMA_FULL - -#define DEF_TIM_DMA__BTCH_TMR17_CH1 DEF_TIM_DMA_FULL +#define DEF_TIM_DMA__BTCH_TMR16_CH1 NONE +#define DEF_TIM_DMA__BTCH_TMR17_CH1 NONE #define DEF_TIM_DMA__BTCH_TMR20_CH1 DEF_TIM_DMA_FULL #define DEF_TIM_DMA__BTCH_TMR20_CH2 DEF_TIM_DMA_FULL @@ -233,9 +246,15 @@ #define DEF_TIM_DMA__BTCH_TMR6_UP DEF_TIM_DMA_FULL #define DEF_TIM_DMA__BTCH_TMR7_UP DEF_TIM_DMA_FULL #define DEF_TIM_DMA__BTCH_TMR8_UP DEF_TIM_DMA_FULL -#define DEF_TIM_DMA__BTCH_TMR15_UP DEF_TIM_DMA_FULL -#define DEF_TIM_DMA__BTCH_TMR16_UP DEF_TIM_DMA_FULL -#define DEF_TIM_DMA__BTCH_TMR17_UP DEF_TIM_DMA_FULL +#define DEF_TIM_DMA__BTCH_TMR9_UP NONE +#define DEF_TIM_DMA__BTCH_TMR10_UP NONE +#define DEF_TIM_DMA__BTCH_TMR11_UP NONE +#define DEF_TIM_DMA__BTCH_TMR12_UP NONE +#define DEF_TIM_DMA__BTCH_TMR13_UP NONE +#define DEF_TIM_DMA__BTCH_TMR14_UP NONE +#define DEF_TIM_DMA__BTCH_TMR15_UP NONE +#define DEF_TIM_DMA__BTCH_TMR16_UP NONE +#define DEF_TIM_DMA__BTCH_TMR17_UP NONE #define DEF_TIM_DMA__BTCH_TMR20_UP DEF_TIM_DMA_FULL // TIMx_CHy request table @@ -272,6 +291,17 @@ #define DEF_TIM_DMA_REQ__BTCH_TMR8_CH3 DMAMUX_DMAREQ_ID_TMR8_CH3 #define DEF_TIM_DMA_REQ__BTCH_TMR8_CH4 DMAMUX_DMAREQ_ID_TMR8_CH4 +#define DEF_TIM_DMA_REQ__BTCH_TMR9_CH1 DMA_REQUEST_NONE +#define DEF_TIM_DMA_REQ__BTCH_TMR9_CH2 DMA_REQUEST_NONE +#define DEF_TIM_DMA_REQ__BTCH_TMR10_CH1 DMA_REQUEST_NONE +#define DEF_TIM_DMA_REQ__BTCH_TMR11_CH1 DMA_REQUEST_NONE + +#define DEF_TIM_DMA_REQ__BTCH_TMR12_CH1 DMA_REQUEST_NONE +#define DEF_TIM_DMA_REQ__BTCH_TMR12_CH2 DMA_REQUEST_NONE + +#define DEF_TIM_DMA_REQ__BTCH_TMR13_CH1 DMA_REQUEST_NONE +#define DEF_TIM_DMA_REQ__BTCH_TMR14_CH1 DMA_REQUEST_NONE + #define DEF_TIM_DMA_REQ__BTCH_TMR20_CH1 DMAMUX_DMAREQ_ID_TMR20_CH1 #define DEF_TIM_DMA_REQ__BTCH_TMR20_CH2 DMAMUX_DMAREQ_ID_TMR20_CH2 #define DEF_TIM_DMA_REQ__BTCH_TMR20_CH3 DMAMUX_DMAREQ_ID_TMR20_CH3 @@ -284,6 +314,12 @@ #define DEF_TIM_DMA_REQ__BTCH_TMR4_UP DMAMUX_DMAREQ_ID_TMR4_OVERFLOW #define DEF_TIM_DMA_REQ__BTCH_TMR5_UP DMAMUX_DMAREQ_ID_TMR5_OVERFLOW #define DEF_TIM_DMA_REQ__BTCH_TMR8_UP DMAMUX_DMAREQ_ID_TMR8_OVERFLOW +#define DEF_TIM_DMA_REQ__BTCH_TMR9_UP DMA_REQUEST_NONE +#define DEF_TIM_DMA_REQ__BTCH_TMR10_UP DMA_REQUEST_NONE +#define DEF_TIM_DMA_REQ__BTCH_TMR11_UP DMA_REQUEST_NONE +#define DEF_TIM_DMA_REQ__BTCH_TMR12_UP DMA_REQUEST_NONE +#define DEF_TIM_DMA_REQ__BTCH_TMR13_UP DMA_REQUEST_NONE +#define DEF_TIM_DMA_REQ__BTCH_TMR14_UP DMA_REQUEST_NONE #define DEF_TIM_DMA_REQ__BTCH_TMR20_UP DMAMUX_DMAREQ_ID_TMR20_OVERFLOW // AF table for timer ,default is GPIO_MUX_1 should be check after debug @@ -299,34 +335,34 @@ #define DEF_TIM_AF__NONE__TCH_TMR8_CH4 D(1, 8) //PORTA MUX 1 -#define DEF_TIM_AF__PA0__TCH_TMR2_CH1 D(1, 2) -#define DEF_TIM_AF__PA1__TCH_TMR2_CH2 D(1, 2) -#define DEF_TIM_AF__PA2__TCH_TMR2_CH3 D(1, 2) -#define DEF_TIM_AF__PA3__TCH_TMR2_CH4 D(1, 2) -#define DEF_TIM_AF__PA5__TCH_TMR2_CH1 D(1, 2) -#define DEF_TIM_AF__PA7__TCH_TMR1_CH1N D(1, 1) -#define DEF_TIM_AF__PA8__TCH_TMR1_CH1 D(1, 1) -#define DEF_TIM_AF__PA9__TCH_TMR1_CH2 D(1, 1) -#define DEF_TIM_AF__PA10__TCH_TMR1_CH3 D(1, 1) -#define DEF_TIM_AF__PA11__TCH_TMR1_CH4 D(1, 1) -#define DEF_TIM_AF__PA15__TCH_TMR2_CH1 D(1, 2) +#define DEF_TIM_AF__PA0__TCH_TMR2_CH1 D(1, 2) +#define DEF_TIM_AF__PA1__TCH_TMR2_CH2 D(1, 2) +#define DEF_TIM_AF__PA2__TCH_TMR2_CH3 D(1, 2) +#define DEF_TIM_AF__PA3__TCH_TMR2_CH4 D(1, 2) +#define DEF_TIM_AF__PA5__TCH_TMR2_CH1 D(1, 2) +#define DEF_TIM_AF__PA7__TCH_TMR1_CH1N D(1, 1) +#define DEF_TIM_AF__PA8__TCH_TMR1_CH1 D(1, 1) +#define DEF_TIM_AF__PA9__TCH_TMR1_CH2 D(1, 1) +#define DEF_TIM_AF__PA10__TCH_TMR1_CH3 D(1, 1) +#define DEF_TIM_AF__PA11__TCH_TMR1_CH4 D(1, 1) +#define DEF_TIM_AF__PA15__TCH_TMR2_CH1 D(1, 2) + //PORTA MUX 2 -#define DEF_TIM_AF__PA0__TCH_TMR5_CH1 D(2, 5) -#define DEF_TIM_AF__PA1__TCH_TMR5_CH2 D(2, 5) -#define DEF_TIM_AF__PA2__TCH_TMR5_CH3 D(2, 5) -#define DEF_TIM_AF__PA3__TCH_TMR5_CH4 D(2, 5) -#define DEF_TIM_AF__PA6__TCH_TMR3_CH1 D(2, 3) -#define DEF_TIM_AF__PA7__TCH_TMR3_CH2 D(2, 3) +#define DEF_TIM_AF__PA0__TCH_TMR5_CH1 D(2, 5) +#define DEF_TIM_AF__PA1__TCH_TMR5_CH2 D(2, 5) +#define DEF_TIM_AF__PA2__TCH_TMR5_CH3 D(2, 5) +#define DEF_TIM_AF__PA3__TCH_TMR5_CH4 D(2, 5) +#define DEF_TIM_AF__PA6__TCH_TMR3_CH1 D(2, 3) +#define DEF_TIM_AF__PA7__TCH_TMR3_CH2 D(2, 3) -//PORTA MUX 3 -//#define DEF_TIM_AF__PA0__TCH_TMR8_CH1N D(1, 15)//tmr8_ext -#define DEF_TIM_AF__PA2__TCH_TMR9_CH1 D(3, 9) -#define DEF_TIM_AF__PA3__TCH_TMR9_CH2 D(3, 9) -#define DEF_TIM_AF__PA5__TCH_TMR8_CH1N D(3, 8) -#define DEF_TIM_AF__PA7__TCH_TMR8_CH1N D(3, 8) +// PORTA MUX 3 +#define DEF_TIM_AF__PA0__TCH_TMR8_EXT D(1, 8) +#define DEF_TIM_AF__PA2__TCH_TMR9_CH1 D(3, 9) +#define DEF_TIM_AF__PA3__TCH_TMR9_CH2 D(3, 9) +#define DEF_TIM_AF__PA5__TCH_TMR8_CH1N D(3, 8) +#define DEF_TIM_AF__PA7__TCH_TMR8_CH1N D(3, 8) - -//PORTB MUX 1 +// PORTB MUX 1 #define DEF_TIM_AF__PB0__TCH_TMR1_CH2N D(1, 1) #define DEF_TIM_AF__PB1__TCH_TMR1_CH3N D(1, 1) #define DEF_TIM_AF__PB2__TCH_TMR2_CH4 D(1, 2) @@ -338,28 +374,33 @@ #define DEF_TIM_AF__PB13__TCH_TMR1_CH1N D(1, 1) #define DEF_TIM_AF__PB14__TCH_TMR1_CH2N D(1, 1) #define DEF_TIM_AF__PB15__TCH_TMR1_CH3N D(1, 1) -//PORTB MUX 2 -#define DEF_TIM_AF__PB0__TCH_TMR3_CH3 D(2, 3) -#define DEF_TIM_AF__PB1__TCH_TMR3_CH4 D(2, 3) -#define DEF_TIM_AF__PB2__TCH_TMR20_CH1 D(2, 20) -#define DEF_TIM_AF__PB4__TCH_TMR3_CH1 D(2, 3) -#define DEF_TIM_AF__PB5__TCH_TMR3_CH2 D(2, 3) -#define DEF_TIM_AF__PB6__TCH_TMR4_CH1 D(2, 4) -#define DEF_TIM_AF__PB7__TCH_TMR4_CH2 D(2, 4) -#define DEF_TIM_AF__PB8__TCH_TMR4_CH3 D(2, 4) -#define DEF_TIM_AF__PB9__TCH_TMR4_CH4 D(2, 4) -#define DEF_TIM_AF__PB11__TCH_TMR5_CH4 D(2, 5) -#define DEF_TIM_AF__PB12__TCH_TMR5_CH1 D(2, 5) -//PORTB MUX 3 -#define DEF_TIM_AF__PB0__TCH_TMR8_CH2N D(3, 8) -#define DEF_TIM_AF__PB1__TCH_TMR8_CH3N D(3, 8) -#define DEF_TIM_AF__PB8__TCH_TMR10_CH1 D(3, 10) -#define DEF_TIM_AF__PB9__TCH_TMR11_CH1 D(3, 11) -#define DEF_TIM_AF__PB14__TCH_TMR8_CH2N D(3, 8) -#define DEF_TIM_AF__PB15__TCH_TMR8_CH3N D(3, 8) +// PORTB MUX 2 +#define DEF_TIM_AF__PB0__TCH_TMR3_CH3 D(2, 3) +#define DEF_TIM_AF__PB1__TCH_TMR3_CH4 D(2, 3) +#define DEF_TIM_AF__PB2__TCH_TMR20_CH1 D(2, 20) +#define DEF_TIM_AF__PB4__TCH_TMR3_CH1 D(2, 3) +#define DEF_TIM_AF__PB5__TCH_TMR3_CH2 D(2, 3) +#define DEF_TIM_AF__PB6__TCH_TMR4_CH1 D(2, 4) +#define DEF_TIM_AF__PB7__TCH_TMR4_CH2 D(2, 4) +#define DEF_TIM_AF__PB8__TCH_TMR4_CH3 D(2, 4) +#define DEF_TIM_AF__PB9__TCH_TMR4_CH4 D(2, 4) +#define DEF_TIM_AF__PB11__TCH_TMR5_CH4 D(2, 5) +#define DEF_TIM_AF__PB12__TCH_TMR5_CH1 D(2, 5) -//PORTC MUX 2 +// PORTB MUX 3 +#define DEF_TIM_AF__PB0__TCH_TMR8_CH2N D(3, 8) +#define DEF_TIM_AF__PB1__TCH_TMR8_CH3N D(3, 8) +#define DEF_TIM_AF__PB8__TCH_TMR10_CH1 D(3, 10) +#define DEF_TIM_AF__PB9__TCH_TMR11_CH1 D(3, 11) +#define DEF_TIM_AF__PB14__TCH_TMR8_CH2N D(3, 8) +#define DEF_TIM_AF__PB15__TCH_TMR8_CH3N D(3, 8) + +// PORTB MUX 9 +#define DEF_TIM_AF__PB14__TCH_TMR12_CH1 D(9, 12) +#define DEF_TIM_AF__PB15__TCH_TMR12_CH2 D(9, 12) + +// PORTC MUX 2 #define DEF_TIM_AF__PC2__TCH_TMR20_CH2 D(2, 20) #define DEF_TIM_AF__PC6__TCH_TMR3_CH1 D(2, 3) #define DEF_TIM_AF__PC7__TCH_TMR3_CH2 D(2, 3) @@ -368,39 +409,88 @@ #define DEF_TIM_AF__PC10__TCH_TMR5_CH2 D(2, 5) #define DEF_TIM_AF__PC11__TCH_TMR5_CH3 D(2, 5) -//PORTC MUX 3 +// PORTC MUX 3 +#define DEF_TIM_AF__PC4__TCH_TMR9_CH1 D(3, 9) +#define DEF_TIM_AF__PC5__TCH_TMR9_CH2 D(3, 9) +#define DEF_TIM_AF__PC6__TCH_TMR8_CH1 D(3, 8) +#define DEF_TIM_AF__PC7__TCH_TMR8_CH2 D(3, 8) +#define DEF_TIM_AF__PC8__TCH_TMR8_CH3 D(3, 8) +#define DEF_TIM_AF__PC9__TCH_TMR8_CH4 D(3, 8) +#define DEF_TIM_AF__PC12__TCH_TMR11_CH1N D(3, 11) -#define DEF_TIM_AF__PC4__TCH_TMR9_CH1 D(3, 9) -#define DEF_TIM_AF__PC5__TCH_TMR9_CH2 D(3, 9) -#define DEF_TIM_AF__PC6__TCH_TMR8_CH1 D(3, 8) -#define DEF_TIM_AF__PC7__TCH_TMR8_CH2 D(3, 8) -#define DEF_TIM_AF__PC8__TCH_TMR8_CH3 D(3, 8) -#define DEF_TIM_AF__PC9__TCH_TMR8_CH4 D(3, 8) -#define DEF_TIM_AF__PC12__TCH_TMR11_CH1N D(3, 11) +// PORTD MUX 2 +#define DEF_TIM_AF__PD12__TCH_TMR4_CH1 D(2, 4) +#define DEF_TIM_AF__PD13__TCH_TMR4_CH2 D(2, 4) +#define DEF_TIM_AF__PD14__TCH_TMR4_CH3 D(2, 4) +#define DEF_TIM_AF__PD15__TCH_TMR4_CH4 D(2, 4) +// PORTE MUX 1 +#define DEF_TIM_AF__PE1__TCH_TMR1_CH2N D(1, 1) +#define DEF_TIM_AF__PE7__TCH_TMR1_EXT D(1, 1) +#define DEF_TIM_AF__PE8__TCH_TMR1_CH1N D(1, 1) +#define DEF_TIM_AF__PE9__TCH_TMR1_CH1 D(1, 1) +#define DEF_TIM_AF__PE10__TCH_TMR1_CH2N D(1, 1) +#define DEF_TIM_AF__PE11__TCH_TMR1_CH2 D(1, 1) +#define DEF_TIM_AF__PE12__TCH_TMR1_CH3N D(1, 1) +#define DEF_TIM_AF__PE13__TCH_TMR1_CH3 D(1, 1) +#define DEF_TIM_AF__PE14__TCH_TMR1_CH4 D(1, 1) +#define DEF_TIM_AF__PE15__TCH_TMR1_BRK D(1, 1) -//PORTD MUX 2 -#define DEF_TIM_AF__PD12__TCH_TMR4_CH1 D(2, 4) -#define DEF_TIM_AF__PD13__TCH_TMR4_CH2 D(2, 4) -#define DEF_TIM_AF__PD14__TCH_TMR4_CH3 D(2, 4) -#define DEF_TIM_AF__PD15__TCH_TMR4_CH4 D(2, 4) +// PORTE MUX 2 +#define DEF_TIM_AF__PE0__TCH_TMR4_EXT D(2, 4) +#define DEF_TIM_AF__PE2__TCH_TMR3_EXT D(2, 3) +#define DEF_TIM_AF__PE3__TCH_TMR3_CH1 D(2, 3) +#define DEF_TIM_AF__PE4__TCH_TMR3_CH2 D(2, 3) +#define DEF_TIM_AF__PE5__TCH_TMR3_CH3 D(2, 3) +#define DEF_TIM_AF__PE6__TCH_TMR3_CH4 D(2, 3) -//PORTE MUX 1 -#define DEF_TIM_AF__PE1__TCH_TMR1_CH2N D(1, 1) -#define DEF_TIM_AF__PE8__TCH_TMR1_CH1N D(1, 1) -#define DEF_TIM_AF__PE9__TCH_TMR1_CH1 D(1, 1) -#define DEF_TIM_AF__PE10__TCH_TMR1_CH2N D(1, 1) -#define DEF_TIM_AF__PE11__TCH_TMR1_CH2 D(1, 1) -#define DEF_TIM_AF__PE12__TCH_TMR1_CH3N D(1, 1) -#define DEF_TIM_AF__PE13__TCH_TMR1_CH3 D(1, 1) -#define DEF_TIM_AF__PE14__TCH_TMR1_CH4 D(1, 1) +// PORTE MUX 3 +#define DEF_TIM_AF__PE5__TCH_TMR9_CH1 D(2, 9) +#define DEF_TIM_AF__PE6__TCH_TMR9_CH2 D(2, 9) -//PORTE MUX 2 -#define DEF_TIM_AF__PE3__TCH_TMR3_CH1 D(2, 3) -#define DEF_TIM_AF__PE4__TCH_TMR3_CH2 D(2, 3) -#define DEF_TIM_AF__PE5__TCH_TMR3_CH3 D(2, 3) -#define DEF_TIM_AF__PE6__TCH_TMR3_CH4 D(2, 3) +// PORTE MUX 6 +#define DEF_TIM_AF__PE0__TCH_TMR20_EXT D(6, 20) +#define DEF_TIM_AF__PE1__TCH_TMR20_CH4 D(6, 20) +#define DEF_TIM_AF__PE2__TCH_TMR20_CH1 D(6, 20) +#define DEF_TIM_AF__PE3__TCH_TMR20_CH2 D(6, 20) +#define DEF_TIM_AF__PE4__TCH_TMR20_CH1N D(6, 20) +#define DEF_TIM_AF__PE5__TCH_TMR20_CH2N D(6, 20) +#define DEF_TIM_AF__PE6__TCH_TMR20_CH3N D(6, 20) -//PORTE MUX 3 -#define DEF_TIM_AF__PE5__TCH_TMR9_CH1 D(2, 9) -#define DEF_TIM_AF__PE6__TCH_TMR9_CH2 D(2, 9) +// PORTF MUX 1 +#define DEF_TIM_AF__PF10__TCH_TMR1_EXT D(2, 1) + +// PORTF MUX 2 +#define DEF_TIM_AF__PF2__TCH_TMR20_CH3 D(2, 20) +#define DEF_TIM_AF__PF3__TCH_TMR20_CH4 D(2, 20) +#define DEF_TIM_AF__PF4__TCH_TMR20_CH1N D(2, 20) +#define DEF_TIM_AF__PF5__TCH_TMR20_CH2N D(2, 20) +#define DEF_TIM_AF__PF6__TCH_TMR20_CH4 D(2, 20) +#define DEF_TIM_AF__PF7__TCH_TMR20_BRK D(2, 20) +#define DEF_TIM_AF__PF9__TCH_TMR20_BRK D(2, 20) +#define DEF_TIM_AF__PF11__TCH_TMR20_EST D(2, 20) +#define DEF_TIM_AF__PF12__TCH_TMR20_CH1 D(2, 20) +#define DEF_TIM_AF__PF13__TCH_TMR20_CH2 D(2, 20) +#define DEF_TIM_AF__PF14__TCH_TMR20_CH3 D(2, 20) +#define DEF_TIM_AF__PF15__TCH_TMR20_CH4 D(2, 20) + +// PORTF MUX 3 +#define DEF_TIM_AF__PF6__TCH_TMR10_CH1 D(3, 10) +#define DEF_TIM_AF__PF7__TCH_TMR11_CH1 D(3, 11) +#define DEF_TIM_AF__PF11__TCH_TMR8_EST D(3, 8) +#define DEF_TIM_AF__PF12__TCH_TMR8_BRK D(3, 8) + +// PORTF MUX 9 +#define DEF_TIM_AF__PF8__TCH_TMR13_CH1 D(9, 13) +#define DEF_TIM_AF__PF9__TCH_TMR14_CH1 D(9, 14) + +// PORTG MUX 2 +#define DEF_TIM_AF__PG0__TCH_TMR20_CH1N D(2, 20) +#define DEF_TIM_AF__PG1__TCH_TMR20_CH2N D(2, 20) +#define DEF_TIM_AF__PG2__TCH_TMR20_CH3N D(2, 20) +#define DEF_TIM_AF__PG3__TCH_TMR20_BRK D(2, 20) +#define DEF_TIM_AF__PG5__TCH_TMR20_EXT D(2, 20) + +// PORTH MUX 2 +#define DEF_TIM_AF__PH2__TCH_TMR5_CH1 D(2, 5) +#define DEF_TIM_AF__PH3__TCH_TMR5_CH2 D(2, 5) diff --git a/src/main/drivers/stm32/timer_def.h b/src/main/drivers/stm32/timer_def.h index ca3166f844..3c3bce48e7 100644 --- a/src/main/drivers/stm32/timer_def.h +++ b/src/main/drivers/stm32/timer_def.h @@ -833,11 +833,11 @@ (DEF_TIM_OUTPUT(CH_ ## chan) | out), \ DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \ DEF_TIM_DMA_COND(/* add comma */ , \ - DEF_TIM_DMA_CHANNEL(dmaopt, TCH_## tim ## _ ## chan), \ + DEF_TIM_DMA_CHANNEL(dmaopt, TCH_## tim ## _ ## chan), \ DEF_TIM_DMA_REQUEST(TCH_## tim ## _ ## chan) \ ) \ DEF_TIM_DMA_COND(/* add comma */ , \ - DEF_TIM_DMA_CHANNEL(upopt, TCH_## tim ## _UP), \ + DEF_TIM_DMA_CHANNEL(upopt, TCH_## tim ## _UP), \ DEF_TIM_DMA_REQUEST(TCH_## tim ## _UP), \ DEF_TIM_DMA_HANDLER(upopt, TCH_## tim ## _UP) \ ) \