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Code Issues Wiki Activity

Disable F7 D-cache until more knowledge is acquired

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This commit is contained in:
Sami Korhonen 2017-02-14 20:13:17 +02:00 • committed by borisbstyle
parent a135e9cbb2
commit 1102df5d68
5 changed files with 8 additions and 8 deletions
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2
src/main/drivers/adc_stm32f7xx.c
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@ -193,7 +193,7 @@ void adcInit(adcConfig_t *config)
} }
} }
HAL_CLEANINVALIDATECACHE((uint32_t*)&adcValues, configuredAdcChannels); //HAL_CLEANINVALIDATECACHE((uint32_t*)&adcValues, configuredAdcChannels);
/*##-4- Start the conversion process #######################################*/ /*##-4- Start the conversion process #######################################*/
if(HAL_ADC_Start_DMA(&adc.ADCHandle, (uint32_t*)&adcValues, configuredAdcChannels) != HAL_OK) if(HAL_ADC_Start_DMA(&adc.ADCHandle, (uint32_t*)&adcValues, configuredAdcChannels) != HAL_OK)
{ {

2
src/main/drivers/bus_spi_hal.c
View file

@ -390,7 +390,7 @@ DMA_HandleTypeDef* spiSetDMATransmit(DMA_Stream_TypeDef *Stream, uint32_t Channe
// DMA TX Interrupt // DMA TX Interrupt
dmaSetHandler(spiHardwareMap[device].dmaIrqHandler, dmaSPIIRQHandler, NVIC_BUILD_PRIORITY(3, 0), (uint32_t)device); dmaSetHandler(spiHardwareMap[device].dmaIrqHandler, dmaSPIIRQHandler, NVIC_BUILD_PRIORITY(3, 0), (uint32_t)device);
HAL_CLEANCACHE(pData,Size); //HAL_CLEANCACHE(pData,Size);
// And Transmit // And Transmit
HAL_SPI_Transmit_DMA(&spiHardwareMap[device].hspi, pData, Size); HAL_SPI_Transmit_DMA(&spiHardwareMap[device].hspi, pData, Size);

4
src/main/drivers/dma.h
View file

@ -39,8 +39,8 @@ typedef struct dmaChannelDescriptor_s {
} dmaChannelDescriptor_t; } dmaChannelDescriptor_t;
#if defined(STM32F7) #if defined(STM32F7)
#define HAL_CLEANINVALIDATECACHE(addr, size) (SCB_CleanInvalidateDCache_by_Addr((uint32_t*)((uint32_t)addr & ~0x1f), ((uint32_t)(addr + size + 0x1f) & ~0x1f) - ((uint32_t)addr & ~0x1f))) //#define HAL_CLEANINVALIDATECACHE(addr, size) (SCB_CleanInvalidateDCache_by_Addr((uint32_t*)((uint32_t)addr & ~0x1f), ((uint32_t)(addr + size + 0x1f) & ~0x1f) - ((uint32_t)addr & ~0x1f)))
#define HAL_CLEANCACHE(addr, size) (SCB_CleanDCache_by_Addr((uint32_t*)((uint32_t)addr & ~0x1f), ((uint32_t)(addr + size + 0x1f) & ~0x1f) - ((uint32_t)addr & ~0x1f))) //#define HAL_CLEANCACHE(addr, size) (SCB_CleanDCache_by_Addr((uint32_t*)((uint32_t)addr & ~0x1f), ((uint32_t)(addr + size + 0x1f) & ~0x1f) - ((uint32_t)addr & ~0x1f)))
#endif #endif
#if defined(STM32F4) || defined(STM32F7) #if defined(STM32F4) || defined(STM32F7)

2
src/main/drivers/serial_uart_hal.c
View file

@ -266,7 +266,7 @@ void uartStartTxDMA(uartPort_t *s)
s->port.txBufferTail = 0; s->port.txBufferTail = 0;
} }
s->txDMAEmpty = false; s->txDMAEmpty = false;
HAL_CLEANCACHE((uint8_t *)&s->port.txBuffer[fromwhere],size); //HAL_CLEANCACHE((uint8_t *)&s->port.txBuffer[fromwhere],size);
HAL_UART_Transmit_DMA(&s->Handle, (uint8_t *)&s->port.txBuffer[fromwhere], size); HAL_UART_Transmit_DMA(&s->Handle, (uint8_t *)&s->port.txBuffer[fromwhere], size);
} }

6
src/main/target/system_stm32f7xx.c
View file

@ -283,14 +283,14 @@ void SystemInit(void)
SCB_EnableICache(); SCB_EnableICache();
/* Enable D-Cache */ /* Enable D-Cache */
SCB_EnableDCache(); //SCB_EnableDCache();
/* Configure the system clock to 216 MHz */ /* Configure the system clock to 216 MHz */
SystemClock_Config(); SystemClock_Config();
//if(SystemCoreClock != 260000000) if(SystemCoreClock != 216000000)
{ {
//while(1) while(1)
{ {
// There is a mismatch between the configured clock and the expected clock in portable.h // There is a mismatch between the configured clock and the expected clock in portable.h
} }