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Initiate APM32F40X MCU Support in Betaflight (#13709)

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* Add APM32F4 driver libraries and USB middleware
* Remove all duplicated APM32 driver files and retaining only the APM32 LIB directory
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Morro 2024-06-28 13:03:34 +08:00 • committed by GitHub
parent 2ff71b0a1f
commit 14bcc13150
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/**
*
* @file apm32f4xx.h
*
* @brief CMSIS APM32F4xx Device Peripheral Access Layer Header File.
*
* @version V1.1.2
*
* @date 2023-12-01
*
* @attention
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* The original code has been modified by Geehy Semiconductor.
*
* Copyright (c) 2017 STMicroelectronics.
* Copyright (C) 2023 Geehy Semiconductor.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup apm32f4xx
* @{
*/
#ifndef __APM32F4xx_H
#define __APM32F4xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief APM32 Family
*/
#if !defined (APM32F4)
#define APM32F4
#endif /* APM32F4 */
/* Uncomment the line below according to the target APM32 device used in your
application
*/
#if !defined (APM32F405xx) && !defined (APM32F407xx) && !defined (APM32F417xx) && \
!defined (APM32F411xx) && !defined (APM32F465xx)
/* #define APM32F405xx */ /*!< APM32F405RG, APM32F405VG and APM32F405ZG Devices */
/* #define APM32F407xx */ /*!< APM32F407VG, APM32F407VE, APM32F407ZG, APM32F407ZE, APM32F407IG and APM32F407IE Devices */
/* #define APM32F417xx */ /*!< APM32F417VG, APM32F417VE, APM32F417ZG, APM32F417ZE, APM32F417IG and APM32F417IE Devices */
/* #define APM32F411xx */ /*!< APM32F411CC, APM32F411CE, APM32F411RC, APM32F411RE, APM32F411VC and APM32F411VE Devices */
/* #define APM32F465xx */ /*!< APM32F465CE, APM32F465RE and APM32F465VE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_DAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_DAL_DRIVER */
#endif /* USE_DAL_DRIVER */
/**
* @brief CMSIS version number V1.1.2
*/
#define __APM32F4xx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __APM32F4xx_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __APM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __APM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __APM32F4xx_CMSIS_VERSION ((__APM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__APM32F4xx_CMSIS_VERSION_SUB1 << 16)\
|(__APM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
|(__APM32F4xx_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(APM32F405xx)
#include "apm32f405xx.h"
#elif defined(APM32F407xx)
#include "apm32f407xx.h"
#elif defined(APM32F417xx)
#include "apm32f417xx.h"
#elif defined(APM32F411xx)
#include "apm32f411xx.h"
#elif defined(APM32F465xx)
#include "apm32f465xx.h"
#else
#error "Please select first the target APM32F4xx device used in your application (in apm32f4xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0U,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macro
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t val; \
do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \
uint16_t val; \
do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/**
* @}
*/
#if defined (USE_DAL_DRIVER)
#include "apm32f4xx_dal.h"
#endif /* USE_DAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __APM32F4xx_H */
/**
* @}
*/
/**
* @}
*/

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This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the Apache-2.0 license shall apply.
You may obtain a copy of the Apache-2.0 at:
https://opensource.org/licenses/Apache-2.0

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;/**
; * @file startup_apm32f405xx.s
; *
; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f405xx
; *
; * @version V1.0.0
; *
; * @date 2023-07-31
; *
; * @attention
; *
; * Copyright (C) 2023 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <<< Use Configuration Wizard in Context Menu >>>
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EINT Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EINT line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EINT line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line0
DCD EINT1_IRQHandler ; EINT Line1
DCD EINT2_IRQHandler ; EINT Line2
DCD EINT3_IRQHandler ; EINT Line3
DCD EINT4_IRQHandler ; EINT Line4
DCD DMA1_STR0_IRQHandler ; DMA1 Stream 0
DCD DMA1_STR1_IRQHandler ; DMA1 Stream 1
DCD DMA1_STR2_IRQHandler ; DMA1 Stream 2
DCD DMA1_STR3_IRQHandler ; DMA1 Stream 3
DCD DMA1_STR4_IRQHandler ; DMA1 Stream 4
DCD DMA1_STR5_IRQHandler ; DMA1 Stream 5
DCD DMA1_STR6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; External Line[9:5]s
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
DCD TMR1_UP_TMR10_IRQHandler ; TMR1 Update and TMR10
DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EINT Line
DCD OTG_FS_WKUP_IRQHandler ; OTG_FS Wakeup through EINT line
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
DCD TMR8_UP_TMR13_IRQHandler ; TMR8 Update and TMR13
DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD DMA1_STR7_IRQHandler ; DMA1 Stream 7
DCD EMMC_IRQHandler ; EMMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_DAC_IRQHandler ; TMR6 and DAC1&2 underrun errors
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; OTG_FS
DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS1_EP1_OUT_IRQHandler ; OTG_HS1 End Point 1 Out
DCD OTG_HS1_EP1_IN_IRQHandler ; OTG_HS1 End Point 1 In
DCD OTG_HS1_WKUP_IRQHandler ; OTG_HS1 Wakeup through EINT
DCD OTG_HS1_IRQHandler ; OTG_HS1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD SM3_IRQHandler ; SM3
DCD SM4_IRQHandler ; SM4
DCD BN_IRQHandler ; BN
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT DMA1_STR0_IRQHandler [WEAK]
EXPORT DMA1_STR1_IRQHandler [WEAK]
EXPORT DMA1_STR2_IRQHandler [WEAK]
EXPORT DMA1_STR3_IRQHandler [WEAK]
EXPORT DMA1_STR4_IRQHandler [WEAK]
EXPORT DMA1_STR5_IRQHandler [WEAK]
EXPORT DMA1_STR6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EINT9_5_IRQHandler [WEAK]
EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
EXPORT TMR1_UP_TMR10_IRQHandler [WEAK]
EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EINT15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
EXPORT TMR8_UP_TMR13_IRQHandler [WEAK]
EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
EXPORT TMR8_CC_IRQHandler [WEAK]
EXPORT DMA1_STR7_IRQHandler [WEAK]
EXPORT EMMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TMR5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TMR6_DAC_IRQHandler [WEAK]
EXPORT TMR7_IRQHandler [WEAK]
EXPORT DMA2_STR0_IRQHandler [WEAK]
EXPORT DMA2_STR1_IRQHandler [WEAK]
EXPORT DMA2_STR2_IRQHandler [WEAK]
EXPORT DMA2_STR3_IRQHandler [WEAK]
EXPORT DMA2_STR4_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_STR5_IRQHandler [WEAK]
EXPORT DMA2_STR6_IRQHandler [WEAK]
EXPORT DMA2_STR7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS1_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS1_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS1_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS1_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT SM3_IRQHandler [WEAK]
EXPORT SM4_IRQHandler [WEAK]
EXPORT BN_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
DMA1_STR0_IRQHandler
DMA1_STR1_IRQHandler
DMA1_STR2_IRQHandler
DMA1_STR3_IRQHandler
DMA1_STR4_IRQHandler
DMA1_STR5_IRQHandler
DMA1_STR6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EINT9_5_IRQHandler
TMR1_BRK_TMR9_IRQHandler
TMR1_UP_TMR10_IRQHandler
TMR1_TRG_COM_TMR11_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EINT15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TMR8_BRK_TMR12_IRQHandler
TMR8_UP_TMR13_IRQHandler
TMR8_TRG_COM_TMR14_IRQHandler
TMR8_CC_IRQHandler
DMA1_STR7_IRQHandler
EMMC_IRQHandler
SDIO_IRQHandler
TMR5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TMR6_DAC_IRQHandler
TMR7_IRQHandler
DMA2_STR0_IRQHandler
DMA2_STR1_IRQHandler
DMA2_STR2_IRQHandler
DMA2_STR3_IRQHandler
DMA2_STR4_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_STR5_IRQHandler
DMA2_STR6_IRQHandler
DMA2_STR7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS1_EP1_OUT_IRQHandler
OTG_HS1_EP1_IN_IRQHandler
OTG_HS1_WKUP_IRQHandler
OTG_HS1_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
SM3_IRQHandler
SM4_IRQHandler
BN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT Geehy Semiconductor Co.,Ltd *****END OF FILE*****

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;/**
; * @file startup_apm32f407xx.s
; *
; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f407xx
; *
; * @version V1.0.0
; *
; * @date 2023-07-31
; *
; * @attention
; *
; * Copyright (C) 2023 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <<< Use Configuration Wizard in Context Menu >>>
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EINT Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EINT line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EINT line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line0
DCD EINT1_IRQHandler ; EINT Line1
DCD EINT2_IRQHandler ; EINT Line2
DCD EINT3_IRQHandler ; EINT Line3
DCD EINT4_IRQHandler ; EINT Line4
DCD DMA1_STR0_IRQHandler ; DMA1 Stream 0
DCD DMA1_STR1_IRQHandler ; DMA1 Stream 1
DCD DMA1_STR2_IRQHandler ; DMA1 Stream 2
DCD DMA1_STR3_IRQHandler ; DMA1 Stream 3
DCD DMA1_STR4_IRQHandler ; DMA1 Stream 4
DCD DMA1_STR5_IRQHandler ; DMA1 Stream 5
DCD DMA1_STR6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; External Line[9:5]s
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
DCD TMR1_UP_TMR10_IRQHandler ; TMR1 Update and TMR10
DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EINT Line
DCD OTG_FS_WKUP_IRQHandler ; OTG_FS Wakeup through EINT line
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
DCD TMR8_UP_TMR13_IRQHandler ; TMR8 Update and TMR13
DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD DMA1_STR7_IRQHandler ; DMA1 Stream 7
DCD EMMC_IRQHandler ; EMMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_DAC_IRQHandler ; TMR6 and DAC1&2 underrun errors
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EINT line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; OTG_FS
DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS1_EP1_OUT_IRQHandler ; OTG_HS1 End Point 1 Out
DCD OTG_HS1_EP1_IN_IRQHandler ; OTG_HS1 End Point 1 In
DCD OTG_HS1_WKUP_IRQHandler ; OTG_HS1 Wakeup through EINT
DCD OTG_HS1_IRQHandler ; OTG_HS1
DCD DCI_IRQHandler ; DCI
DCD 0 ; Reserved
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD SM3_IRQHandler ; SM3
DCD SM4_IRQHandler ; SM4
DCD BN_IRQHandler ; BN
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT DMA1_STR0_IRQHandler [WEAK]
EXPORT DMA1_STR1_IRQHandler [WEAK]
EXPORT DMA1_STR2_IRQHandler [WEAK]
EXPORT DMA1_STR3_IRQHandler [WEAK]
EXPORT DMA1_STR4_IRQHandler [WEAK]
EXPORT DMA1_STR5_IRQHandler [WEAK]
EXPORT DMA1_STR6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EINT9_5_IRQHandler [WEAK]
EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
EXPORT TMR1_UP_TMR10_IRQHandler [WEAK]
EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EINT15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
EXPORT TMR8_UP_TMR13_IRQHandler [WEAK]
EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
EXPORT TMR8_CC_IRQHandler [WEAK]
EXPORT DMA1_STR7_IRQHandler [WEAK]
EXPORT EMMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TMR5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TMR6_DAC_IRQHandler [WEAK]
EXPORT TMR7_IRQHandler [WEAK]
EXPORT DMA2_STR0_IRQHandler [WEAK]
EXPORT DMA2_STR1_IRQHandler [WEAK]
EXPORT DMA2_STR2_IRQHandler [WEAK]
EXPORT DMA2_STR3_IRQHandler [WEAK]
EXPORT DMA2_STR4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_STR5_IRQHandler [WEAK]
EXPORT DMA2_STR6_IRQHandler [WEAK]
EXPORT DMA2_STR7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS1_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS1_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS1_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS1_IRQHandler [WEAK]
EXPORT DCI_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT SM3_IRQHandler [WEAK]
EXPORT SM4_IRQHandler [WEAK]
EXPORT BN_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
DMA1_STR0_IRQHandler
DMA1_STR1_IRQHandler
DMA1_STR2_IRQHandler
DMA1_STR3_IRQHandler
DMA1_STR4_IRQHandler
DMA1_STR5_IRQHandler
DMA1_STR6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EINT9_5_IRQHandler
TMR1_BRK_TMR9_IRQHandler
TMR1_UP_TMR10_IRQHandler
TMR1_TRG_COM_TMR11_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EINT15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TMR8_BRK_TMR12_IRQHandler
TMR8_UP_TMR13_IRQHandler
TMR8_TRG_COM_TMR14_IRQHandler
TMR8_CC_IRQHandler
DMA1_STR7_IRQHandler
EMMC_IRQHandler
SDIO_IRQHandler
TMR5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TMR6_DAC_IRQHandler
TMR7_IRQHandler
DMA2_STR0_IRQHandler
DMA2_STR1_IRQHandler
DMA2_STR2_IRQHandler
DMA2_STR3_IRQHandler
DMA2_STR4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_STR5_IRQHandler
DMA2_STR6_IRQHandler
DMA2_STR7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS1_EP1_OUT_IRQHandler
OTG_HS1_EP1_IN_IRQHandler
OTG_HS1_WKUP_IRQHandler
OTG_HS1_IRQHandler
DCI_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
SM3_IRQHandler
SM4_IRQHandler
BN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT Geehy Semiconductor Co.,Ltd *****END OF FILE*****

410
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/arm/startup_apm32f411xx.s Normal file
View file

@ -0,0 +1,410 @@
;/**
; * @file startup_apm32f411xx.s
; *
; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f411xx
; *
; * @version V1.0.0
; *
; * @date 2023-12-01
; *
; * @attention
; *
; * Copyright (C) 2023 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <<< Use Configuration Wizard in Context Menu >>>
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EINT Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EINT line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EINT line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line0
DCD EINT1_IRQHandler ; EINT Line1
DCD EINT2_IRQHandler ; EINT Line2
DCD EINT3_IRQHandler ; EINT Line3
DCD EINT4_IRQHandler ; EINT Line4
DCD DMA1_STR0_IRQHandler ; DMA1 Stream 0
DCD DMA1_STR1_IRQHandler ; DMA1 Stream 1
DCD DMA1_STR2_IRQHandler ; DMA1 Stream 2
DCD DMA1_STR3_IRQHandler ; DMA1 Stream 3
DCD DMA1_STR4_IRQHandler ; DMA1 Stream 4
DCD DMA1_STR5_IRQHandler ; DMA1 Stream 5
DCD DMA1_STR6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; External Line[9:5]s
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
DCD TMR1_UP_TMR10_IRQHandler ; TMR1 Update and TMR10
DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EINT Line
DCD OTG_FS_WKUP_IRQHandler ; OTG_FS Wakeup through EINT line
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
DCD TMR8_UP_TMR13_IRQHandler ; TMR8 Update and TMR13
DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD DMA1_STR7_IRQHandler ; DMA1 Stream 7
DCD SMC_IRQHandler ; SMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; OTG_FS
DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD QSPI_IRQHandler ; QSPI
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT DMA1_STR0_IRQHandler [WEAK]
EXPORT DMA1_STR1_IRQHandler [WEAK]
EXPORT DMA1_STR2_IRQHandler [WEAK]
EXPORT DMA1_STR3_IRQHandler [WEAK]
EXPORT DMA1_STR4_IRQHandler [WEAK]
EXPORT DMA1_STR5_IRQHandler [WEAK]
EXPORT DMA1_STR6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EINT9_5_IRQHandler [WEAK]
EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
EXPORT TMR1_UP_TMR10_IRQHandler [WEAK]
EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EINT15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
EXPORT TMR8_UP_TMR13_IRQHandler [WEAK]
EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
EXPORT TMR8_CC_IRQHandler [WEAK]
EXPORT DMA1_STR7_IRQHandler [WEAK]
EXPORT SMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TMR5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT DMA2_STR0_IRQHandler [WEAK]
EXPORT DMA2_STR1_IRQHandler [WEAK]
EXPORT DMA2_STR2_IRQHandler [WEAK]
EXPORT DMA2_STR3_IRQHandler [WEAK]
EXPORT DMA2_STR4_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_STR5_IRQHandler [WEAK]
EXPORT DMA2_STR6_IRQHandler [WEAK]
EXPORT DMA2_STR7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT QSPI_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
DMA1_STR0_IRQHandler
DMA1_STR1_IRQHandler
DMA1_STR2_IRQHandler
DMA1_STR3_IRQHandler
DMA1_STR4_IRQHandler
DMA1_STR5_IRQHandler
DMA1_STR6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EINT9_5_IRQHandler
TMR1_BRK_TMR9_IRQHandler
TMR1_UP_TMR10_IRQHandler
TMR1_TRG_COM_TMR11_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EINT15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TMR8_BRK_TMR12_IRQHandler
TMR8_UP_TMR13_IRQHandler
TMR8_TRG_COM_TMR14_IRQHandler
TMR8_CC_IRQHandler
DMA1_STR7_IRQHandler
SMC_IRQHandler
SDIO_IRQHandler
TMR5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
DMA2_STR0_IRQHandler
DMA2_STR1_IRQHandler
DMA2_STR2_IRQHandler
DMA2_STR3_IRQHandler
DMA2_STR4_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_STR5_IRQHandler
DMA2_STR6_IRQHandler
DMA2_STR7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
QSPI_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT Geehy Semiconductor Co.,Ltd *****END OF FILE*****

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@ -0,0 +1,428 @@
;/**
; * @file startup_apm32f417xx.s
; *
; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f417xx
; *
; * @version V1.0.0
; *
; * @date 2023-07-31
; *
; * @attention
; *
; * Copyright (C) 2023 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <<< Use Configuration Wizard in Context Menu >>>
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EINT Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EINT line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EINT line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line0
DCD EINT1_IRQHandler ; EINT Line1
DCD EINT2_IRQHandler ; EINT Line2
DCD EINT3_IRQHandler ; EINT Line3
DCD EINT4_IRQHandler ; EINT Line4
DCD DMA1_STR0_IRQHandler ; DMA1 Stream 0
DCD DMA1_STR1_IRQHandler ; DMA1 Stream 1
DCD DMA1_STR2_IRQHandler ; DMA1 Stream 2
DCD DMA1_STR3_IRQHandler ; DMA1 Stream 3
DCD DMA1_STR4_IRQHandler ; DMA1 Stream 4
DCD DMA1_STR5_IRQHandler ; DMA1 Stream 5
DCD DMA1_STR6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; External Line[9:5]s
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
DCD TMR1_UP_TMR10_IRQHandler ; TMR1 Update and TMR10
DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EINT Line
DCD OTG_FS_WKUP_IRQHandler ; OTG_FS Wakeup through EINT line
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
DCD TMR8_UP_TMR13_IRQHandler ; TMR8 Update and TMR13
DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD DMA1_STR7_IRQHandler ; DMA1 Stream 7
DCD EMMC_IRQHandler ; EMMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_DAC_IRQHandler ; TMR6 and DAC1&2 underrun errors
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EINT line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; OTG_FS
DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS1_EP1_OUT_IRQHandler ; OTG_HS1 End Point 1 Out
DCD OTG_HS1_EP1_IN_IRQHandler ; OTG_HS1 End Point 1 In
DCD OTG_HS1_WKUP_IRQHandler ; OTG_HS1 Wakeup through EINT
DCD OTG_HS1_IRQHandler ; OTG_HS1
DCD DCI_IRQHandler ; DCI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD SM3_IRQHandler ; SM3
DCD SM4_IRQHandler ; SM4
DCD BN_IRQHandler ; BN
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT DMA1_STR0_IRQHandler [WEAK]
EXPORT DMA1_STR1_IRQHandler [WEAK]
EXPORT DMA1_STR2_IRQHandler [WEAK]
EXPORT DMA1_STR3_IRQHandler [WEAK]
EXPORT DMA1_STR4_IRQHandler [WEAK]
EXPORT DMA1_STR5_IRQHandler [WEAK]
EXPORT DMA1_STR6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EINT9_5_IRQHandler [WEAK]
EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
EXPORT TMR1_UP_TMR10_IRQHandler [WEAK]
EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EINT15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
EXPORT TMR8_UP_TMR13_IRQHandler [WEAK]
EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
EXPORT TMR8_CC_IRQHandler [WEAK]
EXPORT DMA1_STR7_IRQHandler [WEAK]
EXPORT EMMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TMR5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TMR6_DAC_IRQHandler [WEAK]
EXPORT TMR7_IRQHandler [WEAK]
EXPORT DMA2_STR0_IRQHandler [WEAK]
EXPORT DMA2_STR1_IRQHandler [WEAK]
EXPORT DMA2_STR2_IRQHandler [WEAK]
EXPORT DMA2_STR3_IRQHandler [WEAK]
EXPORT DMA2_STR4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_STR5_IRQHandler [WEAK]
EXPORT DMA2_STR6_IRQHandler [WEAK]
EXPORT DMA2_STR7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS1_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS1_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS1_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS1_IRQHandler [WEAK]
EXPORT DCI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT SM3_IRQHandler [WEAK]
EXPORT SM4_IRQHandler [WEAK]
EXPORT BN_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
DMA1_STR0_IRQHandler
DMA1_STR1_IRQHandler
DMA1_STR2_IRQHandler
DMA1_STR3_IRQHandler
DMA1_STR4_IRQHandler
DMA1_STR5_IRQHandler
DMA1_STR6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EINT9_5_IRQHandler
TMR1_BRK_TMR9_IRQHandler
TMR1_UP_TMR10_IRQHandler
TMR1_TRG_COM_TMR11_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EINT15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TMR8_BRK_TMR12_IRQHandler
TMR8_UP_TMR13_IRQHandler
TMR8_TRG_COM_TMR14_IRQHandler
TMR8_CC_IRQHandler
DMA1_STR7_IRQHandler
EMMC_IRQHandler
SDIO_IRQHandler
TMR5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TMR6_DAC_IRQHandler
TMR7_IRQHandler
DMA2_STR0_IRQHandler
DMA2_STR1_IRQHandler
DMA2_STR2_IRQHandler
DMA2_STR3_IRQHandler
DMA2_STR4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_STR5_IRQHandler
DMA2_STR6_IRQHandler
DMA2_STR7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS1_EP1_OUT_IRQHandler
OTG_HS1_EP1_IN_IRQHandler
OTG_HS1_WKUP_IRQHandler
OTG_HS1_IRQHandler
DCI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
SM3_IRQHandler
SM4_IRQHandler
BN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT Geehy Semiconductor Co.,Ltd *****END OF FILE*****

421
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@ -0,0 +1,421 @@
;/**
; * @file startup_apm32f465xx.s
; *
; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f465xx
; *
; * @version V1.0.0
; *
; * @date 2023-12-01
; *
; * @attention
; *
; * Copyright (C) 2023 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <<< Use Configuration Wizard in Context Menu >>>
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EINT Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EINT line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EINT line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line0
DCD EINT1_IRQHandler ; EINT Line1
DCD EINT2_IRQHandler ; EINT Line2
DCD EINT3_IRQHandler ; EINT Line3
DCD EINT4_IRQHandler ; EINT Line4
DCD DMA1_STR0_IRQHandler ; DMA1 Stream 0
DCD DMA1_STR1_IRQHandler ; DMA1 Stream 1
DCD DMA1_STR2_IRQHandler ; DMA1 Stream 2
DCD DMA1_STR3_IRQHandler ; DMA1 Stream 3
DCD DMA1_STR4_IRQHandler ; DMA1 Stream 4
DCD DMA1_STR5_IRQHandler ; DMA1 Stream 5
DCD DMA1_STR6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; External Line[9:5]s
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
DCD TMR1_UP_TMR10_IRQHandler ; TMR1 Update and TMR10
DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EINT Line
DCD OTG_FS_WKUP_IRQHandler ; OTG_FS Wakeup through EINT line
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
DCD TMR8_UP_TMR13_IRQHandler ; TMR8 Update and TMR13
DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD DMA1_STR7_IRQHandler ; DMA1 Stream 7
DCD SMC_IRQHandler ; SMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_DAC_IRQHandler ; TMR6 and DAC1&2 underrun errors
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; OTG_FS
DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS1_EP1_OUT_IRQHandler ; OTG_HS1 End Point 1 Out
DCD OTG_HS1_EP1_IN_IRQHandler ; OTG_HS1 End Point 1 In
DCD OTG_HS1_WKUP_IRQHandler ; OTG_HS1 Wakeup through EINT
DCD OTG_HS1_IRQHandler ; OTG_HS1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG
DCD FPU_IRQHandler ; FPU
DCD SM3_IRQHandler ; SM3
DCD SM4_IRQHandler ; SM4
DCD BN_IRQHandler ; BN
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT DMA1_STR0_IRQHandler [WEAK]
EXPORT DMA1_STR1_IRQHandler [WEAK]
EXPORT DMA1_STR2_IRQHandler [WEAK]
EXPORT DMA1_STR3_IRQHandler [WEAK]
EXPORT DMA1_STR4_IRQHandler [WEAK]
EXPORT DMA1_STR5_IRQHandler [WEAK]
EXPORT DMA1_STR6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EINT9_5_IRQHandler [WEAK]
EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
EXPORT TMR1_UP_TMR10_IRQHandler [WEAK]
EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EINT15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
EXPORT TMR8_UP_TMR13_IRQHandler [WEAK]
EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
EXPORT TMR8_CC_IRQHandler [WEAK]
EXPORT DMA1_STR7_IRQHandler [WEAK]
EXPORT SMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TMR5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TMR6_DAC_IRQHandler [WEAK]
EXPORT TMR7_IRQHandler [WEAK]
EXPORT DMA2_STR0_IRQHandler [WEAK]
EXPORT DMA2_STR1_IRQHandler [WEAK]
EXPORT DMA2_STR2_IRQHandler [WEAK]
EXPORT DMA2_STR3_IRQHandler [WEAK]
EXPORT DMA2_STR4_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_STR5_IRQHandler [WEAK]
EXPORT DMA2_STR6_IRQHandler [WEAK]
EXPORT DMA2_STR7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS1_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS1_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS1_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS1_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT SM3_IRQHandler [WEAK]
EXPORT SM4_IRQHandler [WEAK]
EXPORT BN_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
DMA1_STR0_IRQHandler
DMA1_STR1_IRQHandler
DMA1_STR2_IRQHandler
DMA1_STR3_IRQHandler
DMA1_STR4_IRQHandler
DMA1_STR5_IRQHandler
DMA1_STR6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EINT9_5_IRQHandler
TMR1_BRK_TMR9_IRQHandler
TMR1_UP_TMR10_IRQHandler
TMR1_TRG_COM_TMR11_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EINT15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TMR8_BRK_TMR12_IRQHandler
TMR8_UP_TMR13_IRQHandler
TMR8_TRG_COM_TMR14_IRQHandler
TMR8_CC_IRQHandler
DMA1_STR7_IRQHandler
SMC_IRQHandler
SDIO_IRQHandler
TMR5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TMR6_DAC_IRQHandler
TMR7_IRQHandler
DMA2_STR0_IRQHandler
DMA2_STR1_IRQHandler
DMA2_STR2_IRQHandler
DMA2_STR3_IRQHandler
DMA2_STR4_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_STR5_IRQHandler
DMA2_STR6_IRQHandler
DMA2_STR7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS1_EP1_OUT_IRQHandler
OTG_HS1_EP1_IN_IRQHandler
OTG_HS1_WKUP_IRQHandler
OTG_HS1_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
SM3_IRQHandler
SM4_IRQHandler
BN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT Geehy Semiconductor Co.,Ltd *****END OF FILE*****

183
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@ -0,0 +1,183 @@
/**
* @file apm32f405xe_flash.ld
*
* @brief Linker script for APM32F4xxxE series
* 512Kbytes FLASH, 128KByte RAM, 64KByte CCMRAM
*
* @version V1.0.0
*
* @date 2023-07-31
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Flash Configuration*/
/* Flash Base Address */
_rom_base = 0x8000000;
/*Flash Size (in Bytes) */
_rom_size = 0x0080000;
/* Embedded RAM Configuration */
/* RAM Base Address */
_ram_base = 0x20000000;
/* RAM Size (in Bytes) */
_ram_size = 0x00020000;
/* CCMRAM Base Address */
_ccmram_base = 0x10000000;
/* CCMRAM Size (in Bytes) */
_ccmram_size = 0x00010000;
/* Stack / Heap Configuration */
_end_stack = 0x20020000;
/* Heap Size (in Bytes) */
_heap_size = 0x200;
/* Stack Size (in Bytes) */
_stack_size = 0x400;
MEMORY
{
FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size
RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
CCMRAM (xrw) : ORIGIN = _ccmram_base, LENGTH = _ccmram_size
}
SECTIONS
{
.apm32_isr_vector :
{
. = ALIGN(4);
KEEP(*(.apm32_isr_vector))
. = ALIGN(4);
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .;
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
_start_address_init_data = LOADADDR(.data);
.data :
{
. = ALIGN(4);
_start_address_data = .;
*(.data)
*(.data*)
. = ALIGN(4);
_end_address_data = .;
} >RAM AT> FLASH
_siccmram = LOADADDR(.ccmram);
.ccmram :
{
. = ALIGN(4);
_sccmram = .;
*(.ccmram)
*(.ccmram*)
. = ALIGN(4);
_eccmram = .;
} >CCMRAM AT> FLASH
. = ALIGN(4);
.bss :
{
_start_address_bss = .;
__bss_start__ = _start_address_bss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_address_bss = .;
__bss_end__ = _end_address_bss;
} >RAM
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _heap_size;
. = . + _stack_size;
. = ALIGN(8);
} >RAM
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

183
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/**
* @file apm32f405xg_flash.ld
*
* @brief Linker script for APM32F4xxxG series
* 1024Kbytes FLASH, 128KByte RAM, 64KByte CCMRAM
*
* @version V1.0.0
*
* @date 2023-07-31
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Flash Configuration*/
/* Flash Base Address */
_rom_base = 0x8000000;
/*Flash Size (in Bytes) */
_rom_size = 0x0100000;
/* Embedded RAM Configuration */
/* RAM Base Address */
_ram_base = 0x20000000;
/* RAM Size (in Bytes) */
_ram_size = 0x00020000;
/* CCMRAM Base Address */
_ccmram_base = 0x10000000;
/* CCMRAM Size (in Bytes) */
_ccmram_size = 0x00010000;
/* Stack / Heap Configuration */
_end_stack = 0x20020000;
/* Heap Size (in Bytes) */
_heap_size = 0x200;
/* Stack Size (in Bytes) */
_stack_size = 0x400;
MEMORY
{
FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size
RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
CCMRAM (xrw) : ORIGIN = _ccmram_base, LENGTH = _ccmram_size
}
SECTIONS
{
.apm32_isr_vector :
{
. = ALIGN(4);
KEEP(*(.apm32_isr_vector))
. = ALIGN(4);
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .;
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
_start_address_init_data = LOADADDR(.data);
.data :
{
. = ALIGN(4);
_start_address_data = .;
*(.data)
*(.data*)
. = ALIGN(4);
_end_address_data = .;
} >RAM AT> FLASH
_siccmram = LOADADDR(.ccmram);
.ccmram :
{
. = ALIGN(4);
_sccmram = .;
*(.ccmram)
*(.ccmram*)
. = ALIGN(4);
_eccmram = .;
} >CCMRAM AT> FLASH
. = ALIGN(4);
.bss :
{
_start_address_bss = .;
__bss_start__ = _start_address_bss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_address_bss = .;
__bss_end__ = _end_address_bss;
} >RAM
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _heap_size;
. = . + _stack_size;
. = ALIGN(8);
} >RAM
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

183
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@ -0,0 +1,183 @@
/**
* @file apm32f407xe_flash.ld
*
* @brief Linker script for APM32F4xxxE series
* 512Kbytes FLASH, 128KByte RAM, 64KByte CCMRAM
*
* @version V1.0.0
*
* @date 2023-07-31
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Flash Configuration*/
/* Flash Base Address */
_rom_base = 0x8000000;
/*Flash Size (in Bytes) */
_rom_size = 0x0080000;
/* Embedded RAM Configuration */
/* RAM Base Address */
_ram_base = 0x20000000;
/* RAM Size (in Bytes) */
_ram_size = 0x00020000;
/* CCMRAM Base Address */
_ccmram_base = 0x10000000;
/* CCMRAM Size (in Bytes) */
_ccmram_size = 0x00010000;
/* Stack / Heap Configuration */
_end_stack = 0x20020000;
/* Heap Size (in Bytes) */
_heap_size = 0x200;
/* Stack Size (in Bytes) */
_stack_size = 0x400;
MEMORY
{
FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size
RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
CCMRAM (xrw) : ORIGIN = _ccmram_base, LENGTH = _ccmram_size
}
SECTIONS
{
.apm32_isr_vector :
{
. = ALIGN(4);
KEEP(*(.apm32_isr_vector))
. = ALIGN(4);
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .;
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
_start_address_init_data = LOADADDR(.data);
.data :
{
. = ALIGN(4);
_start_address_data = .;
*(.data)
*(.data*)
. = ALIGN(4);
_end_address_data = .;
} >RAM AT> FLASH
_siccmram = LOADADDR(.ccmram);
.ccmram :
{
. = ALIGN(4);
_sccmram = .;
*(.ccmram)
*(.ccmram*)
. = ALIGN(4);
_eccmram = .;
} >CCMRAM AT> FLASH
. = ALIGN(4);
.bss :
{
_start_address_bss = .;
__bss_start__ = _start_address_bss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_address_bss = .;
__bss_end__ = _end_address_bss;
} >RAM
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _heap_size;
. = . + _stack_size;
. = ALIGN(8);
} >RAM
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

183
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@ -0,0 +1,183 @@
/**
* @file apm32f407xg_flash.ld
*
* @brief Linker script for APM32F4xxxG series
* 1024Kbytes FLASH, 128KByte RAM, 64KByte CCMRAM
*
* @version V1.0.0
*
* @date 2023-07-31
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Flash Configuration*/
/* Flash Base Address */
_rom_base = 0x8000000;
/*Flash Size (in Bytes) */
_rom_size = 0x0100000;
/* Embedded RAM Configuration */
/* RAM Base Address */
_ram_base = 0x20000000;
/* RAM Size (in Bytes) */
_ram_size = 0x00020000;
/* CCMRAM Base Address */
_ccmram_base = 0x10000000;
/* CCMRAM Size (in Bytes) */
_ccmram_size = 0x00010000;
/* Stack / Heap Configuration */
_end_stack = 0x20020000;
/* Heap Size (in Bytes) */
_heap_size = 0x200;
/* Stack Size (in Bytes) */
_stack_size = 0x400;
MEMORY
{
FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size
RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
CCMRAM (xrw) : ORIGIN = _ccmram_base, LENGTH = _ccmram_size
}
SECTIONS
{
.apm32_isr_vector :
{
. = ALIGN(4);
KEEP(*(.apm32_isr_vector))
. = ALIGN(4);
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .;
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
_start_address_init_data = LOADADDR(.data);
.data :
{
. = ALIGN(4);
_start_address_data = .;
*(.data)
*(.data*)
. = ALIGN(4);
_end_address_data = .;
} >RAM AT> FLASH
_siccmram = LOADADDR(.ccmram);
.ccmram :
{
. = ALIGN(4);
_sccmram = .;
*(.ccmram)
*(.ccmram*)
. = ALIGN(4);
_eccmram = .;
} >CCMRAM AT> FLASH
. = ALIGN(4);
.bss :
{
_start_address_bss = .;
__bss_start__ = _start_address_bss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_address_bss = .;
__bss_end__ = _end_address_bss;
} >RAM
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _heap_size;
. = . + _stack_size;
. = ALIGN(8);
} >RAM
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

164
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@ -0,0 +1,164 @@
/*!
* @file apm32f411xc_flash.ld
*
* @brief Linker script for APM32F411xC series
* 256Kbytes FLASH, 128KByte RAM
*
* @version V1.0.0
*
* @date 2023-12-01
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Flash Configuration*/
/* Flash Base Address */
_rom_base = 0x8000000;
/*Flash Size (in Bytes) */
_rom_size = 0x0040000;
/* Embedded RAM Configuration */
/* RAM Base Address */
_ram_base = 0x20000000;
/* RAM Size (in Bytes) */
_ram_size = 0x00020000;
/* Stack / Heap Configuration */
_end_stack = 0x20020000;
/* Heap Size (in Bytes) */
_heap_size = 0x200;
/* Stack Size (in Bytes) */
_stack_size = 0x400;
MEMORY
{
FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size
RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
}
SECTIONS
{
.apm32_isr_vector :
{
. = ALIGN(4);
KEEP(*(.apm32_isr_vector))
. = ALIGN(4);
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .;
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
_start_address_init_data = LOADADDR(.data);
.data :
{
. = ALIGN(4);
_start_address_data = .;
*(.data)
*(.data*)
. = ALIGN(4);
_end_address_data = .;
} >RAM AT> FLASH
. = ALIGN(4);
.bss :
{
_start_address_bss = .;
__bss_start__ = _start_address_bss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_address_bss = .;
__bss_end__ = _end_address_bss;
} >RAM
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _heap_size;
. = . + _stack_size;
. = ALIGN(8);
} >RAM
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

164
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/gcc/apm32f411xe_flash.ld Normal file
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/*!
* @file apm32f411xe_flash.ld
*
* @brief Linker script for APM32F411xE series
* 256Kbytes FLASH, 128KByte RAM
*
* @version V1.0.0
*
* @date 2023-12-01
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Flash Configuration*/
/* Flash Base Address */
_rom_base = 0x8000000;
/*Flash Size (in Bytes) */
_rom_size = 0x0080000;
/* Embedded RAM Configuration */
/* RAM Base Address */
_ram_base = 0x20000000;
/* RAM Size (in Bytes) */
_ram_size = 0x00020000;
/* Stack / Heap Configuration */
_end_stack = 0x20020000;
/* Heap Size (in Bytes) */
_heap_size = 0x200;
/* Stack Size (in Bytes) */
_stack_size = 0x400;
MEMORY
{
FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size
RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
}
SECTIONS
{
.apm32_isr_vector :
{
. = ALIGN(4);
KEEP(*(.apm32_isr_vector))
. = ALIGN(4);
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .;
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
_start_address_init_data = LOADADDR(.data);
.data :
{
. = ALIGN(4);
_start_address_data = .;
*(.data)
*(.data*)
. = ALIGN(4);
_end_address_data = .;
} >RAM AT> FLASH
. = ALIGN(4);
.bss :
{
_start_address_bss = .;
__bss_start__ = _start_address_bss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_address_bss = .;
__bss_end__ = _end_address_bss;
} >RAM
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _heap_size;
. = . + _stack_size;
. = ALIGN(8);
} >RAM
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

183
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/gcc/apm32f417xe_flash.ld Normal file
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@ -0,0 +1,183 @@
/**
* @file apm32f417xe_flash.ld
*
* @brief Linker script for APM32F4xxxE series
* 512Kbytes FLASH, 128KByte RAM, 64KByte CCMRAM
*
* @version V1.0.0
*
* @date 2023-07-31
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Flash Configuration*/
/* Flash Base Address */
_rom_base = 0x8000000;
/*Flash Size (in Bytes) */
_rom_size = 0x0080000;
/* Embedded RAM Configuration */
/* RAM Base Address */
_ram_base = 0x20000000;
/* RAM Size (in Bytes) */
_ram_size = 0x00020000;
/* CCMRAM Base Address */
_ccmram_base = 0x10000000;
/* CCMRAM Size (in Bytes) */
_ccmram_size = 0x00010000;
/* Stack / Heap Configuration */
_end_stack = 0x20020000;
/* Heap Size (in Bytes) */
_heap_size = 0x200;
/* Stack Size (in Bytes) */
_stack_size = 0x400;
MEMORY
{
FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size
RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
CCMRAM (xrw) : ORIGIN = _ccmram_base, LENGTH = _ccmram_size
}
SECTIONS
{
.apm32_isr_vector :
{
. = ALIGN(4);
KEEP(*(.apm32_isr_vector))
. = ALIGN(4);
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .;
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
_start_address_init_data = LOADADDR(.data);
.data :
{
. = ALIGN(4);
_start_address_data = .;
*(.data)
*(.data*)
. = ALIGN(4);
_end_address_data = .;
} >RAM AT> FLASH
_siccmram = LOADADDR(.ccmram);
.ccmram :
{
. = ALIGN(4);
_sccmram = .;
*(.ccmram)
*(.ccmram*)
. = ALIGN(4);
_eccmram = .;
} >CCMRAM AT> FLASH
. = ALIGN(4);
.bss :
{
_start_address_bss = .;
__bss_start__ = _start_address_bss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_address_bss = .;
__bss_end__ = _end_address_bss;
} >RAM
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _heap_size;
. = . + _stack_size;
. = ALIGN(8);
} >RAM
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

183
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/gcc/apm32f417xg_flash.ld Normal file
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/**
* @file apm32f417xg_flash.ld
*
* @brief Linker script for APM32F4xxxG series
* 1024Kbytes FLASH, 128KByte RAM, 64KByte CCMRAM
*
* @version V1.0.0
*
* @date 2023-07-31
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Flash Configuration*/
/* Flash Base Address */
_rom_base = 0x8000000;
/*Flash Size (in Bytes) */
_rom_size = 0x0100000;
/* Embedded RAM Configuration */
/* RAM Base Address */
_ram_base = 0x20000000;
/* RAM Size (in Bytes) */
_ram_size = 0x00020000;
/* CCMRAM Base Address */
_ccmram_base = 0x10000000;
/* CCMRAM Size (in Bytes) */
_ccmram_size = 0x00010000;
/* Stack / Heap Configuration */
_end_stack = 0x20020000;
/* Heap Size (in Bytes) */
_heap_size = 0x200;
/* Stack Size (in Bytes) */
_stack_size = 0x400;
MEMORY
{
FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size
RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
CCMRAM (xrw) : ORIGIN = _ccmram_base, LENGTH = _ccmram_size
}
SECTIONS
{
.apm32_isr_vector :
{
. = ALIGN(4);
KEEP(*(.apm32_isr_vector))
. = ALIGN(4);
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .;
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
_start_address_init_data = LOADADDR(.data);
.data :
{
. = ALIGN(4);
_start_address_data = .;
*(.data)
*(.data*)
. = ALIGN(4);
_end_address_data = .;
} >RAM AT> FLASH
_siccmram = LOADADDR(.ccmram);
.ccmram :
{
. = ALIGN(4);
_sccmram = .;
*(.ccmram)
*(.ccmram*)
. = ALIGN(4);
_eccmram = .;
} >CCMRAM AT> FLASH
. = ALIGN(4);
.bss :
{
_start_address_bss = .;
__bss_start__ = _start_address_bss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_address_bss = .;
__bss_end__ = _end_address_bss;
} >RAM
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _heap_size;
. = . + _stack_size;
. = ALIGN(8);
} >RAM
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

183
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/gcc/apm32f465xe_flash.ld Normal file
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/**
* @file apm32f465xe_flash.ld
*
* @brief Linker script for APM32F465xE series
* 512Kbytes FLASH, 128KByte RAM, 64KByte CCMRAM
*
* @version V1.0.0
*
* @date 2023-12-01
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Flash Configuration*/
/* Flash Base Address */
_rom_base = 0x8000000;
/*Flash Size (in Bytes) */
_rom_size = 0x0080000;
/* Embedded RAM Configuration */
/* RAM Base Address */
_ram_base = 0x20000000;
/* RAM Size (in Bytes) */
_ram_size = 0x00020000;
/* CCMRAM Base Address */
_ccmram_base = 0x10000000;
/* CCMRAM Size (in Bytes) */
_ccmram_size = 0x00010000;
/* Stack / Heap Configuration */
_end_stack = 0x20020000;
/* Heap Size (in Bytes) */
_heap_size = 0x200;
/* Stack Size (in Bytes) */
_stack_size = 0x400;
MEMORY
{
FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size
RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
CCMRAM (xrw) : ORIGIN = _ccmram_base, LENGTH = _ccmram_size
}
SECTIONS
{
.apm32_isr_vector :
{
. = ALIGN(4);
KEEP(*(.apm32_isr_vector))
. = ALIGN(4);
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .;
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
_start_address_init_data = LOADADDR(.data);
.data :
{
. = ALIGN(4);
_start_address_data = .;
*(.data)
*(.data*)
. = ALIGN(4);
_end_address_data = .;
} >RAM AT> FLASH
_siccmram = LOADADDR(.ccmram);
.ccmram :
{
. = ALIGN(4);
_sccmram = .;
*(.ccmram)
*(.ccmram*)
. = ALIGN(4);
_eccmram = .;
} >CCMRAM AT> FLASH
. = ALIGN(4);
.bss :
{
_start_address_bss = .;
__bss_start__ = _start_address_bss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_address_bss = .;
__bss_end__ = _end_address_bss;
} >RAM
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _heap_size;
. = . + _stack_size;
. = ALIGN(8);
} >RAM
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

485
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/gcc/startup_apm32f405xx.S Normal file
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/**
* @file startup_apm32f405xx.S
*
* @brief APM32F405xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*
* @version V1.0.0
*
* @date 2023-07-31
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_apm32_Vectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _start_address_init_data
/* start address for the .data section. defined in linker script */
.word _start_address_data
/* end address for the .data section. defined in linker script */
.word _end_address_data
/* start address for the .bss section. defined in linker script */
.word _start_address_bss
/* end address for the .bss section. defined in linker script */
.word _end_address_bss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
// Reset handler routine
Reset_Handler:
ldr sp, =_end_stack
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_start_address_data
ldr r1, =_end_address_data
ldr r2, =_start_address_init_data
movs r3, #0
b L_loop0_0
L_loop0:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
L_loop0_0:
adds r4, r0, r3
cmp r4, r1
bcc L_loop0
ldr r2, =_start_address_bss
ldr r4, =_end_address_bss
movs r3, #0
b L_loop1
L_loop2:
str r3, [r2]
adds r2, r2, #4
L_loop1:
cmp r2, r4
bcc L_loop2
bl SystemInit
bl __libc_init_array
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
// This is the code that gets called when the processor receives an unexpected interrupt.
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
// The minimal vector table for a Cortex M4.
.section .apm32_isr_vector,"a",%progbits
.type g_apm32_Vectors, %object
.size g_apm32_Vectors, .-g_apm32_Vectors
// Vector Table Mapped to Address 0 at Reset
g_apm32_Vectors:
.word _end_stack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
/* External Interrupts */
.word WWDT_IRQHandler // Window WatchDog
.word PVD_IRQHandler // PVD through EINT Line detection
.word TAMP_STAMP_IRQHandler // Tamper and TimeStamps through the EINT line
.word RTC_WKUP_IRQHandler // RTC Wakeup through the EINT line
.word FLASH_IRQHandler // FLASH
.word RCM_IRQHandler // RCM
.word EINT0_IRQHandler // EINT Line0
.word EINT1_IRQHandler // EINT Line1
.word EINT2_IRQHandler // EINT Line2
.word EINT3_IRQHandler // EINT Line3
.word EINT4_IRQHandler // EINT Line4
.word DMA1_STR0_IRQHandler // DMA1 Stream 0
.word DMA1_STR1_IRQHandler // DMA1 Stream 1
.word DMA1_STR2_IRQHandler // DMA1 Stream 2
.word DMA1_STR3_IRQHandler // DMA1 Stream 3
.word DMA1_STR4_IRQHandler // DMA1 Stream 4
.word DMA1_STR5_IRQHandler // DMA1 Stream 5
.word DMA1_STR6_IRQHandler // DMA1 Stream 6
.word ADC_IRQHandler // ADC1, ADC2 and ADC3s
.word CAN1_TX_IRQHandler // CAN1 TX
.word CAN1_RX0_IRQHandler // CAN1 RX0
.word CAN1_RX1_IRQHandler // CAN1 RX1
.word CAN1_SCE_IRQHandler // CAN1 SCE
.word EINT9_5_IRQHandler // External Line[9:5]s
.word TMR1_BRK_TMR9_IRQHandler // TMR1 Break and TMR9
.word TMR1_UP_TMR10_IRQHandler // TMR1 Update and TMR10
.word TMR1_TRG_COM_TMR11_IRQHandler // TMR1 Trigger and Commutation and TMR11
.word TMR1_CC_IRQHandler // TMR1 Capture Compare
.word TMR2_IRQHandler // TMR2
.word TMR3_IRQHandler // TMR3
.word TMR4_IRQHandler // TMR4
.word I2C1_EV_IRQHandler // I2C1 Event
.word I2C1_ER_IRQHandler // I2C1 Error
.word I2C2_EV_IRQHandler // I2C2 Event
.word I2C2_ER_IRQHandler // I2C2 Error
.word SPI1_IRQHandler // SPI1
.word SPI2_IRQHandler // SPI2
.word USART1_IRQHandler // USART1
.word USART2_IRQHandler // USART2
.word USART3_IRQHandler // USART3
.word EINT15_10_IRQHandler // External Line[15:10]s
.word RTC_Alarm_IRQHandler // RTC Alarm (A and B) through EINT Line
.word OTG_FS_WKUP_IRQHandler // USB OTG FS Wakeup through EINT line
.word TMR8_BRK_TMR12_IRQHandler // TMR8 Break and TMR12
.word TMR8_UP_TMR13_IRQHandler // TMR8 Update and TMR13
.word TMR8_TRG_COM_TMR14_IRQHandler // TMR8 Trigger and Commutation and TMR14
.word TMR8_CC_IRQHandler // TMR8 Capture Compare
.word DMA1_STR7_IRQHandler // DMA1 Stream7
.word EMMC_IRQHandler // EMMC
.word SDIO_IRQHandler // SDIO
.word TMR5_IRQHandler // TMR5
.word SPI3_IRQHandler // SPI3
.word UART4_IRQHandler // UART4
.word UART5_IRQHandler // UART5
.word TMR6_DAC_IRQHandler // TMR6 and DAC1&2 underrun errors
.word TMR7_IRQHandler // TMR7
.word DMA2_STR0_IRQHandler // DMA2 Stream 0
.word DMA2_STR1_IRQHandler // DMA2 Stream 1
.word DMA2_STR2_IRQHandler // DMA2 Stream 2
.word DMA2_STR3_IRQHandler // DMA2 Stream 3
.word DMA2_STR4_IRQHandler // DMA2 Stream 4
.word 0 // Reserved
.word 0 // Reserved
.word CAN2_TX_IRQHandler // CAN2 TX
.word CAN2_RX0_IRQHandler // CAN2 RX0
.word CAN2_RX1_IRQHandler // CAN2 RX1
.word CAN2_SCE_IRQHandler // CAN2 SCE
.word OTG_FS_IRQHandler // USB OTG FS
.word DMA2_STR5_IRQHandler // DMA2 Stream 5
.word DMA2_STR6_IRQHandler // DMA2 Stream 6
.word DMA2_STR7_IRQHandler // DMA2 Stream 7
.word USART6_IRQHandler // USART6
.word I2C3_EV_IRQHandler // I2C3 event
.word I2C3_ER_IRQHandler // I2C3 error
.word OTG_HS1_EP1_OUT_IRQHandler // USB OTG HS End Point 1 Out
.word OTG_HS1_EP1_IN_IRQHandler // USB OTG HS End Point 1 In
.word OTG_HS1_WKUP_IRQHandler // USB OTG HS Wakeup through EINT
.word OTG_HS1_IRQHandler // USB OTG HS
.word 0 // Reserved
.word 0 // Reserved
.word HASH_RNG_IRQHandler // Hash and Rng
.word FPU_IRQHandler // FPU
.word SM3_IRQHandler // SM3
.word SM4_IRQHandler // SM4
.word BN_IRQHandler // BN
// Default exception/interrupt handler
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDT_IRQHandler
.thumb_set WWDT_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCM_IRQHandler
.thumb_set RCM_IRQHandler,Default_Handler
.weak EINT0_IRQHandler
.thumb_set EINT0_IRQHandler,Default_Handler
.weak EINT1_IRQHandler
.thumb_set EINT1_IRQHandler,Default_Handler
.weak EINT2_IRQHandler
.thumb_set EINT2_IRQHandler,Default_Handler
.weak EINT3_IRQHandler
.thumb_set EINT3_IRQHandler,Default_Handler
.weak EINT4_IRQHandler
.thumb_set EINT4_IRQHandler,Default_Handler
.weak DMA1_STR0_IRQHandler
.thumb_set DMA1_STR0_IRQHandler,Default_Handler
.weak DMA1_STR1_IRQHandler
.thumb_set DMA1_STR1_IRQHandler,Default_Handler
.weak DMA1_STR2_IRQHandler
.thumb_set DMA1_STR2_IRQHandler,Default_Handler
.weak DMA1_STR3_IRQHandler
.thumb_set DMA1_STR3_IRQHandler,Default_Handler
.weak DMA1_STR4_IRQHandler
.thumb_set DMA1_STR4_IRQHandler,Default_Handler
.weak DMA1_STR5_IRQHandler
.thumb_set DMA1_STR5_IRQHandler,Default_Handler
.weak DMA1_STR6_IRQHandler
.thumb_set DMA1_STR6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EINT9_5_IRQHandler
.thumb_set EINT9_5_IRQHandler,Default_Handler
.weak TMR1_BRK_TMR9_IRQHandler
.thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
.weak TMR1_UP_TMR10_IRQHandler
.thumb_set TMR1_UP_TMR10_IRQHandler,Default_Handler
.weak TMR1_TRG_COM_TMR11_IRQHandler
.thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
.weak TMR1_CC_IRQHandler
.thumb_set TMR1_CC_IRQHandler,Default_Handler
.weak TMR2_IRQHandler
.thumb_set TMR2_IRQHandler,Default_Handler
.weak TMR3_IRQHandler
.thumb_set TMR3_IRQHandler,Default_Handler
.weak TMR4_IRQHandler
.thumb_set TMR4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EINT15_10_IRQHandler
.thumb_set EINT15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TMR8_BRK_TMR12_IRQHandler
.thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
.weak TMR8_UP_TMR13_IRQHandler
.thumb_set TMR8_UP_TMR13_IRQHandler,Default_Handler
.weak TMR8_TRG_COM_TMR14_IRQHandler
.thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
.weak TMR8_CC_IRQHandler
.thumb_set TMR8_CC_IRQHandler,Default_Handler
.weak DMA1_STR7_IRQHandler
.thumb_set DMA1_STR7_IRQHandler,Default_Handler
.weak EMMC_IRQHandler
.thumb_set EMMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TMR5_IRQHandler
.thumb_set TMR5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TMR6_DAC_IRQHandler
.thumb_set TMR6_DAC_IRQHandler,Default_Handler
.weak TMR7_IRQHandler
.thumb_set TMR7_IRQHandler,Default_Handler
.weak DMA2_STR0_IRQHandler
.thumb_set DMA2_STR0_IRQHandler,Default_Handler
.weak DMA2_STR1_IRQHandler
.thumb_set DMA2_STR1_IRQHandler,Default_Handler
.weak DMA2_STR2_IRQHandler
.thumb_set DMA2_STR2_IRQHandler,Default_Handler
.weak DMA2_STR3_IRQHandler
.thumb_set DMA2_STR3_IRQHandler,Default_Handler
.weak DMA2_STR4_IRQHandler
.thumb_set DMA2_STR4_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_STR5_IRQHandler
.thumb_set DMA2_STR5_IRQHandler,Default_Handler
.weak DMA2_STR6_IRQHandler
.thumb_set DMA2_STR6_IRQHandler,Default_Handler
.weak DMA2_STR7_IRQHandler
.thumb_set DMA2_STR7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS1_EP1_OUT_IRQHandler
.thumb_set OTG_HS1_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS1_EP1_IN_IRQHandler
.thumb_set OTG_HS1_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS1_WKUP_IRQHandler
.thumb_set OTG_HS1_WKUP_IRQHandler,Default_Handler
.weak OTG_HS1_IRQHandler
.thumb_set OTG_HS1_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak SM3_IRQHandler
.thumb_set SM3_IRQHandler,Default_Handler
.weak SM4_IRQHandler
.thumb_set SM4_IRQHandler,Default_Handler
.weak BN_IRQHandler
.thumb_set BN_IRQHandler,Default_Handler

494
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/gcc/startup_apm32f407xx.S Normal file
View file

@ -0,0 +1,494 @@
/**
* @file startup_apm32f407xx.S
*
* @brief APM32F407xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*
* @version V1.0.0
*
* @date 2023-07-31
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_apm32_Vectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _start_address_init_data
/* start address for the .data section. defined in linker script */
.word _start_address_data
/* end address for the .data section. defined in linker script */
.word _end_address_data
/* start address for the .bss section. defined in linker script */
.word _start_address_bss
/* end address for the .bss section. defined in linker script */
.word _end_address_bss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
// Reset handler routine
Reset_Handler:
ldr sp, =_end_stack
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_start_address_data
ldr r1, =_end_address_data
ldr r2, =_start_address_init_data
movs r3, #0
b L_loop0_0
L_loop0:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
L_loop0_0:
adds r4, r0, r3
cmp r4, r1
bcc L_loop0
ldr r2, =_start_address_bss
ldr r4, =_end_address_bss
movs r3, #0
b L_loop1
L_loop2:
str r3, [r2]
adds r2, r2, #4
L_loop1:
cmp r2, r4
bcc L_loop2
bl SystemInit
bl __libc_init_array
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
// This is the code that gets called when the processor receives an unexpected interrupt.
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
// The minimal vector table for a Cortex M4.
.section .apm32_isr_vector,"a",%progbits
.type g_apm32_Vectors, %object
.size g_apm32_Vectors, .-g_apm32_Vectors
// Vector Table Mapped to Address 0 at Reset
g_apm32_Vectors:
.word _end_stack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
/* External Interrupts */
.word WWDT_IRQHandler // Window WatchDog
.word PVD_IRQHandler // PVD through EINT Line detection
.word TAMP_STAMP_IRQHandler // Tamper and TimeStamps through the EINT line
.word RTC_WKUP_IRQHandler // RTC Wakeup through the EINT line
.word FLASH_IRQHandler // FLASH
.word RCM_IRQHandler // RCM
.word EINT0_IRQHandler // EINT Line0
.word EINT1_IRQHandler // EINT Line1
.word EINT2_IRQHandler // EINT Line2
.word EINT3_IRQHandler // EINT Line3
.word EINT4_IRQHandler // EINT Line4
.word DMA1_STR0_IRQHandler // DMA1 Stream 0
.word DMA1_STR1_IRQHandler // DMA1 Stream 1
.word DMA1_STR2_IRQHandler // DMA1 Stream 2
.word DMA1_STR3_IRQHandler // DMA1 Stream 3
.word DMA1_STR4_IRQHandler // DMA1 Stream 4
.word DMA1_STR5_IRQHandler // DMA1 Stream 5
.word DMA1_STR6_IRQHandler // DMA1 Stream 6
.word ADC_IRQHandler // ADC1, ADC2 and ADC3s
.word CAN1_TX_IRQHandler // CAN1 TX
.word CAN1_RX0_IRQHandler // CAN1 RX0
.word CAN1_RX1_IRQHandler // CAN1 RX1
.word CAN1_SCE_IRQHandler // CAN1 SCE
.word EINT9_5_IRQHandler // External Line[9:5]s
.word TMR1_BRK_TMR9_IRQHandler // TMR1 Break and TMR9
.word TMR1_UP_TMR10_IRQHandler // TMR1 Update and TMR10
.word TMR1_TRG_COM_TMR11_IRQHandler // TMR1 Trigger and Commutation and TMR11
.word TMR1_CC_IRQHandler // TMR1 Capture Compare
.word TMR2_IRQHandler // TMR2
.word TMR3_IRQHandler // TMR3
.word TMR4_IRQHandler // TMR4
.word I2C1_EV_IRQHandler // I2C1 Event
.word I2C1_ER_IRQHandler // I2C1 Error
.word I2C2_EV_IRQHandler // I2C2 Event
.word I2C2_ER_IRQHandler // I2C2 Error
.word SPI1_IRQHandler // SPI1
.word SPI2_IRQHandler // SPI2
.word USART1_IRQHandler // USART1
.word USART2_IRQHandler // USART2
.word USART3_IRQHandler // USART3
.word EINT15_10_IRQHandler // External Line[15:10]s
.word RTC_Alarm_IRQHandler // RTC Alarm (A and B) through EINT Line
.word OTG_FS_WKUP_IRQHandler // USB OTG FS Wakeup through EINT line
.word TMR8_BRK_TMR12_IRQHandler // TMR8 Break and TMR12
.word TMR8_UP_TMR13_IRQHandler // TMR8 Update and TMR13
.word TMR8_TRG_COM_TMR14_IRQHandler // TMR8 Trigger and Commutation and TMR14
.word TMR8_CC_IRQHandler // TMR8 Capture Compare
.word DMA1_STR7_IRQHandler // DMA1 Stream7
.word EMMC_IRQHandler // EMMC
.word SDIO_IRQHandler // SDIO
.word TMR5_IRQHandler // TMR5
.word SPI3_IRQHandler // SPI3
.word UART4_IRQHandler // UART4
.word UART5_IRQHandler // UART5
.word TMR6_DAC_IRQHandler // TMR6 and DAC1&2 underrun errors
.word TMR7_IRQHandler // TMR7
.word DMA2_STR0_IRQHandler // DMA2 Stream 0
.word DMA2_STR1_IRQHandler // DMA2 Stream 1
.word DMA2_STR2_IRQHandler // DMA2 Stream 2
.word DMA2_STR3_IRQHandler // DMA2 Stream 3
.word DMA2_STR4_IRQHandler // DMA2 Stream 4
.word ETH_IRQHandler // Ethernet
.word ETH_WKUP_IRQHandler // Ethernet Wakeup through EINT line
.word CAN2_TX_IRQHandler // CAN2 TX
.word CAN2_RX0_IRQHandler // CAN2 RX0
.word CAN2_RX1_IRQHandler // CAN2 RX1
.word CAN2_SCE_IRQHandler // CAN2 SCE
.word OTG_FS_IRQHandler // USB OTG FS
.word DMA2_STR5_IRQHandler // DMA2 Stream 5
.word DMA2_STR6_IRQHandler // DMA2 Stream 6
.word DMA2_STR7_IRQHandler // DMA2 Stream 7
.word USART6_IRQHandler // USART6
.word I2C3_EV_IRQHandler // I2C3 event
.word I2C3_ER_IRQHandler // I2C3 error
.word OTG_HS1_EP1_OUT_IRQHandler // USB OTG HS End Point 1 Out
.word OTG_HS1_EP1_IN_IRQHandler // USB OTG HS End Point 1 In
.word OTG_HS1_WKUP_IRQHandler // USB OTG HS Wakeup through EINT
.word OTG_HS1_IRQHandler // USB OTG HS
.word DCI_IRQHandler // DCI
.word 0 // Reserved
.word HASH_RNG_IRQHandler // Hash and Rng
.word FPU_IRQHandler // FPU
.word SM3_IRQHandler // SM3
.word SM4_IRQHandler // SM4
.word BN_IRQHandler // BN
// Default exception/interrupt handler
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDT_IRQHandler
.thumb_set WWDT_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCM_IRQHandler
.thumb_set RCM_IRQHandler,Default_Handler
.weak EINT0_IRQHandler
.thumb_set EINT0_IRQHandler,Default_Handler
.weak EINT1_IRQHandler
.thumb_set EINT1_IRQHandler,Default_Handler
.weak EINT2_IRQHandler
.thumb_set EINT2_IRQHandler,Default_Handler
.weak EINT3_IRQHandler
.thumb_set EINT3_IRQHandler,Default_Handler
.weak EINT4_IRQHandler
.thumb_set EINT4_IRQHandler,Default_Handler
.weak DMA1_STR0_IRQHandler
.thumb_set DMA1_STR0_IRQHandler,Default_Handler
.weak DMA1_STR1_IRQHandler
.thumb_set DMA1_STR1_IRQHandler,Default_Handler
.weak DMA1_STR2_IRQHandler
.thumb_set DMA1_STR2_IRQHandler,Default_Handler
.weak DMA1_STR3_IRQHandler
.thumb_set DMA1_STR3_IRQHandler,Default_Handler
.weak DMA1_STR4_IRQHandler
.thumb_set DMA1_STR4_IRQHandler,Default_Handler
.weak DMA1_STR5_IRQHandler
.thumb_set DMA1_STR5_IRQHandler,Default_Handler
.weak DMA1_STR6_IRQHandler
.thumb_set DMA1_STR6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EINT9_5_IRQHandler
.thumb_set EINT9_5_IRQHandler,Default_Handler
.weak TMR1_BRK_TMR9_IRQHandler
.thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
.weak TMR1_UP_TMR10_IRQHandler
.thumb_set TMR1_UP_TMR10_IRQHandler,Default_Handler
.weak TMR1_TRG_COM_TMR11_IRQHandler
.thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
.weak TMR1_CC_IRQHandler
.thumb_set TMR1_CC_IRQHandler,Default_Handler
.weak TMR2_IRQHandler
.thumb_set TMR2_IRQHandler,Default_Handler
.weak TMR3_IRQHandler
.thumb_set TMR3_IRQHandler,Default_Handler
.weak TMR4_IRQHandler
.thumb_set TMR4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EINT15_10_IRQHandler
.thumb_set EINT15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TMR8_BRK_TMR12_IRQHandler
.thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
.weak TMR8_UP_TMR13_IRQHandler
.thumb_set TMR8_UP_TMR13_IRQHandler,Default_Handler
.weak TMR8_TRG_COM_TMR14_IRQHandler
.thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
.weak TMR8_CC_IRQHandler
.thumb_set TMR8_CC_IRQHandler,Default_Handler
.weak DMA1_STR7_IRQHandler
.thumb_set DMA1_STR7_IRQHandler,Default_Handler
.weak EMMC_IRQHandler
.thumb_set EMMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TMR5_IRQHandler
.thumb_set TMR5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TMR6_DAC_IRQHandler
.thumb_set TMR6_DAC_IRQHandler,Default_Handler
.weak TMR7_IRQHandler
.thumb_set TMR7_IRQHandler,Default_Handler
.weak DMA2_STR0_IRQHandler
.thumb_set DMA2_STR0_IRQHandler,Default_Handler
.weak DMA2_STR1_IRQHandler
.thumb_set DMA2_STR1_IRQHandler,Default_Handler
.weak DMA2_STR2_IRQHandler
.thumb_set DMA2_STR2_IRQHandler,Default_Handler
.weak DMA2_STR3_IRQHandler
.thumb_set DMA2_STR3_IRQHandler,Default_Handler
.weak DMA2_STR4_IRQHandler
.thumb_set DMA2_STR4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_STR5_IRQHandler
.thumb_set DMA2_STR5_IRQHandler,Default_Handler
.weak DMA2_STR6_IRQHandler
.thumb_set DMA2_STR6_IRQHandler,Default_Handler
.weak DMA2_STR7_IRQHandler
.thumb_set DMA2_STR7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS1_EP1_OUT_IRQHandler
.thumb_set OTG_HS1_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS1_EP1_IN_IRQHandler
.thumb_set OTG_HS1_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS1_WKUP_IRQHandler
.thumb_set OTG_HS1_WKUP_IRQHandler,Default_Handler
.weak OTG_HS1_IRQHandler
.thumb_set OTG_HS1_IRQHandler,Default_Handler
.weak DCI_IRQHandler
.thumb_set DCI_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak SM3_IRQHandler
.thumb_set SM3_IRQHandler,Default_Handler
.weak SM4_IRQHandler
.thumb_set SM4_IRQHandler,Default_Handler
.weak BN_IRQHandler
.thumb_set BN_IRQHandler,Default_Handler

468
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/gcc/startup_apm32f411xx.S Normal file
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@ -0,0 +1,468 @@
/**
* @file startup_apm32f411xx.S
*
* @brief APM32F411xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*
* @version V1.0.0
*
* @date 2023-12-01
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_apm32_Vectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _start_address_init_data
/* start address for the .data section. defined in linker script */
.word _start_address_data
/* end address for the .data section. defined in linker script */
.word _end_address_data
/* start address for the .bss section. defined in linker script */
.word _start_address_bss
/* end address for the .bss section. defined in linker script */
.word _end_address_bss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
// Reset handler routine
Reset_Handler:
ldr sp, =_end_stack
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_start_address_data
ldr r1, =_end_address_data
ldr r2, =_start_address_init_data
movs r3, #0
b L_loop0_0
L_loop0:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
L_loop0_0:
adds r4, r0, r3
cmp r4, r1
bcc L_loop0
ldr r2, =_start_address_bss
ldr r4, =_end_address_bss
movs r3, #0
b L_loop1
L_loop2:
str r3, [r2]
adds r2, r2, #4
L_loop1:
cmp r2, r4
bcc L_loop2
bl SystemInit
bl __libc_init_array
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
// This is the code that gets called when the processor receives an unexpected interrupt.
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
// The minimal vector table for a Cortex M4.
.section .apm32_isr_vector,"a",%progbits
.type g_apm32_Vectors, %object
.size g_apm32_Vectors, .-g_apm32_Vectors
// Vector Table Mapped to Address 0 at Reset
g_apm32_Vectors:
.word _end_stack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
/* External Interrupts */
.word WWDT_IRQHandler // Window WatchDog
.word PVD_IRQHandler // PVD through EINT Line detection
.word TAMP_STAMP_IRQHandler // Tamper and TimeStamps through the EINT line
.word RTC_WKUP_IRQHandler // RTC Wakeup through the EINT line
.word FLASH_IRQHandler // FLASH
.word RCM_IRQHandler // RCM
.word EINT0_IRQHandler // EINT Line0
.word EINT1_IRQHandler // EINT Line1
.word EINT2_IRQHandler // EINT Line2
.word EINT3_IRQHandler // EINT Line3
.word EINT4_IRQHandler // EINT Line4
.word DMA1_STR0_IRQHandler // DMA1 Stream 0
.word DMA1_STR1_IRQHandler // DMA1 Stream 1
.word DMA1_STR2_IRQHandler // DMA1 Stream 2
.word DMA1_STR3_IRQHandler // DMA1 Stream 3
.word DMA1_STR4_IRQHandler // DMA1 Stream 4
.word DMA1_STR5_IRQHandler // DMA1 Stream 5
.word DMA1_STR6_IRQHandler // DMA1 Stream 6
.word ADC_IRQHandler // ADC1, ADC2
.word CAN1_TX_IRQHandler // CAN1 TX
.word CAN1_RX0_IRQHandler // CAN1 RX0
.word CAN1_RX1_IRQHandler // CAN1 RX1
.word CAN1_SCE_IRQHandler // CAN1 SCE
.word EINT9_5_IRQHandler // External Line[9:5]s
.word TMR1_BRK_TMR9_IRQHandler // TMR1 Break and TMR9
.word TMR1_UP_TMR10_IRQHandler // TMR1 Update and TMR10
.word TMR1_TRG_COM_TMR11_IRQHandler // TMR1 Trigger and Commutation and TMR11
.word TMR1_CC_IRQHandler // TMR1 Capture Compare
.word TMR2_IRQHandler // TMR2
.word TMR3_IRQHandler // TMR3
.word TMR4_IRQHandler // TMR4
.word I2C1_EV_IRQHandler // I2C1 Event
.word I2C1_ER_IRQHandler // I2C1 Error
.word I2C2_EV_IRQHandler // I2C2 Event
.word I2C2_ER_IRQHandler // I2C2 Error
.word SPI1_IRQHandler // SPI1
.word SPI2_IRQHandler // SPI2
.word USART1_IRQHandler // USART1
.word USART2_IRQHandler // USART2
.word USART3_IRQHandler // USART3
.word EINT15_10_IRQHandler // External Line[15:10]s
.word RTC_Alarm_IRQHandler // RTC Alarm (A and B) through EINT Line
.word OTG_FS_WKUP_IRQHandler // USB OTG FS Wakeup through EINT line
.word TMR8_BRK_TMR12_IRQHandler // TMR8 Break and TMR12
.word TMR8_UP_TMR13_IRQHandler // TMR8 Update and TMR13
.word TMR8_TRG_COM_TMR14_IRQHandler // TMR8 Trigger and Commutation and TMR14
.word TMR8_CC_IRQHandler // TMR8 Capture Compare
.word DMA1_STR7_IRQHandler // DMA1 Stream7
.word SMC_IRQHandler // SMC
.word SDIO_IRQHandler // SDIO
.word TMR5_IRQHandler // TMR5
.word SPI3_IRQHandler // SPI3
.word UART4_IRQHandler // UART4
.word UART5_IRQHandler // UART5
.word 0 // Reserved
.word 0 // Reserved
.word DMA2_STR0_IRQHandler // DMA2 Stream 0
.word DMA2_STR1_IRQHandler // DMA2 Stream 1
.word DMA2_STR2_IRQHandler // DMA2 Stream 2
.word DMA2_STR3_IRQHandler // DMA2 Stream 3
.word DMA2_STR4_IRQHandler // DMA2 Stream 4
.word 0 // Reserved
.word 0 // Reserved
.word CAN2_TX_IRQHandler // CAN2 TX
.word CAN2_RX0_IRQHandler // CAN2 RX0
.word CAN2_RX1_IRQHandler // CAN2 RX1
.word CAN2_SCE_IRQHandler // CAN2 SCE
.word OTG_FS_IRQHandler // USB OTG FS
.word DMA2_STR5_IRQHandler // DMA2 Stream 5
.word DMA2_STR6_IRQHandler // DMA2 Stream 6
.word DMA2_STR7_IRQHandler // DMA2 Stream 7
.word USART6_IRQHandler // USART6
.word I2C3_EV_IRQHandler // I2C3 event
.word I2C3_ER_IRQHandler // I2C3 error
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word RNG_IRQHandler // RNG
.word FPU_IRQHandler // FPU
.word 0 // Reserved
.word QSPI_IRQHandler // QSPI
.word SPI4_IRQHandler // SPI4
.word SPI5_IRQHandler // SPI5
// Default exception/interrupt handler
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDT_IRQHandler
.thumb_set WWDT_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCM_IRQHandler
.thumb_set RCM_IRQHandler,Default_Handler
.weak EINT0_IRQHandler
.thumb_set EINT0_IRQHandler,Default_Handler
.weak EINT1_IRQHandler
.thumb_set EINT1_IRQHandler,Default_Handler
.weak EINT2_IRQHandler
.thumb_set EINT2_IRQHandler,Default_Handler
.weak EINT3_IRQHandler
.thumb_set EINT3_IRQHandler,Default_Handler
.weak EINT4_IRQHandler
.thumb_set EINT4_IRQHandler,Default_Handler
.weak DMA1_STR0_IRQHandler
.thumb_set DMA1_STR0_IRQHandler,Default_Handler
.weak DMA1_STR1_IRQHandler
.thumb_set DMA1_STR1_IRQHandler,Default_Handler
.weak DMA1_STR2_IRQHandler
.thumb_set DMA1_STR2_IRQHandler,Default_Handler
.weak DMA1_STR3_IRQHandler
.thumb_set DMA1_STR3_IRQHandler,Default_Handler
.weak DMA1_STR4_IRQHandler
.thumb_set DMA1_STR4_IRQHandler,Default_Handler
.weak DMA1_STR5_IRQHandler
.thumb_set DMA1_STR5_IRQHandler,Default_Handler
.weak DMA1_STR6_IRQHandler
.thumb_set DMA1_STR6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EINT9_5_IRQHandler
.thumb_set EINT9_5_IRQHandler,Default_Handler
.weak TMR1_BRK_TMR9_IRQHandler
.thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
.weak TMR1_UP_TMR10_IRQHandler
.thumb_set TMR1_UP_TMR10_IRQHandler,Default_Handler
.weak TMR1_TRG_COM_TMR11_IRQHandler
.thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
.weak TMR1_CC_IRQHandler
.thumb_set TMR1_CC_IRQHandler,Default_Handler
.weak TMR2_IRQHandler
.thumb_set TMR2_IRQHandler,Default_Handler
.weak TMR3_IRQHandler
.thumb_set TMR3_IRQHandler,Default_Handler
.weak TMR4_IRQHandler
.thumb_set TMR4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EINT15_10_IRQHandler
.thumb_set EINT15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TMR8_BRK_TMR12_IRQHandler
.thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
.weak TMR8_UP_TMR13_IRQHandler
.thumb_set TMR8_UP_TMR13_IRQHandler,Default_Handler
.weak TMR8_TRG_COM_TMR14_IRQHandler
.thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
.weak TMR8_CC_IRQHandler
.thumb_set TMR8_CC_IRQHandler,Default_Handler
.weak DMA1_STR7_IRQHandler
.thumb_set DMA1_STR7_IRQHandler,Default_Handler
.weak SMC_IRQHandler
.thumb_set SMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TMR5_IRQHandler
.thumb_set TMR5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak DMA2_STR0_IRQHandler
.thumb_set DMA2_STR0_IRQHandler,Default_Handler
.weak DMA2_STR1_IRQHandler
.thumb_set DMA2_STR1_IRQHandler,Default_Handler
.weak DMA2_STR2_IRQHandler
.thumb_set DMA2_STR2_IRQHandler,Default_Handler
.weak DMA2_STR3_IRQHandler
.thumb_set DMA2_STR3_IRQHandler,Default_Handler
.weak DMA2_STR4_IRQHandler
.thumb_set DMA2_STR4_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_STR5_IRQHandler
.thumb_set DMA2_STR5_IRQHandler,Default_Handler
.weak DMA2_STR6_IRQHandler
.thumb_set DMA2_STR6_IRQHandler,Default_Handler
.weak DMA2_STR7_IRQHandler
.thumb_set DMA2_STR7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak QSPI_IRQHandler
.thumb_set QSPI_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler

497
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/gcc/startup_apm32f417xx.S Normal file
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@ -0,0 +1,497 @@
/**
* @file startup_apm32f417xx.S
*
* @brief APM32F417xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*
* @version V1.0.0
*
* @date 2023-07-31
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_apm32_Vectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _start_address_init_data
/* start address for the .data section. defined in linker script */
.word _start_address_data
/* end address for the .data section. defined in linker script */
.word _end_address_data
/* start address for the .bss section. defined in linker script */
.word _start_address_bss
/* end address for the .bss section. defined in linker script */
.word _end_address_bss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
// Reset handler routine
Reset_Handler:
ldr sp, =_end_stack
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_start_address_data
ldr r1, =_end_address_data
ldr r2, =_start_address_init_data
movs r3, #0
b L_loop0_0
L_loop0:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
L_loop0_0:
adds r4, r0, r3
cmp r4, r1
bcc L_loop0
ldr r2, =_start_address_bss
ldr r4, =_end_address_bss
movs r3, #0
b L_loop1
L_loop2:
str r3, [r2]
adds r2, r2, #4
L_loop1:
cmp r2, r4
bcc L_loop2
bl SystemInit
bl __libc_init_array
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
// This is the code that gets called when the processor receives an unexpected interrupt.
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
// The minimal vector table for a Cortex M4.
.section .apm32_isr_vector,"a",%progbits
.type g_apm32_Vectors, %object
.size g_apm32_Vectors, .-g_apm32_Vectors
// Vector Table Mapped to Address 0 at Reset
g_apm32_Vectors:
.word _end_stack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
/* External Interrupts */
.word WWDT_IRQHandler // Window WatchDog
.word PVD_IRQHandler // PVD through EINT Line detection
.word TAMP_STAMP_IRQHandler // Tamper and TimeStamps through the EINT line
.word RTC_WKUP_IRQHandler // RTC Wakeup through the EINT line
.word FLASH_IRQHandler // FLASH
.word RCM_IRQHandler // RCM
.word EINT0_IRQHandler // EINT Line0
.word EINT1_IRQHandler // EINT Line1
.word EINT2_IRQHandler // EINT Line2
.word EINT3_IRQHandler // EINT Line3
.word EINT4_IRQHandler // EINT Line4
.word DMA1_STR0_IRQHandler // DMA1 Stream 0
.word DMA1_STR1_IRQHandler // DMA1 Stream 1
.word DMA1_STR2_IRQHandler // DMA1 Stream 2
.word DMA1_STR3_IRQHandler // DMA1 Stream 3
.word DMA1_STR4_IRQHandler // DMA1 Stream 4
.word DMA1_STR5_IRQHandler // DMA1 Stream 5
.word DMA1_STR6_IRQHandler // DMA1 Stream 6
.word ADC_IRQHandler // ADC1, ADC2 and ADC3s
.word CAN1_TX_IRQHandler // CAN1 TX
.word CAN1_RX0_IRQHandler // CAN1 RX0
.word CAN1_RX1_IRQHandler // CAN1 RX1
.word CAN1_SCE_IRQHandler // CAN1 SCE
.word EINT9_5_IRQHandler // External Line[9:5]s
.word TMR1_BRK_TMR9_IRQHandler // TMR1 Break and TMR9
.word TMR1_UP_TMR10_IRQHandler // TMR1 Update and TMR10
.word TMR1_TRG_COM_TMR11_IRQHandler // TMR1 Trigger and Commutation and TMR11
.word TMR1_CC_IRQHandler // TMR1 Capture Compare
.word TMR2_IRQHandler // TMR2
.word TMR3_IRQHandler // TMR3
.word TMR4_IRQHandler // TMR4
.word I2C1_EV_IRQHandler // I2C1 Event
.word I2C1_ER_IRQHandler // I2C1 Error
.word I2C2_EV_IRQHandler // I2C2 Event
.word I2C2_ER_IRQHandler // I2C2 Error
.word SPI1_IRQHandler // SPI1
.word SPI2_IRQHandler // SPI2
.word USART1_IRQHandler // USART1
.word USART2_IRQHandler // USART2
.word USART3_IRQHandler // USART3
.word EINT15_10_IRQHandler // External Line[15:10]s
.word RTC_Alarm_IRQHandler // RTC Alarm (A and B) through EINT Line
.word OTG_FS_WKUP_IRQHandler // USB OTG FS Wakeup through EINT line
.word TMR8_BRK_TMR12_IRQHandler // TMR8 Break and TMR12
.word TMR8_UP_TMR13_IRQHandler // TMR8 Update and TMR13
.word TMR8_TRG_COM_TMR14_IRQHandler // TMR8 Trigger and Commutation and TMR14
.word TMR8_CC_IRQHandler // TMR8 Capture Compare
.word DMA1_STR7_IRQHandler // DMA1 Stream7
.word EMMC_IRQHandler // EMMC
.word SDIO_IRQHandler // SDIO
.word TMR5_IRQHandler // TMR5
.word SPI3_IRQHandler // SPI3
.word UART4_IRQHandler // UART4
.word UART5_IRQHandler // UART5
.word TMR6_DAC_IRQHandler // TMR6 and DAC1&2 underrun errors
.word TMR7_IRQHandler // TMR7
.word DMA2_STR0_IRQHandler // DMA2 Stream 0
.word DMA2_STR1_IRQHandler // DMA2 Stream 1
.word DMA2_STR2_IRQHandler // DMA2 Stream 2
.word DMA2_STR3_IRQHandler // DMA2 Stream 3
.word DMA2_STR4_IRQHandler // DMA2 Stream 4
.word ETH_IRQHandler // Ethernet
.word ETH_WKUP_IRQHandler // Ethernet Wakeup through EINT line
.word CAN2_TX_IRQHandler // CAN2 TX
.word CAN2_RX0_IRQHandler // CAN2 RX0
.word CAN2_RX1_IRQHandler // CAN2 RX1
.word CAN2_SCE_IRQHandler // CAN2 SCE
.word OTG_FS_IRQHandler // USB OTG FS
.word DMA2_STR5_IRQHandler // DMA2 Stream 5
.word DMA2_STR6_IRQHandler // DMA2 Stream 6
.word DMA2_STR7_IRQHandler // DMA2 Stream 7
.word USART6_IRQHandler // USART6
.word I2C3_EV_IRQHandler // I2C3 event
.word I2C3_ER_IRQHandler // I2C3 error
.word OTG_HS1_EP1_OUT_IRQHandler // USB OTG HS End Point 1 Out
.word OTG_HS1_EP1_IN_IRQHandler // USB OTG HS End Point 1 In
.word OTG_HS1_WKUP_IRQHandler // USB OTG HS Wakeup through EINT
.word OTG_HS1_IRQHandler // USB OTG HS
.word DCI_IRQHandler // DCI
.word CRYP_IRQHandler // CRYP crypto
.word HASH_RNG_IRQHandler // Hash and Rng
.word FPU_IRQHandler // FPU
.word SM3_IRQHandler // SM3
.word SM4_IRQHandler // SM4
.word BN_IRQHandler // BN
// Default exception/interrupt handler
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDT_IRQHandler
.thumb_set WWDT_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCM_IRQHandler
.thumb_set RCM_IRQHandler,Default_Handler
.weak EINT0_IRQHandler
.thumb_set EINT0_IRQHandler,Default_Handler
.weak EINT1_IRQHandler
.thumb_set EINT1_IRQHandler,Default_Handler
.weak EINT2_IRQHandler
.thumb_set EINT2_IRQHandler,Default_Handler
.weak EINT3_IRQHandler
.thumb_set EINT3_IRQHandler,Default_Handler
.weak EINT4_IRQHandler
.thumb_set EINT4_IRQHandler,Default_Handler
.weak DMA1_STR0_IRQHandler
.thumb_set DMA1_STR0_IRQHandler,Default_Handler
.weak DMA1_STR1_IRQHandler
.thumb_set DMA1_STR1_IRQHandler,Default_Handler
.weak DMA1_STR2_IRQHandler
.thumb_set DMA1_STR2_IRQHandler,Default_Handler
.weak DMA1_STR3_IRQHandler
.thumb_set DMA1_STR3_IRQHandler,Default_Handler
.weak DMA1_STR4_IRQHandler
.thumb_set DMA1_STR4_IRQHandler,Default_Handler
.weak DMA1_STR5_IRQHandler
.thumb_set DMA1_STR5_IRQHandler,Default_Handler
.weak DMA1_STR6_IRQHandler
.thumb_set DMA1_STR6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EINT9_5_IRQHandler
.thumb_set EINT9_5_IRQHandler,Default_Handler
.weak TMR1_BRK_TMR9_IRQHandler
.thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
.weak TMR1_UP_TMR10_IRQHandler
.thumb_set TMR1_UP_TMR10_IRQHandler,Default_Handler
.weak TMR1_TRG_COM_TMR11_IRQHandler
.thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
.weak TMR1_CC_IRQHandler
.thumb_set TMR1_CC_IRQHandler,Default_Handler
.weak TMR2_IRQHandler
.thumb_set TMR2_IRQHandler,Default_Handler
.weak TMR3_IRQHandler
.thumb_set TMR3_IRQHandler,Default_Handler
.weak TMR4_IRQHandler
.thumb_set TMR4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EINT15_10_IRQHandler
.thumb_set EINT15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TMR8_BRK_TMR12_IRQHandler
.thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
.weak TMR8_UP_TMR13_IRQHandler
.thumb_set TMR8_UP_TMR13_IRQHandler,Default_Handler
.weak TMR8_TRG_COM_TMR14_IRQHandler
.thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
.weak TMR8_CC_IRQHandler
.thumb_set TMR8_CC_IRQHandler,Default_Handler
.weak DMA1_STR7_IRQHandler
.thumb_set DMA1_STR7_IRQHandler,Default_Handler
.weak EMMC_IRQHandler
.thumb_set EMMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TMR5_IRQHandler
.thumb_set TMR5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TMR6_DAC_IRQHandler
.thumb_set TMR6_DAC_IRQHandler,Default_Handler
.weak TMR7_IRQHandler
.thumb_set TMR7_IRQHandler,Default_Handler
.weak DMA2_STR0_IRQHandler
.thumb_set DMA2_STR0_IRQHandler,Default_Handler
.weak DMA2_STR1_IRQHandler
.thumb_set DMA2_STR1_IRQHandler,Default_Handler
.weak DMA2_STR2_IRQHandler
.thumb_set DMA2_STR2_IRQHandler,Default_Handler
.weak DMA2_STR3_IRQHandler
.thumb_set DMA2_STR3_IRQHandler,Default_Handler
.weak DMA2_STR4_IRQHandler
.thumb_set DMA2_STR4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_STR5_IRQHandler
.thumb_set DMA2_STR5_IRQHandler,Default_Handler
.weak DMA2_STR6_IRQHandler
.thumb_set DMA2_STR6_IRQHandler,Default_Handler
.weak DMA2_STR7_IRQHandler
.thumb_set DMA2_STR7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS1_EP1_OUT_IRQHandler
.thumb_set OTG_HS1_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS1_EP1_IN_IRQHandler
.thumb_set OTG_HS1_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS1_WKUP_IRQHandler
.thumb_set OTG_HS1_WKUP_IRQHandler,Default_Handler
.weak OTG_HS1_IRQHandler
.thumb_set OTG_HS1_IRQHandler,Default_Handler
.weak DCI_IRQHandler
.thumb_set DCI_IRQHandler,Default_Handler
.weak CRYP_IRQHandler
.thumb_set CRYP_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak SM3_IRQHandler
.thumb_set SM3_IRQHandler,Default_Handler
.weak SM4_IRQHandler
.thumb_set SM4_IRQHandler,Default_Handler
.weak BN_IRQHandler
.thumb_set BN_IRQHandler,Default_Handler

485
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/gcc/startup_apm32f465xx.S Normal file
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@ -0,0 +1,485 @@
/**
* @file startup_apm32f465xx.S
*
* @brief APM32F465xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*
* @version V1.0.0
*
* @date 2023-12-01
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_apm32_Vectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _start_address_init_data
/* start address for the .data section. defined in linker script */
.word _start_address_data
/* end address for the .data section. defined in linker script */
.word _end_address_data
/* start address for the .bss section. defined in linker script */
.word _start_address_bss
/* end address for the .bss section. defined in linker script */
.word _end_address_bss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
// Reset handler routine
Reset_Handler:
ldr sp, =_end_stack
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_start_address_data
ldr r1, =_end_address_data
ldr r2, =_start_address_init_data
movs r3, #0
b L_loop0_0
L_loop0:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
L_loop0_0:
adds r4, r0, r3
cmp r4, r1
bcc L_loop0
ldr r2, =_start_address_bss
ldr r4, =_end_address_bss
movs r3, #0
b L_loop1
L_loop2:
str r3, [r2]
adds r2, r2, #4
L_loop1:
cmp r2, r4
bcc L_loop2
bl SystemInit
bl __libc_init_array
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
// This is the code that gets called when the processor receives an unexpected interrupt.
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
// The minimal vector table for a Cortex M4.
.section .apm32_isr_vector,"a",%progbits
.type g_apm32_Vectors, %object
.size g_apm32_Vectors, .-g_apm32_Vectors
// Vector Table Mapped to Address 0 at Reset
g_apm32_Vectors:
.word _end_stack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
/* External Interrupts */
.word WWDT_IRQHandler // Window WatchDog
.word PVD_IRQHandler // PVD through EINT Line detection
.word TAMP_STAMP_IRQHandler // Tamper and TimeStamps through the EINT line
.word RTC_WKUP_IRQHandler // RTC Wakeup through the EINT line
.word FLASH_IRQHandler // FLASH
.word RCM_IRQHandler // RCM
.word EINT0_IRQHandler // EINT Line0
.word EINT1_IRQHandler // EINT Line1
.word EINT2_IRQHandler // EINT Line2
.word EINT3_IRQHandler // EINT Line3
.word EINT4_IRQHandler // EINT Line4
.word DMA1_STR0_IRQHandler // DMA1 Stream 0
.word DMA1_STR1_IRQHandler // DMA1 Stream 1
.word DMA1_STR2_IRQHandler // DMA1 Stream 2
.word DMA1_STR3_IRQHandler // DMA1 Stream 3
.word DMA1_STR4_IRQHandler // DMA1 Stream 4
.word DMA1_STR5_IRQHandler // DMA1 Stream 5
.word DMA1_STR6_IRQHandler // DMA1 Stream 6
.word ADC_IRQHandler // ADC1, ADC2 and ADC3s
.word CAN1_TX_IRQHandler // CAN1 TX
.word CAN1_RX0_IRQHandler // CAN1 RX0
.word CAN1_RX1_IRQHandler // CAN1 RX1
.word CAN1_SCE_IRQHandler // CAN1 SCE
.word EINT9_5_IRQHandler // External Line[9:5]s
.word TMR1_BRK_TMR9_IRQHandler // TMR1 Break and TMR9
.word TMR1_UP_TMR10_IRQHandler // TMR1 Update and TMR10
.word TMR1_TRG_COM_TMR11_IRQHandler // TMR1 Trigger and Commutation and TMR11
.word TMR1_CC_IRQHandler // TMR1 Capture Compare
.word TMR2_IRQHandler // TMR2
.word TMR3_IRQHandler // TMR3
.word TMR4_IRQHandler // TMR4
.word I2C1_EV_IRQHandler // I2C1 Event
.word I2C1_ER_IRQHandler // I2C1 Error
.word I2C2_EV_IRQHandler // I2C2 Event
.word I2C2_ER_IRQHandler // I2C2 Error
.word SPI1_IRQHandler // SPI1
.word SPI2_IRQHandler // SPI2
.word USART1_IRQHandler // USART1
.word USART2_IRQHandler // USART2
.word USART3_IRQHandler // USART3
.word EINT15_10_IRQHandler // External Line[15:10]s
.word RTC_Alarm_IRQHandler // RTC Alarm (A and B) through EINT Line
.word OTG_FS_WKUP_IRQHandler // USB OTG FS Wakeup through EINT line
.word TMR8_BRK_TMR12_IRQHandler // TMR8 Break and TMR12
.word TMR8_UP_TMR13_IRQHandler // TMR8 Update and TMR13
.word TMR8_TRG_COM_TMR14_IRQHandler // TMR8 Trigger and Commutation and TMR14
.word TMR8_CC_IRQHandler // TMR8 Capture Compare
.word DMA1_STR7_IRQHandler // DMA1 Stream7
.word SMC_IRQHandler // SMC
.word SDIO_IRQHandler // SDIO
.word TMR5_IRQHandler // TMR5
.word SPI3_IRQHandler // SPI3
.word UART4_IRQHandler // UART4
.word UART5_IRQHandler // UART5
.word TMR6_DAC_IRQHandler // TMR6 and DAC1&2 underrun errors
.word TMR7_IRQHandler // TMR7
.word DMA2_STR0_IRQHandler // DMA2 Stream 0
.word DMA2_STR1_IRQHandler // DMA2 Stream 1
.word DMA2_STR2_IRQHandler // DMA2 Stream 2
.word DMA2_STR3_IRQHandler // DMA2 Stream 3
.word DMA2_STR4_IRQHandler // DMA2 Stream 4
.word 0 // Reserved
.word 0 // Reserved
.word CAN2_TX_IRQHandler // CAN2 TX
.word CAN2_RX0_IRQHandler // CAN2 RX0
.word CAN2_RX1_IRQHandler // CAN2 RX1
.word CAN2_SCE_IRQHandler // CAN2 SCE
.word OTG_FS_IRQHandler // USB OTG FS
.word DMA2_STR5_IRQHandler // DMA2 Stream 5
.word DMA2_STR6_IRQHandler // DMA2 Stream 6
.word DMA2_STR7_IRQHandler // DMA2 Stream 7
.word USART6_IRQHandler // USART6
.word I2C3_EV_IRQHandler // I2C3 event
.word I2C3_ER_IRQHandler // I2C3 error
.word OTG_HS1_EP1_OUT_IRQHandler // USB OTG HS End Point 1 Out
.word OTG_HS1_EP1_IN_IRQHandler // USB OTG HS End Point 1 In
.word OTG_HS1_WKUP_IRQHandler // USB OTG HS Wakeup through EINT
.word OTG_HS1_IRQHandler // USB OTG HS
.word 0 // Reserved
.word 0 // Reserved
.word RNG_IRQHandler // RNG
.word FPU_IRQHandler // FPU
.word SM3_IRQHandler // SM3
.word SM4_IRQHandler // SM4
.word BN_IRQHandler // BN
// Default exception/interrupt handler
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDT_IRQHandler
.thumb_set WWDT_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCM_IRQHandler
.thumb_set RCM_IRQHandler,Default_Handler
.weak EINT0_IRQHandler
.thumb_set EINT0_IRQHandler,Default_Handler
.weak EINT1_IRQHandler
.thumb_set EINT1_IRQHandler,Default_Handler
.weak EINT2_IRQHandler
.thumb_set EINT2_IRQHandler,Default_Handler
.weak EINT3_IRQHandler
.thumb_set EINT3_IRQHandler,Default_Handler
.weak EINT4_IRQHandler
.thumb_set EINT4_IRQHandler,Default_Handler
.weak DMA1_STR0_IRQHandler
.thumb_set DMA1_STR0_IRQHandler,Default_Handler
.weak DMA1_STR1_IRQHandler
.thumb_set DMA1_STR1_IRQHandler,Default_Handler
.weak DMA1_STR2_IRQHandler
.thumb_set DMA1_STR2_IRQHandler,Default_Handler
.weak DMA1_STR3_IRQHandler
.thumb_set DMA1_STR3_IRQHandler,Default_Handler
.weak DMA1_STR4_IRQHandler
.thumb_set DMA1_STR4_IRQHandler,Default_Handler
.weak DMA1_STR5_IRQHandler
.thumb_set DMA1_STR5_IRQHandler,Default_Handler
.weak DMA1_STR6_IRQHandler
.thumb_set DMA1_STR6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EINT9_5_IRQHandler
.thumb_set EINT9_5_IRQHandler,Default_Handler
.weak TMR1_BRK_TMR9_IRQHandler
.thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
.weak TMR1_UP_TMR10_IRQHandler
.thumb_set TMR1_UP_TMR10_IRQHandler,Default_Handler
.weak TMR1_TRG_COM_TMR11_IRQHandler
.thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
.weak TMR1_CC_IRQHandler
.thumb_set TMR1_CC_IRQHandler,Default_Handler
.weak TMR2_IRQHandler
.thumb_set TMR2_IRQHandler,Default_Handler
.weak TMR3_IRQHandler
.thumb_set TMR3_IRQHandler,Default_Handler
.weak TMR4_IRQHandler
.thumb_set TMR4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EINT15_10_IRQHandler
.thumb_set EINT15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TMR8_BRK_TMR12_IRQHandler
.thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
.weak TMR8_UP_TMR13_IRQHandler
.thumb_set TMR8_UP_TMR13_IRQHandler,Default_Handler
.weak TMR8_TRG_COM_TMR14_IRQHandler
.thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
.weak TMR8_CC_IRQHandler
.thumb_set TMR8_CC_IRQHandler,Default_Handler
.weak DMA1_STR7_IRQHandler
.thumb_set DMA1_STR7_IRQHandler,Default_Handler
.weak SMC_IRQHandler
.thumb_set SMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TMR5_IRQHandler
.thumb_set TMR5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TMR6_DAC_IRQHandler
.thumb_set TMR6_DAC_IRQHandler,Default_Handler
.weak TMR7_IRQHandler
.thumb_set TMR7_IRQHandler,Default_Handler
.weak DMA2_STR0_IRQHandler
.thumb_set DMA2_STR0_IRQHandler,Default_Handler
.weak DMA2_STR1_IRQHandler
.thumb_set DMA2_STR1_IRQHandler,Default_Handler
.weak DMA2_STR2_IRQHandler
.thumb_set DMA2_STR2_IRQHandler,Default_Handler
.weak DMA2_STR3_IRQHandler
.thumb_set DMA2_STR3_IRQHandler,Default_Handler
.weak DMA2_STR4_IRQHandler
.thumb_set DMA2_STR4_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_STR5_IRQHandler
.thumb_set DMA2_STR5_IRQHandler,Default_Handler
.weak DMA2_STR6_IRQHandler
.thumb_set DMA2_STR6_IRQHandler,Default_Handler
.weak DMA2_STR7_IRQHandler
.thumb_set DMA2_STR7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS1_EP1_OUT_IRQHandler
.thumb_set OTG_HS1_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS1_EP1_IN_IRQHandler
.thumb_set OTG_HS1_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS1_WKUP_IRQHandler
.thumb_set OTG_HS1_WKUP_IRQHandler,Default_Handler
.weak OTG_HS1_IRQHandler
.thumb_set OTG_HS1_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak SM3_IRQHandler
.thumb_set SM3_IRQHandler,Default_Handler
.weak SM4_IRQHandler
.thumb_set SM4_IRQHandler,Default_Handler
.weak BN_IRQHandler
.thumb_set BN_IRQHandler,Default_Handler

172
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/iar/apm32f405xG.icf Normal file
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@ -0,0 +1,172 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x080FFFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x10000000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x1000FFFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define symbol use_IROM1 = (__ICFEDIT_region_IROM1_start__ != 0x0 || __ICFEDIT_region_IROM1_end__ != 0x0);
define symbol use_IROM2 = (__ICFEDIT_region_IROM2_start__ != 0x0 || __ICFEDIT_region_IROM2_end__ != 0x0);
define symbol use_EROM1 = (__ICFEDIT_region_EROM1_start__ != 0x0 || __ICFEDIT_region_EROM1_end__ != 0x0);
define symbol use_EROM2 = (__ICFEDIT_region_EROM2_start__ != 0x0 || __ICFEDIT_region_EROM2_end__ != 0x0);
define symbol use_EROM3 = (__ICFEDIT_region_EROM3_start__ != 0x0 || __ICFEDIT_region_EROM3_end__ != 0x0);
define symbol use_IRAM1 = (__ICFEDIT_region_IRAM1_start__ != 0x0 || __ICFEDIT_region_IRAM1_end__ != 0x0);
define symbol use_IRAM2 = (__ICFEDIT_region_IRAM2_start__ != 0x0 || __ICFEDIT_region_IRAM2_end__ != 0x0);
define symbol use_ERAM1 = (__ICFEDIT_region_ERAM1_start__ != 0x0 || __ICFEDIT_region_ERAM1_end__ != 0x0);
define symbol use_ERAM2 = (__ICFEDIT_region_ERAM2_start__ != 0x0 || __ICFEDIT_region_ERAM2_end__ != 0x0);
define symbol use_ERAM3 = (__ICFEDIT_region_ERAM3_start__ != 0x0 || __ICFEDIT_region_ERAM3_end__ != 0x0);
if (use_IROM1)
{
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
}
else
{
define region IROM1_region = [];
}
if (use_IROM2)
{
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
}
else
{
define region IROM2_region = [];
}
define region IROM_region = IROM1_region | IROM2_region;
if (use_EROM1)
{
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
}
else
{
define region EROM1_region = [];
}
if (use_EROM2)
{
define region EROM2_region = mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__];
}
else
{
define region EROM2_region = [];
}
if (use_EROM3)
{
define region EROM3_region = mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
}
else
{
define region EROM3_region = [];
}
define region EROM_region = EROM1_region | EROM2_region | EROM3_region;
if (use_IRAM1)
{
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
}
else
{
define region IRAM1_region = [];
}
if (use_IRAM2)
{
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
}
else
{
define region IRAM2_region = [];
}
define region IRAM_region = IRAM1_region;
define region TCMRAM_region = IRAM2_region;
if (use_ERAM1)
{
define region ERAM1_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__];
}
else
{
define region ERAM1_region = [];
}
if (use_ERAM2)
{
define region ERAM2_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__];
}
else
{
define region ERAM2_region = [];
}
if (use_ERAM3)
{
define region ERAM3_region = mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
}
else
{
define region ERAM3_region = [];
}
define region ERAM_region = ERAM1_region | ERAM2_region | ERAM3_region;
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
if (!isempty(IROM_region))
{
place in IROM_region { readonly };
}
if (!isempty(EROM_region))
{
place in EROM_region { readonly section application_specific_ro };
}
if (!isempty(IRAM_region))
{
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
}
if (!isempty(TCMRAM_region))
{
place in TCMRAM_region { section .textrw };
}
if (!isempty(ERAM_region))
{
place in ERAM_region { readwrite section application_specific_rw };
}

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x0807FFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x10000000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x1000FFFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define symbol use_IROM1 = (__ICFEDIT_region_IROM1_start__ != 0x0 || __ICFEDIT_region_IROM1_end__ != 0x0);
define symbol use_IROM2 = (__ICFEDIT_region_IROM2_start__ != 0x0 || __ICFEDIT_region_IROM2_end__ != 0x0);
define symbol use_EROM1 = (__ICFEDIT_region_EROM1_start__ != 0x0 || __ICFEDIT_region_EROM1_end__ != 0x0);
define symbol use_EROM2 = (__ICFEDIT_region_EROM2_start__ != 0x0 || __ICFEDIT_region_EROM2_end__ != 0x0);
define symbol use_EROM3 = (__ICFEDIT_region_EROM3_start__ != 0x0 || __ICFEDIT_region_EROM3_end__ != 0x0);
define symbol use_IRAM1 = (__ICFEDIT_region_IRAM1_start__ != 0x0 || __ICFEDIT_region_IRAM1_end__ != 0x0);
define symbol use_IRAM2 = (__ICFEDIT_region_IRAM2_start__ != 0x0 || __ICFEDIT_region_IRAM2_end__ != 0x0);
define symbol use_ERAM1 = (__ICFEDIT_region_ERAM1_start__ != 0x0 || __ICFEDIT_region_ERAM1_end__ != 0x0);
define symbol use_ERAM2 = (__ICFEDIT_region_ERAM2_start__ != 0x0 || __ICFEDIT_region_ERAM2_end__ != 0x0);
define symbol use_ERAM3 = (__ICFEDIT_region_ERAM3_start__ != 0x0 || __ICFEDIT_region_ERAM3_end__ != 0x0);
if (use_IROM1)
{
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
}
else
{
define region IROM1_region = [];
}
if (use_IROM2)
{
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
}
else
{
define region IROM2_region = [];
}
define region IROM_region = IROM1_region | IROM2_region;
if (use_EROM1)
{
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
}
else
{
define region EROM1_region = [];
}
if (use_EROM2)
{
define region EROM2_region = mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__];
}
else
{
define region EROM2_region = [];
}
if (use_EROM3)
{
define region EROM3_region = mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
}
else
{
define region EROM3_region = [];
}
define region EROM_region = EROM1_region | EROM2_region | EROM3_region;
if (use_IRAM1)
{
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
}
else
{
define region IRAM1_region = [];
}
if (use_IRAM2)
{
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
}
else
{
define region IRAM2_region = [];
}
define region IRAM_region = IRAM1_region;
define region TCMRAM_region = IRAM2_region;
if (use_ERAM1)
{
define region ERAM1_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__];
}
else
{
define region ERAM1_region = [];
}
if (use_ERAM2)
{
define region ERAM2_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__];
}
else
{
define region ERAM2_region = [];
}
if (use_ERAM3)
{
define region ERAM3_region = mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
}
else
{
define region ERAM3_region = [];
}
define region ERAM_region = ERAM1_region | ERAM2_region | ERAM3_region;
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
if (!isempty(IROM_region))
{
place in IROM_region { readonly };
}
if (!isempty(EROM_region))
{
place in EROM_region { readonly section application_specific_ro };
}
if (!isempty(IRAM_region))
{
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
}
if (!isempty(TCMRAM_region))
{
place in TCMRAM_region { section .textrw };
}
if (!isempty(ERAM_region))
{
place in ERAM_region { readwrite section application_specific_rw };
}

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x080FFFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x10000000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x1000FFFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define symbol use_IROM1 = (__ICFEDIT_region_IROM1_start__ != 0x0 || __ICFEDIT_region_IROM1_end__ != 0x0);
define symbol use_IROM2 = (__ICFEDIT_region_IROM2_start__ != 0x0 || __ICFEDIT_region_IROM2_end__ != 0x0);
define symbol use_EROM1 = (__ICFEDIT_region_EROM1_start__ != 0x0 || __ICFEDIT_region_EROM1_end__ != 0x0);
define symbol use_EROM2 = (__ICFEDIT_region_EROM2_start__ != 0x0 || __ICFEDIT_region_EROM2_end__ != 0x0);
define symbol use_EROM3 = (__ICFEDIT_region_EROM3_start__ != 0x0 || __ICFEDIT_region_EROM3_end__ != 0x0);
define symbol use_IRAM1 = (__ICFEDIT_region_IRAM1_start__ != 0x0 || __ICFEDIT_region_IRAM1_end__ != 0x0);
define symbol use_IRAM2 = (__ICFEDIT_region_IRAM2_start__ != 0x0 || __ICFEDIT_region_IRAM2_end__ != 0x0);
define symbol use_ERAM1 = (__ICFEDIT_region_ERAM1_start__ != 0x0 || __ICFEDIT_region_ERAM1_end__ != 0x0);
define symbol use_ERAM2 = (__ICFEDIT_region_ERAM2_start__ != 0x0 || __ICFEDIT_region_ERAM2_end__ != 0x0);
define symbol use_ERAM3 = (__ICFEDIT_region_ERAM3_start__ != 0x0 || __ICFEDIT_region_ERAM3_end__ != 0x0);
if (use_IROM1)
{
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
}
else
{
define region IROM1_region = [];
}
if (use_IROM2)
{
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
}
else
{
define region IROM2_region = [];
}
define region IROM_region = IROM1_region | IROM2_region;
if (use_EROM1)
{
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
}
else
{
define region EROM1_region = [];
}
if (use_EROM2)
{
define region EROM2_region = mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__];
}
else
{
define region EROM2_region = [];
}
if (use_EROM3)
{
define region EROM3_region = mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
}
else
{
define region EROM3_region = [];
}
define region EROM_region = EROM1_region | EROM2_region | EROM3_region;
if (use_IRAM1)
{
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
}
else
{
define region IRAM1_region = [];
}
if (use_IRAM2)
{
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
}
else
{
define region IRAM2_region = [];
}
define region IRAM_region = IRAM1_region;
define region TCMRAM_region = IRAM2_region;
if (use_ERAM1)
{
define region ERAM1_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__];
}
else
{
define region ERAM1_region = [];
}
if (use_ERAM2)
{
define region ERAM2_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__];
}
else
{
define region ERAM2_region = [];
}
if (use_ERAM3)
{
define region ERAM3_region = mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
}
else
{
define region ERAM3_region = [];
}
define region ERAM_region = ERAM1_region | ERAM2_region | ERAM3_region;
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
if (!isempty(IROM_region))
{
place in IROM_region { readonly };
}
if (!isempty(EROM_region))
{
place in EROM_region { readonly section application_specific_ro };
}
if (!isempty(IRAM_region))
{
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
}
if (!isempty(TCMRAM_region))
{
place in TCMRAM_region { section .textrw };
}
if (!isempty(ERAM_region))
{
place in ERAM_region { readwrite section application_specific_rw };
}

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x0803FFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define symbol use_IROM1 = (__ICFEDIT_region_IROM1_start__ != 0x0 || __ICFEDIT_region_IROM1_end__ != 0x0);
define symbol use_IROM2 = (__ICFEDIT_region_IROM2_start__ != 0x0 || __ICFEDIT_region_IROM2_end__ != 0x0);
define symbol use_EROM1 = (__ICFEDIT_region_EROM1_start__ != 0x0 || __ICFEDIT_region_EROM1_end__ != 0x0);
define symbol use_EROM2 = (__ICFEDIT_region_EROM2_start__ != 0x0 || __ICFEDIT_region_EROM2_end__ != 0x0);
define symbol use_EROM3 = (__ICFEDIT_region_EROM3_start__ != 0x0 || __ICFEDIT_region_EROM3_end__ != 0x0);
define symbol use_IRAM1 = (__ICFEDIT_region_IRAM1_start__ != 0x0 || __ICFEDIT_region_IRAM1_end__ != 0x0);
define symbol use_IRAM2 = (__ICFEDIT_region_IRAM2_start__ != 0x0 || __ICFEDIT_region_IRAM2_end__ != 0x0);
define symbol use_ERAM1 = (__ICFEDIT_region_ERAM1_start__ != 0x0 || __ICFEDIT_region_ERAM1_end__ != 0x0);
define symbol use_ERAM2 = (__ICFEDIT_region_ERAM2_start__ != 0x0 || __ICFEDIT_region_ERAM2_end__ != 0x0);
define symbol use_ERAM3 = (__ICFEDIT_region_ERAM3_start__ != 0x0 || __ICFEDIT_region_ERAM3_end__ != 0x0);
if (use_IROM1)
{
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
}
else
{
define region IROM1_region = [];
}
if (use_IROM2)
{
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
}
else
{
define region IROM2_region = [];
}
define region IROM_region = IROM1_region | IROM2_region;
if (use_EROM1)
{
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
}
else
{
define region EROM1_region = [];
}
if (use_EROM2)
{
define region EROM2_region = mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__];
}
else
{
define region EROM2_region = [];
}
if (use_EROM3)
{
define region EROM3_region = mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
}
else
{
define region EROM3_region = [];
}
define region EROM_region = EROM1_region | EROM2_region | EROM3_region;
if (use_IRAM1)
{
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
}
else
{
define region IRAM1_region = [];
}
if (use_IRAM2)
{
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
}
else
{
define region IRAM2_region = [];
}
define region IRAM_region = IRAM1_region;
define region TCMRAM_region = IRAM2_region;
if (use_ERAM1)
{
define region ERAM1_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__];
}
else
{
define region ERAM1_region = [];
}
if (use_ERAM2)
{
define region ERAM2_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__];
}
else
{
define region ERAM2_region = [];
}
if (use_ERAM3)
{
define region ERAM3_region = mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
}
else
{
define region ERAM3_region = [];
}
define region ERAM_region = ERAM1_region | ERAM2_region | ERAM3_region;
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
if (!isempty(IROM_region))
{
place in IROM_region { readonly };
}
if (!isempty(EROM_region))
{
place in EROM_region { readonly section application_specific_ro };
}
if (!isempty(IRAM_region))
{
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
}
if (!isempty(TCMRAM_region))
{
place in TCMRAM_region { section .textrw };
}
if (!isempty(ERAM_region))
{
place in ERAM_region { readwrite section application_specific_rw };
}

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x0807FFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define symbol use_IROM1 = (__ICFEDIT_region_IROM1_start__ != 0x0 || __ICFEDIT_region_IROM1_end__ != 0x0);
define symbol use_IROM2 = (__ICFEDIT_region_IROM2_start__ != 0x0 || __ICFEDIT_region_IROM2_end__ != 0x0);
define symbol use_EROM1 = (__ICFEDIT_region_EROM1_start__ != 0x0 || __ICFEDIT_region_EROM1_end__ != 0x0);
define symbol use_EROM2 = (__ICFEDIT_region_EROM2_start__ != 0x0 || __ICFEDIT_region_EROM2_end__ != 0x0);
define symbol use_EROM3 = (__ICFEDIT_region_EROM3_start__ != 0x0 || __ICFEDIT_region_EROM3_end__ != 0x0);
define symbol use_IRAM1 = (__ICFEDIT_region_IRAM1_start__ != 0x0 || __ICFEDIT_region_IRAM1_end__ != 0x0);
define symbol use_IRAM2 = (__ICFEDIT_region_IRAM2_start__ != 0x0 || __ICFEDIT_region_IRAM2_end__ != 0x0);
define symbol use_ERAM1 = (__ICFEDIT_region_ERAM1_start__ != 0x0 || __ICFEDIT_region_ERAM1_end__ != 0x0);
define symbol use_ERAM2 = (__ICFEDIT_region_ERAM2_start__ != 0x0 || __ICFEDIT_region_ERAM2_end__ != 0x0);
define symbol use_ERAM3 = (__ICFEDIT_region_ERAM3_start__ != 0x0 || __ICFEDIT_region_ERAM3_end__ != 0x0);
if (use_IROM1)
{
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
}
else
{
define region IROM1_region = [];
}
if (use_IROM2)
{
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
}
else
{
define region IROM2_region = [];
}
define region IROM_region = IROM1_region | IROM2_region;
if (use_EROM1)
{
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
}
else
{
define region EROM1_region = [];
}
if (use_EROM2)
{
define region EROM2_region = mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__];
}
else
{
define region EROM2_region = [];
}
if (use_EROM3)
{
define region EROM3_region = mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
}
else
{
define region EROM3_region = [];
}
define region EROM_region = EROM1_region | EROM2_region | EROM3_region;
if (use_IRAM1)
{
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
}
else
{
define region IRAM1_region = [];
}
if (use_IRAM2)
{
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
}
else
{
define region IRAM2_region = [];
}
define region IRAM_region = IRAM1_region;
define region TCMRAM_region = IRAM2_region;
if (use_ERAM1)
{
define region ERAM1_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__];
}
else
{
define region ERAM1_region = [];
}
if (use_ERAM2)
{
define region ERAM2_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__];
}
else
{
define region ERAM2_region = [];
}
if (use_ERAM3)
{
define region ERAM3_region = mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
}
else
{
define region ERAM3_region = [];
}
define region ERAM_region = ERAM1_region | ERAM2_region | ERAM3_region;
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
if (!isempty(IROM_region))
{
place in IROM_region { readonly };
}
if (!isempty(EROM_region))
{
place in EROM_region { readonly section application_specific_ro };
}
if (!isempty(IRAM_region))
{
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
}
if (!isempty(TCMRAM_region))
{
place in TCMRAM_region { section .textrw };
}
if (!isempty(ERAM_region))
{
place in ERAM_region { readwrite section application_specific_rw };
}

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x0807FFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x10000000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x1000FFFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define symbol use_IROM1 = (__ICFEDIT_region_IROM1_start__ != 0x0 || __ICFEDIT_region_IROM1_end__ != 0x0);
define symbol use_IROM2 = (__ICFEDIT_region_IROM2_start__ != 0x0 || __ICFEDIT_region_IROM2_end__ != 0x0);
define symbol use_EROM1 = (__ICFEDIT_region_EROM1_start__ != 0x0 || __ICFEDIT_region_EROM1_end__ != 0x0);
define symbol use_EROM2 = (__ICFEDIT_region_EROM2_start__ != 0x0 || __ICFEDIT_region_EROM2_end__ != 0x0);
define symbol use_EROM3 = (__ICFEDIT_region_EROM3_start__ != 0x0 || __ICFEDIT_region_EROM3_end__ != 0x0);
define symbol use_IRAM1 = (__ICFEDIT_region_IRAM1_start__ != 0x0 || __ICFEDIT_region_IRAM1_end__ != 0x0);
define symbol use_IRAM2 = (__ICFEDIT_region_IRAM2_start__ != 0x0 || __ICFEDIT_region_IRAM2_end__ != 0x0);
define symbol use_ERAM1 = (__ICFEDIT_region_ERAM1_start__ != 0x0 || __ICFEDIT_region_ERAM1_end__ != 0x0);
define symbol use_ERAM2 = (__ICFEDIT_region_ERAM2_start__ != 0x0 || __ICFEDIT_region_ERAM2_end__ != 0x0);
define symbol use_ERAM3 = (__ICFEDIT_region_ERAM3_start__ != 0x0 || __ICFEDIT_region_ERAM3_end__ != 0x0);
if (use_IROM1)
{
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
}
else
{
define region IROM1_region = [];
}
if (use_IROM2)
{
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
}
else
{
define region IROM2_region = [];
}
define region IROM_region = IROM1_region | IROM2_region;
if (use_EROM1)
{
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
}
else
{
define region EROM1_region = [];
}
if (use_EROM2)
{
define region EROM2_region = mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__];
}
else
{
define region EROM2_region = [];
}
if (use_EROM3)
{
define region EROM3_region = mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
}
else
{
define region EROM3_region = [];
}
define region EROM_region = EROM1_region | EROM2_region | EROM3_region;
if (use_IRAM1)
{
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
}
else
{
define region IRAM1_region = [];
}
if (use_IRAM2)
{
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
}
else
{
define region IRAM2_region = [];
}
define region IRAM_region = IRAM1_region;
define region TCMRAM_region = IRAM2_region;
if (use_ERAM1)
{
define region ERAM1_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__];
}
else
{
define region ERAM1_region = [];
}
if (use_ERAM2)
{
define region ERAM2_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__];
}
else
{
define region ERAM2_region = [];
}
if (use_ERAM3)
{
define region ERAM3_region = mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
}
else
{
define region ERAM3_region = [];
}
define region ERAM_region = ERAM1_region | ERAM2_region | ERAM3_region;
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
if (!isempty(IROM_region))
{
place in IROM_region { readonly };
}
if (!isempty(EROM_region))
{
place in EROM_region { readonly section application_specific_ro };
}
if (!isempty(IRAM_region))
{
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
}
if (!isempty(TCMRAM_region))
{
place in TCMRAM_region { section .textrw };
}
if (!isempty(ERAM_region))
{
place in ERAM_region { readwrite section application_specific_rw };
}

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x080FFFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x10000000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x1000FFFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define symbol use_IROM1 = (__ICFEDIT_region_IROM1_start__ != 0x0 || __ICFEDIT_region_IROM1_end__ != 0x0);
define symbol use_IROM2 = (__ICFEDIT_region_IROM2_start__ != 0x0 || __ICFEDIT_region_IROM2_end__ != 0x0);
define symbol use_EROM1 = (__ICFEDIT_region_EROM1_start__ != 0x0 || __ICFEDIT_region_EROM1_end__ != 0x0);
define symbol use_EROM2 = (__ICFEDIT_region_EROM2_start__ != 0x0 || __ICFEDIT_region_EROM2_end__ != 0x0);
define symbol use_EROM3 = (__ICFEDIT_region_EROM3_start__ != 0x0 || __ICFEDIT_region_EROM3_end__ != 0x0);
define symbol use_IRAM1 = (__ICFEDIT_region_IRAM1_start__ != 0x0 || __ICFEDIT_region_IRAM1_end__ != 0x0);
define symbol use_IRAM2 = (__ICFEDIT_region_IRAM2_start__ != 0x0 || __ICFEDIT_region_IRAM2_end__ != 0x0);
define symbol use_ERAM1 = (__ICFEDIT_region_ERAM1_start__ != 0x0 || __ICFEDIT_region_ERAM1_end__ != 0x0);
define symbol use_ERAM2 = (__ICFEDIT_region_ERAM2_start__ != 0x0 || __ICFEDIT_region_ERAM2_end__ != 0x0);
define symbol use_ERAM3 = (__ICFEDIT_region_ERAM3_start__ != 0x0 || __ICFEDIT_region_ERAM3_end__ != 0x0);
if (use_IROM1)
{
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
}
else
{
define region IROM1_region = [];
}
if (use_IROM2)
{
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
}
else
{
define region IROM2_region = [];
}
define region IROM_region = IROM1_region | IROM2_region;
if (use_EROM1)
{
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
}
else
{
define region EROM1_region = [];
}
if (use_EROM2)
{
define region EROM2_region = mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__];
}
else
{
define region EROM2_region = [];
}
if (use_EROM3)
{
define region EROM3_region = mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
}
else
{
define region EROM3_region = [];
}
define region EROM_region = EROM1_region | EROM2_region | EROM3_region;
if (use_IRAM1)
{
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
}
else
{
define region IRAM1_region = [];
}
if (use_IRAM2)
{
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
}
else
{
define region IRAM2_region = [];
}
define region IRAM_region = IRAM1_region;
define region TCMRAM_region = IRAM2_region;
if (use_ERAM1)
{
define region ERAM1_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__];
}
else
{
define region ERAM1_region = [];
}
if (use_ERAM2)
{
define region ERAM2_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__];
}
else
{
define region ERAM2_region = [];
}
if (use_ERAM3)
{
define region ERAM3_region = mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
}
else
{
define region ERAM3_region = [];
}
define region ERAM_region = ERAM1_region | ERAM2_region | ERAM3_region;
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
if (!isempty(IROM_region))
{
place in IROM_region { readonly };
}
if (!isempty(EROM_region))
{
place in EROM_region { readonly section application_specific_ro };
}
if (!isempty(IRAM_region))
{
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
}
if (!isempty(TCMRAM_region))
{
place in TCMRAM_region { section .textrw };
}
if (!isempty(ERAM_region))
{
place in ERAM_region { readwrite section application_specific_rw };
}

172
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/iar/apm32f465xE.icf Normal file
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@ -0,0 +1,172 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x080FFFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x1000FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define symbol use_IROM1 = (__ICFEDIT_region_IROM1_start__ != 0x0 || __ICFEDIT_region_IROM1_end__ != 0x0);
define symbol use_IROM2 = (__ICFEDIT_region_IROM2_start__ != 0x0 || __ICFEDIT_region_IROM2_end__ != 0x0);
define symbol use_EROM1 = (__ICFEDIT_region_EROM1_start__ != 0x0 || __ICFEDIT_region_EROM1_end__ != 0x0);
define symbol use_EROM2 = (__ICFEDIT_region_EROM2_start__ != 0x0 || __ICFEDIT_region_EROM2_end__ != 0x0);
define symbol use_EROM3 = (__ICFEDIT_region_EROM3_start__ != 0x0 || __ICFEDIT_region_EROM3_end__ != 0x0);
define symbol use_IRAM1 = (__ICFEDIT_region_IRAM1_start__ != 0x0 || __ICFEDIT_region_IRAM1_end__ != 0x0);
define symbol use_IRAM2 = (__ICFEDIT_region_IRAM2_start__ != 0x0 || __ICFEDIT_region_IRAM2_end__ != 0x0);
define symbol use_ERAM1 = (__ICFEDIT_region_ERAM1_start__ != 0x0 || __ICFEDIT_region_ERAM1_end__ != 0x0);
define symbol use_ERAM2 = (__ICFEDIT_region_ERAM2_start__ != 0x0 || __ICFEDIT_region_ERAM2_end__ != 0x0);
define symbol use_ERAM3 = (__ICFEDIT_region_ERAM3_start__ != 0x0 || __ICFEDIT_region_ERAM3_end__ != 0x0);
if (use_IROM1)
{
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
}
else
{
define region IROM1_region = [];
}
if (use_IROM2)
{
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
}
else
{
define region IROM2_region = [];
}
define region IROM_region = IROM1_region | IROM2_region;
if (use_EROM1)
{
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
}
else
{
define region EROM1_region = [];
}
if (use_EROM2)
{
define region EROM2_region = mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__];
}
else
{
define region EROM2_region = [];
}
if (use_EROM3)
{
define region EROM3_region = mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
}
else
{
define region EROM3_region = [];
}
define region EROM_region = EROM1_region | EROM2_region | EROM3_region;
if (use_IRAM1)
{
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
}
else
{
define region IRAM1_region = [];
}
if (use_IRAM2)
{
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
}
else
{
define region IRAM2_region = [];
}
define region IRAM_region = IRAM1_region;
define region TCMRAM_region = IRAM2_region;
if (use_ERAM1)
{
define region ERAM1_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__];
}
else
{
define region ERAM1_region = [];
}
if (use_ERAM2)
{
define region ERAM2_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__];
}
else
{
define region ERAM2_region = [];
}
if (use_ERAM3)
{
define region ERAM3_region = mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
}
else
{
define region ERAM3_region = [];
}
define region ERAM_region = ERAM1_region | ERAM2_region | ERAM3_region;
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
if (!isempty(IROM_region))
{
place in IROM_region { readonly };
}
if (!isempty(EROM_region))
{
place in EROM_region { readonly section application_specific_ro };
}
if (!isempty(IRAM_region))
{
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
}
if (!isempty(TCMRAM_region))
{
place in TCMRAM_region { section .textrw };
}
if (!isempty(ERAM_region))
{
place in ERAM_region { readwrite section application_specific_rw };
}

608
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/iar/startup_apm32f405xx.s Normal file
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@ -0,0 +1,608 @@
;/**
; * @file startup_apm32f405xx.s
; *
; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f405xx
; *
; * @version V1.0.0
; *
; * @date 2023-07-31
; *
; * @attention
; *
; * Copyright (C) 2023 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EINT Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EINT line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EINT line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line0
DCD EINT1_IRQHandler ; EINT Line1
DCD EINT2_IRQHandler ; EINT Line2
DCD EINT3_IRQHandler ; EINT Line3
DCD EINT4_IRQHandler ; EINT Line4
DCD DMA1_STR0_IRQHandler ; DMA1 Stream 0
DCD DMA1_STR1_IRQHandler ; DMA1 Stream 1
DCD DMA1_STR2_IRQHandler ; DMA1 Stream 2
DCD DMA1_STR3_IRQHandler ; DMA1 Stream 3
DCD DMA1_STR4_IRQHandler ; DMA1 Stream 4
DCD DMA1_STR5_IRQHandler ; DMA1 Stream 5
DCD DMA1_STR6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; External Line[9:5]s
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
DCD TMR1_UP_TMR10_IRQHandler ; TMR1 Update and TMR10
DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EINT Line
DCD OTG_FS_WKUP_IRQHandler ; OTG_FS Wakeup through EINT line
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
DCD TMR8_UP_TMR13_IRQHandler ; TMR8 Update and TMR13
DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD DMA1_STR7_IRQHandler ; DMA1 Stream 7
DCD EMMC_IRQHandler ; EMMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_DAC_IRQHandler ; TMR6 and DAC1&2 underrun errors
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; OTG_FS
DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS1_EP1_OUT_IRQHandler ; OTG_HS1 End Point 1 Out
DCD OTG_HS1_EP1_IN_IRQHandler ; OTG_HS1 End Point 1 In
DCD OTG_HS1_WKUP_IRQHandler ; OTG_HS1 Wakeup through EINT
DCD OTG_HS1_IRQHandler ; OTG_HS1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD SM3_IRQHandler ; SM3
DCD SM4_IRQHandler ; SM4
DCD BN_IRQHandler ; BN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDT_IRQHandler
B WWDT_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCM_IRQHandler
B RCM_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT4_IRQHandler
B EINT4_IRQHandler
PUBWEAK DMA1_STR0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR0_IRQHandler
B DMA1_STR0_IRQHandler
PUBWEAK DMA1_STR1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR1_IRQHandler
B DMA1_STR1_IRQHandler
PUBWEAK DMA1_STR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR2_IRQHandler
B DMA1_STR2_IRQHandler
PUBWEAK DMA1_STR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR3_IRQHandler
B DMA1_STR3_IRQHandler
PUBWEAK DMA1_STR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR4_IRQHandler
B DMA1_STR4_IRQHandler
PUBWEAK DMA1_STR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR5_IRQHandler
B DMA1_STR5_IRQHandler
PUBWEAK DMA1_STR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR6_IRQHandler
B DMA1_STR6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EINT9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT9_5_IRQHandler
B EINT9_5_IRQHandler
PUBWEAK TMR1_BRK_TMR9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_BRK_TMR9_IRQHandler
B TMR1_BRK_TMR9_IRQHandler
PUBWEAK TMR1_UP_TMR10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_UP_TMR10_IRQHandler
B TMR1_UP_TMR10_IRQHandler
PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_TRG_COM_TMR11_IRQHandler
B TMR1_TRG_COM_TMR11_IRQHandler
PUBWEAK TMR1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_CC_IRQHandler
B TMR1_CC_IRQHandler
PUBWEAK TMR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR2_IRQHandler
B TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR3_IRQHandler
B TMR3_IRQHandler
PUBWEAK TMR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR4_IRQHandler
B TMR4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EINT15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT15_10_IRQHandler
B EINT15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TMR8_BRK_TMR12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_BRK_TMR12_IRQHandler
B TMR8_BRK_TMR12_IRQHandler
PUBWEAK TMR8_UP_TMR13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_UP_TMR13_IRQHandler
B TMR8_UP_TMR13_IRQHandler
PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_TRG_COM_TMR14_IRQHandler
B TMR8_TRG_COM_TMR14_IRQHandler
PUBWEAK TMR8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_CC_IRQHandler
B TMR8_CC_IRQHandler
PUBWEAK DMA1_STR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR7_IRQHandler
B DMA1_STR7_IRQHandler
PUBWEAK EMMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EMMC_IRQHandler
B EMMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TMR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR5_IRQHandler
B TMR5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TMR6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR6_DAC_IRQHandler
B TMR6_DAC_IRQHandler
PUBWEAK TMR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR7_IRQHandler
B TMR7_IRQHandler
PUBWEAK DMA2_STR0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR0_IRQHandler
B DMA2_STR0_IRQHandler
PUBWEAK DMA2_STR1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR1_IRQHandler
B DMA2_STR1_IRQHandler
PUBWEAK DMA2_STR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR2_IRQHandler
B DMA2_STR2_IRQHandler
PUBWEAK DMA2_STR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR3_IRQHandler
B DMA2_STR3_IRQHandler
PUBWEAK DMA2_STR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR4_IRQHandler
B DMA2_STR4_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_STR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR5_IRQHandler
B DMA2_STR5_IRQHandler
PUBWEAK DMA2_STR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR6_IRQHandler
B DMA2_STR6_IRQHandler
PUBWEAK DMA2_STR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR7_IRQHandler
B DMA2_STR7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS1_EP1_OUT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_EP1_OUT_IRQHandler
B OTG_HS1_EP1_OUT_IRQHandler
PUBWEAK OTG_HS1_EP1_IN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_EP1_IN_IRQHandler
B OTG_HS1_EP1_IN_IRQHandler
PUBWEAK OTG_HS1_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_WKUP_IRQHandler
B OTG_HS1_WKUP_IRQHandler
PUBWEAK OTG_HS1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_IRQHandler
B OTG_HS1_IRQHandler
PUBWEAK HASH_RNG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HASH_RNG_IRQHandler
B HASH_RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK SM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SM3_IRQHandler
B SM3_IRQHandler
PUBWEAK SM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SM4_IRQHandler
B SM4_IRQHandler
PUBWEAK BN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
BN_IRQHandler
B BN_IRQHandler
END

623
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@ -0,0 +1,623 @@
;/**
; * @file startup_apm32f407xx.s
; *
; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f407xx
; *
; * @version V1.0.0
; *
; * @date 2023-07-31
; *
; * @attention
; *
; * Copyright (C) 2023 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EINT Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EINT line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EINT line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line0
DCD EINT1_IRQHandler ; EINT Line1
DCD EINT2_IRQHandler ; EINT Line2
DCD EINT3_IRQHandler ; EINT Line3
DCD EINT4_IRQHandler ; EINT Line4
DCD DMA1_STR0_IRQHandler ; DMA1 Stream 0
DCD DMA1_STR1_IRQHandler ; DMA1 Stream 1
DCD DMA1_STR2_IRQHandler ; DMA1 Stream 2
DCD DMA1_STR3_IRQHandler ; DMA1 Stream 3
DCD DMA1_STR4_IRQHandler ; DMA1 Stream 4
DCD DMA1_STR5_IRQHandler ; DMA1 Stream 5
DCD DMA1_STR6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; External Line[9:5]s
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
DCD TMR1_UP_TMR10_IRQHandler ; TMR1 Update and TMR10
DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EINT Line
DCD OTG_FS_WKUP_IRQHandler ; OTG_FS Wakeup through EINT line
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
DCD TMR8_UP_TMR13_IRQHandler ; TMR8 Update and TMR13
DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD DMA1_STR7_IRQHandler ; DMA1 Stream 7
DCD EMMC_IRQHandler ; EMMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_DAC_IRQHandler ; TMR6 and DAC1&2 underrun errors
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EINT line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; OTG_FS
DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS1_EP1_OUT_IRQHandler ; OTG_HS1 End Point 1 Out
DCD OTG_HS1_EP1_IN_IRQHandler ; OTG_HS1 End Point 1 In
DCD OTG_HS1_WKUP_IRQHandler ; OTG_HS1 Wakeup through EINT
DCD OTG_HS1_IRQHandler ; OTG_HS1
DCD DCI_IRQHandler ; DCI
DCD 0 ; Reserved
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD SM3_IRQHandler ; SM3
DCD SM4_IRQHandler ; SM4
DCD BN_IRQHandler ; BN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDT_IRQHandler
B WWDT_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCM_IRQHandler
B RCM_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT4_IRQHandler
B EINT4_IRQHandler
PUBWEAK DMA1_STR0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR0_IRQHandler
B DMA1_STR0_IRQHandler
PUBWEAK DMA1_STR1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR1_IRQHandler
B DMA1_STR1_IRQHandler
PUBWEAK DMA1_STR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR2_IRQHandler
B DMA1_STR2_IRQHandler
PUBWEAK DMA1_STR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR3_IRQHandler
B DMA1_STR3_IRQHandler
PUBWEAK DMA1_STR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR4_IRQHandler
B DMA1_STR4_IRQHandler
PUBWEAK DMA1_STR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR5_IRQHandler
B DMA1_STR5_IRQHandler
PUBWEAK DMA1_STR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR6_IRQHandler
B DMA1_STR6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EINT9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT9_5_IRQHandler
B EINT9_5_IRQHandler
PUBWEAK TMR1_BRK_TMR9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_BRK_TMR9_IRQHandler
B TMR1_BRK_TMR9_IRQHandler
PUBWEAK TMR1_UP_TMR10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_UP_TMR10_IRQHandler
B TMR1_UP_TMR10_IRQHandler
PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_TRG_COM_TMR11_IRQHandler
B TMR1_TRG_COM_TMR11_IRQHandler
PUBWEAK TMR1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_CC_IRQHandler
B TMR1_CC_IRQHandler
PUBWEAK TMR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR2_IRQHandler
B TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR3_IRQHandler
B TMR3_IRQHandler
PUBWEAK TMR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR4_IRQHandler
B TMR4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EINT15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT15_10_IRQHandler
B EINT15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TMR8_BRK_TMR12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_BRK_TMR12_IRQHandler
B TMR8_BRK_TMR12_IRQHandler
PUBWEAK TMR8_UP_TMR13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_UP_TMR13_IRQHandler
B TMR8_UP_TMR13_IRQHandler
PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_TRG_COM_TMR14_IRQHandler
B TMR8_TRG_COM_TMR14_IRQHandler
PUBWEAK TMR8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_CC_IRQHandler
B TMR8_CC_IRQHandler
PUBWEAK DMA1_STR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR7_IRQHandler
B DMA1_STR7_IRQHandler
PUBWEAK EMMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EMMC_IRQHandler
B EMMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TMR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR5_IRQHandler
B TMR5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TMR6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR6_DAC_IRQHandler
B TMR6_DAC_IRQHandler
PUBWEAK TMR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR7_IRQHandler
B TMR7_IRQHandler
PUBWEAK DMA2_STR0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR0_IRQHandler
B DMA2_STR0_IRQHandler
PUBWEAK DMA2_STR1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR1_IRQHandler
B DMA2_STR1_IRQHandler
PUBWEAK DMA2_STR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR2_IRQHandler
B DMA2_STR2_IRQHandler
PUBWEAK DMA2_STR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR3_IRQHandler
B DMA2_STR3_IRQHandler
PUBWEAK DMA2_STR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR4_IRQHandler
B DMA2_STR4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_STR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR5_IRQHandler
B DMA2_STR5_IRQHandler
PUBWEAK DMA2_STR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR6_IRQHandler
B DMA2_STR6_IRQHandler
PUBWEAK DMA2_STR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR7_IRQHandler
B DMA2_STR7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS1_EP1_OUT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_EP1_OUT_IRQHandler
B OTG_HS1_EP1_OUT_IRQHandler
PUBWEAK OTG_HS1_EP1_IN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_EP1_IN_IRQHandler
B OTG_HS1_EP1_IN_IRQHandler
PUBWEAK OTG_HS1_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_WKUP_IRQHandler
B OTG_HS1_WKUP_IRQHandler
PUBWEAK OTG_HS1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_IRQHandler
B OTG_HS1_IRQHandler
PUBWEAK DCI_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DCI_IRQHandler
B DCI_IRQHandler
PUBWEAK HASH_RNG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HASH_RNG_IRQHandler
B HASH_RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK SM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SM3_IRQHandler
B SM3_IRQHandler
PUBWEAK SM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SM4_IRQHandler
B SM4_IRQHandler
PUBWEAK BN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
BN_IRQHandler
B BN_IRQHandler
END

579
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@ -0,0 +1,579 @@
;/**
; * @file startup_apm32f411xx.s
; *
; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f411xx
; *
; * @version V1.0.0
; *
; * @date 2023-12-01
; *
; * @attention
; *
; * Copyright (C) 2023 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EINT Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EINT line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EINT line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line0
DCD EINT1_IRQHandler ; EINT Line1
DCD EINT2_IRQHandler ; EINT Line2
DCD EINT3_IRQHandler ; EINT Line3
DCD EINT4_IRQHandler ; EINT Line4
DCD DMA1_STR0_IRQHandler ; DMA1 Stream 0
DCD DMA1_STR1_IRQHandler ; DMA1 Stream 1
DCD DMA1_STR2_IRQHandler ; DMA1 Stream 2
DCD DMA1_STR3_IRQHandler ; DMA1 Stream 3
DCD DMA1_STR4_IRQHandler ; DMA1 Stream 4
DCD DMA1_STR5_IRQHandler ; DMA1 Stream 5
DCD DMA1_STR6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; External Line[9:5]s
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
DCD TMR1_UP_TMR10_IRQHandler ; TMR1 Update and TMR10
DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EINT Line
DCD OTG_FS_WKUP_IRQHandler ; OTG_FS Wakeup through EINT line
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
DCD TMR8_UP_TMR13_IRQHandler ; TMR8 Update and TMR13
DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD DMA1_STR7_IRQHandler ; DMA1 Stream 7
DCD SMC_IRQHandler ; SMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; OTG_FS
DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD QSPI_IRQHandler ; QSPI
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDT_IRQHandler
B WWDT_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCM_IRQHandler
B RCM_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT4_IRQHandler
B EINT4_IRQHandler
PUBWEAK DMA1_STR0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR0_IRQHandler
B DMA1_STR0_IRQHandler
PUBWEAK DMA1_STR1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR1_IRQHandler
B DMA1_STR1_IRQHandler
PUBWEAK DMA1_STR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR2_IRQHandler
B DMA1_STR2_IRQHandler
PUBWEAK DMA1_STR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR3_IRQHandler
B DMA1_STR3_IRQHandler
PUBWEAK DMA1_STR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR4_IRQHandler
B DMA1_STR4_IRQHandler
PUBWEAK DMA1_STR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR5_IRQHandler
B DMA1_STR5_IRQHandler
PUBWEAK DMA1_STR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR6_IRQHandler
B DMA1_STR6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EINT9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT9_5_IRQHandler
B EINT9_5_IRQHandler
PUBWEAK TMR1_BRK_TMR9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_BRK_TMR9_IRQHandler
B TMR1_BRK_TMR9_IRQHandler
PUBWEAK TMR1_UP_TMR10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_UP_TMR10_IRQHandler
B TMR1_UP_TMR10_IRQHandler
PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_TRG_COM_TMR11_IRQHandler
B TMR1_TRG_COM_TMR11_IRQHandler
PUBWEAK TMR1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_CC_IRQHandler
B TMR1_CC_IRQHandler
PUBWEAK TMR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR2_IRQHandler
B TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR3_IRQHandler
B TMR3_IRQHandler
PUBWEAK TMR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR4_IRQHandler
B TMR4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EINT15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT15_10_IRQHandler
B EINT15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TMR8_BRK_TMR12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_BRK_TMR12_IRQHandler
B TMR8_BRK_TMR12_IRQHandler
PUBWEAK TMR8_UP_TMR13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_UP_TMR13_IRQHandler
B TMR8_UP_TMR13_IRQHandler
PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_TRG_COM_TMR14_IRQHandler
B TMR8_TRG_COM_TMR14_IRQHandler
PUBWEAK TMR8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_CC_IRQHandler
B TMR8_CC_IRQHandler
PUBWEAK DMA1_STR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR7_IRQHandler
B DMA1_STR7_IRQHandler
PUBWEAK SMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SMC_IRQHandler
B SMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TMR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR5_IRQHandler
B TMR5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK DMA2_STR0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR0_IRQHandler
B DMA2_STR0_IRQHandler
PUBWEAK DMA2_STR1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR1_IRQHandler
B DMA2_STR1_IRQHandler
PUBWEAK DMA2_STR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR2_IRQHandler
B DMA2_STR2_IRQHandler
PUBWEAK DMA2_STR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR3_IRQHandler
B DMA2_STR3_IRQHandler
PUBWEAK DMA2_STR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR4_IRQHandler
B DMA2_STR4_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_STR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR5_IRQHandler
B DMA2_STR5_IRQHandler
PUBWEAK DMA2_STR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR6_IRQHandler
B DMA2_STR6_IRQHandler
PUBWEAK DMA2_STR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR7_IRQHandler
B DMA2_STR7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK QSPI_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
QSPI_IRQHandler
B QSPI_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI5_IRQHandler
B SPI5_IRQHandler
END

628
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/iar/startup_apm32f417xx.s Normal file
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@ -0,0 +1,628 @@
;/**
; * @file startup_apm32f417xx.s
; *
; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f417xx
; *
; * @version V1.0.0
; *
; * @date 2023-07-31
; *
; * @attention
; *
; * Copyright (C) 2023 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EINT Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EINT line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EINT line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line0
DCD EINT1_IRQHandler ; EINT Line1
DCD EINT2_IRQHandler ; EINT Line2
DCD EINT3_IRQHandler ; EINT Line3
DCD EINT4_IRQHandler ; EINT Line4
DCD DMA1_STR0_IRQHandler ; DMA1 Stream 0
DCD DMA1_STR1_IRQHandler ; DMA1 Stream 1
DCD DMA1_STR2_IRQHandler ; DMA1 Stream 2
DCD DMA1_STR3_IRQHandler ; DMA1 Stream 3
DCD DMA1_STR4_IRQHandler ; DMA1 Stream 4
DCD DMA1_STR5_IRQHandler ; DMA1 Stream 5
DCD DMA1_STR6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; External Line[9:5]s
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
DCD TMR1_UP_TMR10_IRQHandler ; TMR1 Update and TMR10
DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EINT Line
DCD OTG_FS_WKUP_IRQHandler ; OTG_FS Wakeup through EINT line
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
DCD TMR8_UP_TMR13_IRQHandler ; TMR8 Update and TMR13
DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD DMA1_STR7_IRQHandler ; DMA1 Stream 7
DCD EMMC_IRQHandler ; EMMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_DAC_IRQHandler ; TMR6 and DAC1&2 underrun errors
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EINT line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; OTG_FS
DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS1_EP1_OUT_IRQHandler ; OTG_HS1 End Point 1 Out
DCD OTG_HS1_EP1_IN_IRQHandler ; OTG_HS1 End Point 1 In
DCD OTG_HS1_WKUP_IRQHandler ; OTG_HS1 Wakeup through EINT
DCD OTG_HS1_IRQHandler ; OTG_HS1
DCD DCI_IRQHandler ; DCI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD SM3_IRQHandler ; SM3
DCD SM4_IRQHandler ; SM4
DCD BN_IRQHandler ; BN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDT_IRQHandler
B WWDT_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCM_IRQHandler
B RCM_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT4_IRQHandler
B EINT4_IRQHandler
PUBWEAK DMA1_STR0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR0_IRQHandler
B DMA1_STR0_IRQHandler
PUBWEAK DMA1_STR1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR1_IRQHandler
B DMA1_STR1_IRQHandler
PUBWEAK DMA1_STR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR2_IRQHandler
B DMA1_STR2_IRQHandler
PUBWEAK DMA1_STR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR3_IRQHandler
B DMA1_STR3_IRQHandler
PUBWEAK DMA1_STR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR4_IRQHandler
B DMA1_STR4_IRQHandler
PUBWEAK DMA1_STR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR5_IRQHandler
B DMA1_STR5_IRQHandler
PUBWEAK DMA1_STR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR6_IRQHandler
B DMA1_STR6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EINT9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT9_5_IRQHandler
B EINT9_5_IRQHandler
PUBWEAK TMR1_BRK_TMR9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_BRK_TMR9_IRQHandler
B TMR1_BRK_TMR9_IRQHandler
PUBWEAK TMR1_UP_TMR10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_UP_TMR10_IRQHandler
B TMR1_UP_TMR10_IRQHandler
PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_TRG_COM_TMR11_IRQHandler
B TMR1_TRG_COM_TMR11_IRQHandler
PUBWEAK TMR1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_CC_IRQHandler
B TMR1_CC_IRQHandler
PUBWEAK TMR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR2_IRQHandler
B TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR3_IRQHandler
B TMR3_IRQHandler
PUBWEAK TMR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR4_IRQHandler
B TMR4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EINT15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT15_10_IRQHandler
B EINT15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TMR8_BRK_TMR12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_BRK_TMR12_IRQHandler
B TMR8_BRK_TMR12_IRQHandler
PUBWEAK TMR8_UP_TMR13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_UP_TMR13_IRQHandler
B TMR8_UP_TMR13_IRQHandler
PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_TRG_COM_TMR14_IRQHandler
B TMR8_TRG_COM_TMR14_IRQHandler
PUBWEAK TMR8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_CC_IRQHandler
B TMR8_CC_IRQHandler
PUBWEAK DMA1_STR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR7_IRQHandler
B DMA1_STR7_IRQHandler
PUBWEAK EMMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EMMC_IRQHandler
B EMMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TMR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR5_IRQHandler
B TMR5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TMR6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR6_DAC_IRQHandler
B TMR6_DAC_IRQHandler
PUBWEAK TMR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR7_IRQHandler
B TMR7_IRQHandler
PUBWEAK DMA2_STR0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR0_IRQHandler
B DMA2_STR0_IRQHandler
PUBWEAK DMA2_STR1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR1_IRQHandler
B DMA2_STR1_IRQHandler
PUBWEAK DMA2_STR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR2_IRQHandler
B DMA2_STR2_IRQHandler
PUBWEAK DMA2_STR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR3_IRQHandler
B DMA2_STR3_IRQHandler
PUBWEAK DMA2_STR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR4_IRQHandler
B DMA2_STR4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_STR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR5_IRQHandler
B DMA2_STR5_IRQHandler
PUBWEAK DMA2_STR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR6_IRQHandler
B DMA2_STR6_IRQHandler
PUBWEAK DMA2_STR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR7_IRQHandler
B DMA2_STR7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS1_EP1_OUT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_EP1_OUT_IRQHandler
B OTG_HS1_EP1_OUT_IRQHandler
PUBWEAK OTG_HS1_EP1_IN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_EP1_IN_IRQHandler
B OTG_HS1_EP1_IN_IRQHandler
PUBWEAK OTG_HS1_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_WKUP_IRQHandler
B OTG_HS1_WKUP_IRQHandler
PUBWEAK OTG_HS1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_IRQHandler
B OTG_HS1_IRQHandler
PUBWEAK DCI_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DCI_IRQHandler
B DCI_IRQHandler
PUBWEAK CRYP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CRYP_IRQHandler
B CRYP_IRQHandler
PUBWEAK HASH_RNG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HASH_RNG_IRQHandler
B HASH_RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK SM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SM3_IRQHandler
B SM3_IRQHandler
PUBWEAK SM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SM4_IRQHandler
B SM4_IRQHandler
PUBWEAK BN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
BN_IRQHandler
B BN_IRQHandler
END

608
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/iar/startup_apm32f465xx.s Normal file
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@ -0,0 +1,608 @@
;/**
; * @file startup_apm32f465xx.s
; *
; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f465xx
; *
; * @version V1.0.0
; *
; * @date 2023-12-01
; *
; * @attention
; *
; * Copyright (C) 2023 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EINT Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EINT line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EINT line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line0
DCD EINT1_IRQHandler ; EINT Line1
DCD EINT2_IRQHandler ; EINT Line2
DCD EINT3_IRQHandler ; EINT Line3
DCD EINT4_IRQHandler ; EINT Line4
DCD DMA1_STR0_IRQHandler ; DMA1 Stream 0
DCD DMA1_STR1_IRQHandler ; DMA1 Stream 1
DCD DMA1_STR2_IRQHandler ; DMA1 Stream 2
DCD DMA1_STR3_IRQHandler ; DMA1 Stream 3
DCD DMA1_STR4_IRQHandler ; DMA1 Stream 4
DCD DMA1_STR5_IRQHandler ; DMA1 Stream 5
DCD DMA1_STR6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; External Line[9:5]s
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
DCD TMR1_UP_TMR10_IRQHandler ; TMR1 Update and TMR10
DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EINT Line
DCD OTG_FS_WKUP_IRQHandler ; OTG_FS Wakeup through EINT line
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
DCD TMR8_UP_TMR13_IRQHandler ; TMR8 Update and TMR13
DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD DMA1_STR7_IRQHandler ; DMA1 Stream 7
DCD SMC_IRQHandler ; SMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_DAC_IRQHandler ; TMR6 and DAC1&2 underrun errors
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; OTG_FS
DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS1_EP1_OUT_IRQHandler ; OTG_HS1 End Point 1 Out
DCD OTG_HS1_EP1_IN_IRQHandler ; OTG_HS1 End Point 1 In
DCD OTG_HS1_WKUP_IRQHandler ; OTG_HS1 Wakeup through EINT
DCD OTG_HS1_IRQHandler ; OTG_HS1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG
DCD FPU_IRQHandler ; FPU
DCD SM3_IRQHandler ; SM3
DCD SM4_IRQHandler ; SM4
DCD BN_IRQHandler ; BN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDT_IRQHandler
B WWDT_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCM_IRQHandler
B RCM_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT4_IRQHandler
B EINT4_IRQHandler
PUBWEAK DMA1_STR0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR0_IRQHandler
B DMA1_STR0_IRQHandler
PUBWEAK DMA1_STR1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR1_IRQHandler
B DMA1_STR1_IRQHandler
PUBWEAK DMA1_STR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR2_IRQHandler
B DMA1_STR2_IRQHandler
PUBWEAK DMA1_STR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR3_IRQHandler
B DMA1_STR3_IRQHandler
PUBWEAK DMA1_STR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR4_IRQHandler
B DMA1_STR4_IRQHandler
PUBWEAK DMA1_STR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR5_IRQHandler
B DMA1_STR5_IRQHandler
PUBWEAK DMA1_STR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR6_IRQHandler
B DMA1_STR6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EINT9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT9_5_IRQHandler
B EINT9_5_IRQHandler
PUBWEAK TMR1_BRK_TMR9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_BRK_TMR9_IRQHandler
B TMR1_BRK_TMR9_IRQHandler
PUBWEAK TMR1_UP_TMR10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_UP_TMR10_IRQHandler
B TMR1_UP_TMR10_IRQHandler
PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_TRG_COM_TMR11_IRQHandler
B TMR1_TRG_COM_TMR11_IRQHandler
PUBWEAK TMR1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_CC_IRQHandler
B TMR1_CC_IRQHandler
PUBWEAK TMR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR2_IRQHandler
B TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR3_IRQHandler
B TMR3_IRQHandler
PUBWEAK TMR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR4_IRQHandler
B TMR4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EINT15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT15_10_IRQHandler
B EINT15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TMR8_BRK_TMR12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_BRK_TMR12_IRQHandler
B TMR8_BRK_TMR12_IRQHandler
PUBWEAK TMR8_UP_TMR13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_UP_TMR13_IRQHandler
B TMR8_UP_TMR13_IRQHandler
PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_TRG_COM_TMR14_IRQHandler
B TMR8_TRG_COM_TMR14_IRQHandler
PUBWEAK TMR8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_CC_IRQHandler
B TMR8_CC_IRQHandler
PUBWEAK DMA1_STR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_STR7_IRQHandler
B DMA1_STR7_IRQHandler
PUBWEAK SMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SMC_IRQHandler
B SMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TMR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR5_IRQHandler
B TMR5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TMR6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR6_DAC_IRQHandler
B TMR6_DAC_IRQHandler
PUBWEAK TMR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR7_IRQHandler
B TMR7_IRQHandler
PUBWEAK DMA2_STR0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR0_IRQHandler
B DMA2_STR0_IRQHandler
PUBWEAK DMA2_STR1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR1_IRQHandler
B DMA2_STR1_IRQHandler
PUBWEAK DMA2_STR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR2_IRQHandler
B DMA2_STR2_IRQHandler
PUBWEAK DMA2_STR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR3_IRQHandler
B DMA2_STR3_IRQHandler
PUBWEAK DMA2_STR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR4_IRQHandler
B DMA2_STR4_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_STR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR5_IRQHandler
B DMA2_STR5_IRQHandler
PUBWEAK DMA2_STR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR6_IRQHandler
B DMA2_STR6_IRQHandler
PUBWEAK DMA2_STR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_STR7_IRQHandler
B DMA2_STR7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS1_EP1_OUT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_EP1_OUT_IRQHandler
B OTG_HS1_EP1_OUT_IRQHandler
PUBWEAK OTG_HS1_EP1_IN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_EP1_IN_IRQHandler
B OTG_HS1_EP1_IN_IRQHandler
PUBWEAK OTG_HS1_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_WKUP_IRQHandler
B OTG_HS1_WKUP_IRQHandler
PUBWEAK OTG_HS1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS1_IRQHandler
B OTG_HS1_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK SM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SM3_IRQHandler
B SM3_IRQHandler
PUBWEAK SM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SM4_IRQHandler
B SM4_IRQHandler
PUBWEAK BN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
BN_IRQHandler
B BN_IRQHandler
END

229
lib/main/APM32F4/Libraries/Device/Geehy/APM32F4xx/Source/system_apm32f4xx.c Normal file
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@ -0,0 +1,229 @@
/**
*
* @file system_apm32f4xx.c
*
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* @version V1.0.0
*
* @date 2023-07-31
*
* @attention
*
* Copyright (C) 2023 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup apm32f4xx_system
* @{
*/
/** @addtogroup APM32F4xx_System_Private_Includes
* @{
*/
#include "apm32f4xx.h"
/* Value of the external oscillator in Hz */
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U)
#endif /* HSE_VALUE */
/* Value of the internal oscillator in Hz */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U)
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup APM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup APM32F4xx_System_Private_Defines
* @{
*/
/* Uncomment the following line if you need to relocate your vector table in internal SRAM */
/* #define VECT_TAB_SRAM */
/* Vector table base offset field. This value must be a multiple of 0x200 */
#define VECT_TAB_OFFSET 0x00
/**
* @}
*/
/** @addtogroup APM32F4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup APM32F4xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup APM32F4xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup APM32F4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
*
* @param None
*
* @retval None
*/
void SystemInit(void)
{
uint8_t i;
/* Disable global interrupt */
__disable_irq();
SysTick->CTRL = 0U;
SysTick->LOAD = 0U;
SysTick->VAL = 0U;
for (i = 0U; i < 8U; i++)
{
NVIC->ICER[i] = 0xFFFFFFFFU;
NVIC->ICPR[i] = 0xFFFFFFFFU;
}
/* FPU settings */
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
SCB->CPACR |= ((3UL << 10U * 2U)|(3UL << 11U * 2U)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCM clock configuration to the default reset state */
/* Set HSIEN bit */
RCM->CTRL |= (uint32_t)0x00000001;
/* Reset CFG register */
RCM->CFG = 0x00000000;
/* Reset HSEEN, CSSEN and PLL1EN bits */
RCM->CTRL &= (uint32_t)0xFEF6FFFF;
/* Reset PLL1CFG register */
RCM->PLL1CFG = 0x24003010;
/* Reset HSEBCFG bit */
RCM->CTRL &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCM->INT = 0x00000000;
/* Configure the Vector Table location add offset address */
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
/* Enable global interrupt */
__enable_irq();
}
/**
* @brief Update SystemCoreClock variable according to clock register values
* The SystemCoreClock variable contains the core clock (HCLK)
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t sysClock = 0, pllvco = 0, pllc, pllClock, pllb;
/* Get SYSCLK source */
sysClock = RCM->CFG & RCM_CFG_SCLKSWSTS;
switch (sysClock)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
pllClock = (RCM->PLL1CFG & RCM_PLL1CFG_PLL1CLKS) >> 22;
pllb = RCM->PLL1CFG & RCM_PLL1CFG_PLLB;
if (pllClock != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllb) * ((RCM->PLL1CFG & RCM_PLL1CFG_PLL1A) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllb) * ((RCM->PLL1CFG & RCM_PLL1CFG_PLL1A) >> 6);
}
pllc = (((RCM->PLL1CFG & RCM_PLL1CFG_PLL1C) >> 16) + 1 ) * 2;
SystemCoreClock = pllvco / pllc;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
sysClock = AHBPrescTable[((RCM->CFG & RCM_CFG_AHBPSC) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= sysClock;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/