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Code Issues Wiki Activity

Remove need for IRQ to be provided in target.c

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This commit is contained in:
blckmn 2016-11-07 09:54:55 +11:00
parent dc5b0a64bd
commit 159236093e
6 changed files with 80 additions and 48 deletions
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20
src/main/drivers/timer.c
View file

@ -207,6 +207,16 @@ rccPeriphTag_t timerRCC(TIM_TypeDef *tim)
return 0; return 0;
} }
uint8_t timerInputIrq(TIM_TypeDef *tim)
{
for (int i = 0; i < HARDWARE_TIMER_DEFINITION_COUNT; i++) {
if (timerDefinitions[i].TIMx == tim) {
return timerDefinitions[i].inputIrq;
}
}
return 0;
}
void timerNVICConfigure(uint8_t irq) void timerNVICConfigure(uint8_t irq)
{ {
NVIC_InitTypeDef NVIC_InitStructure; NVIC_InitTypeDef NVIC_InitStructure;
@ -239,9 +249,11 @@ void timerConfigure(const timerHardware_t *timerHardwarePtr, uint16_t period, ui
{ {
configTimeBase(timerHardwarePtr->tim, period, mhz); configTimeBase(timerHardwarePtr->tim, period, mhz);
TIM_Cmd(timerHardwarePtr->tim, ENABLE); TIM_Cmd(timerHardwarePtr->tim, ENABLE);
timerNVICConfigure(timerHardwarePtr->irq);
uint8_t irq = timerInputIrq(timerHardwarePtr->tim);
timerNVICConfigure(irq);
// HACK - enable second IRQ on timers that need it // HACK - enable second IRQ on timers that need it
switch(timerHardwarePtr->irq) { switch(irq) {
#if defined(STM32F10X) #if defined(STM32F10X)
case TIM1_CC_IRQn: case TIM1_CC_IRQn:
timerNVICConfigure(TIM1_UP_IRQn); timerNVICConfigure(TIM1_UP_IRQn);
@ -271,7 +283,7 @@ void timerConfigure(const timerHardware_t *timerHardwarePtr, uint16_t period, ui
} }
// allocate and configure timer channel. Timer priority is set to highest priority of its channels // allocate and configure timer channel. Timer priority is set to highest priority of its channels
void timerChInit(const timerHardware_t *timHw, channelType_t type, int irqPriority) void timerChInit(const timerHardware_t *timHw, channelType_t type, int irqPriority, uint8_t irq)
{ {
unsigned channel = timHw - timerHardware; unsigned channel = timHw - timerHardware;
if(channel >= USABLE_TIMER_CHANNEL_COUNT) if(channel >= USABLE_TIMER_CHANNEL_COUNT)
@ -288,7 +300,7 @@ void timerChInit(const timerHardware_t *timHw, channelType_t type, int irqPriori
NVIC_InitTypeDef NVIC_InitStructure; NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = timHw->irq; NVIC_InitStructure.NVIC_IRQChannel = irq;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(irqPriority); NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(irqPriority);
NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(irqPriority); NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(irqPriority);
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

6
src/main/drivers/timer.h
View file

@ -81,6 +81,7 @@ typedef struct timerOvrHandlerRec_s {
typedef struct timerDef_s { typedef struct timerDef_s {
TIM_TypeDef *TIMx; TIM_TypeDef *TIMx;
rccPeriphTag_t rcc; rccPeriphTag_t rcc;
uint8_t inputIrq;
} timerDef_t; } timerDef_t;
typedef struct timerHardware_s { typedef struct timerHardware_s {
@ -121,6 +122,8 @@ typedef enum {
#endif #endif
#elif defined(STM32F3) #elif defined(STM32F3)
#define HARDWARE_TIMER_DEFINITION_COUNT 10 #define HARDWARE_TIMER_DEFINITION_COUNT 10
#elif defined(STM32F411xE)
#define HARDWARE_TIMER_DEFINITION_COUNT 10
#elif defined(STM32F4) #elif defined(STM32F4)
#define HARDWARE_TIMER_DEFINITION_COUNT 14 #define HARDWARE_TIMER_DEFINITION_COUNT 14
#elif defined(STM32F7) #elif defined(STM32F7)
@ -167,7 +170,7 @@ void timerChITConfigDualLo(const timerHardware_t* timHw, FunctionalState newStat
void timerChITConfig(const timerHardware_t* timHw, FunctionalState newState); void timerChITConfig(const timerHardware_t* timHw, FunctionalState newState);
void timerChClearCCFlag(const timerHardware_t* timHw); void timerChClearCCFlag(const timerHardware_t* timHw);
void timerChInit(const timerHardware_t *timHw, channelType_t type, int irqPriority); void timerChInit(const timerHardware_t *timHw, channelType_t type, int irqPriority, uint8_t irq);
void timerInit(void); void timerInit(void);
void timerStart(void); void timerStart(void);
@ -178,6 +181,7 @@ uint8_t timerClockDivisor(TIM_TypeDef *tim);
void configTimeBase(TIM_TypeDef *tim, uint16_t period, uint8_t mhz); // TODO - just for migration void configTimeBase(TIM_TypeDef *tim, uint16_t period, uint8_t mhz); // TODO - just for migration
rccPeriphTag_t timerRCC(TIM_TypeDef *tim); rccPeriphTag_t timerRCC(TIM_TypeDef *tim);
uint8_t timerInputIrq(TIM_TypeDef *tim);
const timerHardware_t *timerGetByTag(ioTag_t tag, timerUsageFlag_e flag); const timerHardware_t *timerGetByTag(ioTag_t tag, timerUsageFlag_e flag);

22
src/main/drivers/timer_hal.c
View file

@ -216,6 +216,16 @@ rccPeriphTag_t timerRCC(TIM_TypeDef *tim)
return 0; return 0;
} }
uint8_t timerInputIrq(TIM_TypeDef *tim)
{
for (int i = 0; i < HARDWARE_TIMER_DEFINITION_COUNT; i++) {
if (timerDefinitions[i].TIMx == tim) {
return timerDefinitions[i].inputIrq;
}
}
return 0;
}
void timerNVICConfigure(uint8_t irq) void timerNVICConfigure(uint8_t irq)
{ {
HAL_NVIC_SetPriority(irq, NVIC_PRIORITY_BASE(NVIC_PRIO_TIMER), NVIC_PRIORITY_SUB(NVIC_PRIO_TIMER)); HAL_NVIC_SetPriority(irq, NVIC_PRIORITY_BASE(NVIC_PRIO_TIMER), NVIC_PRIORITY_SUB(NVIC_PRIO_TIMER));
@ -285,9 +295,11 @@ void timerConfigure(const timerHardware_t *timerHardwarePtr, uint16_t period, ui
configTimeBase(timerHardwarePtr->tim, period, mhz); configTimeBase(timerHardwarePtr->tim, period, mhz);
HAL_TIM_Base_Start(&timerHandle[timerIndex].Handle); HAL_TIM_Base_Start(&timerHandle[timerIndex].Handle);
timerNVICConfigure(timerHardwarePtr->irq);
uint8_t irq = timerInputIrq(timerHardwarePtr->tim);
timerNVICConfigure(irq);
// HACK - enable second IRQ on timers that need it // HACK - enable second IRQ on timers that need it
switch(timerHardwarePtr->irq) { switch(irq) {
case TIM1_CC_IRQn: case TIM1_CC_IRQn:
timerNVICConfigure(TIM1_UP_TIM10_IRQn); timerNVICConfigure(TIM1_UP_TIM10_IRQn);
@ -300,7 +312,7 @@ void timerConfigure(const timerHardware_t *timerHardwarePtr, uint16_t period, ui
} }
// allocate and configure timer channel. Timer priority is set to highest priority of its channels // allocate and configure timer channel. Timer priority is set to highest priority of its channels
void timerChInit(const timerHardware_t *timHw, channelType_t type, int irqPriority) void timerChInit(const timerHardware_t *timHw, channelType_t type, int irqPriority, uint8_t irq)
{ {
uint8_t timerIndex = lookupTimerIndex(timHw->tim); uint8_t timerIndex = lookupTimerIndex(timHw->tim);
if (timerIndex >= USED_TIMER_COUNT) { if (timerIndex >= USED_TIMER_COUNT) {
@ -320,8 +332,8 @@ void timerChInit(const timerHardware_t *timHw, channelType_t type, int irqPriori
HAL_TIM_Base_Start(&timerHandle[timerIndex].Handle); HAL_TIM_Base_Start(&timerHandle[timerIndex].Handle);
HAL_NVIC_SetPriority(timHw->irq, NVIC_PRIORITY_BASE(irqPriority), NVIC_PRIORITY_SUB(irqPriority)); HAL_NVIC_SetPriority(irq, NVIC_PRIORITY_BASE(irqPriority), NVIC_PRIORITY_SUB(irqPriority));
HAL_NVIC_EnableIRQ(timHw->irq); HAL_NVIC_EnableIRQ(irq);
timerInfo[timer].priority = irqPriority; timerInfo[timer].priority = irqPriority;
} }

20
src/main/drivers/timer_stm32f30x.c
View file

@ -17,16 +17,16 @@
#include "timer.h" #include "timer.h"
const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = { const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
{ .TIMx = TIM1, .rcc = RCC_APB2(TIM1) }, { .TIMx = TIM1, .rcc = RCC_APB2(TIM1), .inputIrq = TIM1_CC_IRQn },
{ .TIMx = TIM2, .rcc = RCC_APB1(TIM2) }, { .TIMx = TIM2, .rcc = RCC_APB1(TIM2), .inputIrq = TIM2_IRQn },
{ .TIMx = TIM3, .rcc = RCC_APB1(TIM3) }, { .TIMx = TIM3, .rcc = RCC_APB1(TIM3), .inputIrq = TIM3_IRQn },
{ .TIMx = TIM4, .rcc = RCC_APB1(TIM4) }, { .TIMx = TIM4, .rcc = RCC_APB1(TIM4), .inputIrq = TIM4_IRQn },
{ .TIMx = TIM6, .rcc = RCC_APB1(TIM6) }, { .TIMx = TIM6, .rcc = RCC_APB1(TIM6), .inputIrq = 0 },
{ .TIMx = TIM7, .rcc = RCC_APB1(TIM7) }, { .TIMx = TIM7, .rcc = RCC_APB1(TIM7), .inputIrq = 0 },
{ .TIMx = TIM8, .rcc = RCC_APB2(TIM8) }, { .TIMx = TIM8, .rcc = RCC_APB2(TIM8), .inputIrq = TIM8_CC_IRQn },
{ .TIMx = TIM15, .rcc = RCC_APB2(TIM15) }, { .TIMx = TIM15, .rcc = RCC_APB2(TIM15), .inputIrq = TIM1_BRK_TIM15_IRQn },
{ .TIMx = TIM16, .rcc = RCC_APB2(TIM16) }, { .TIMx = TIM16, .rcc = RCC_APB2(TIM16), .inputIrq = TIM1_UP_TIM16_IRQn },
{ .TIMx = TIM17, .rcc = RCC_APB2(TIM17) }, { .TIMx = TIM17, .rcc = RCC_APB2(TIM17), .inputIrq = TIM1_TRG_COM_TIM17_IRQn },
}; };
uint8_t timerClockDivisor(TIM_TypeDef *tim) uint8_t timerClockDivisor(TIM_TypeDef *tim)

32
src/main/drivers/timer_stm32f4xx.c
View file

@ -42,20 +42,24 @@
#define CCMR_Offset ((uint16_t)0x0018) #define CCMR_Offset ((uint16_t)0x0018)
const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = { const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
{ .TIMx = TIM1, .rcc = RCC_APB2(TIM1) }, { .TIMx = TIM1, .rcc = RCC_APB2(TIM1), .inputIrq = TIM1_CC_IRQn},
{ .TIMx = TIM2, .rcc = RCC_APB1(TIM2) }, { .TIMx = TIM2, .rcc = RCC_APB1(TIM2), .inputIrq = TIM2_IRQn},
{ .TIMx = TIM3, .rcc = RCC_APB1(TIM3) }, { .TIMx = TIM3, .rcc = RCC_APB1(TIM3), .inputIrq = TIM3_IRQn},
{ .TIMx = TIM4, .rcc = RCC_APB1(TIM4) }, { .TIMx = TIM4, .rcc = RCC_APB1(TIM4), .inputIrq = TIM4_IRQn},
{ .TIMx = TIM5, .rcc = RCC_APB1(TIM5) }, { .TIMx = TIM5, .rcc = RCC_APB1(TIM5), .inputIrq = TIM5_IRQn},
{ .TIMx = TIM6, .rcc = RCC_APB1(TIM6) }, { .TIMx = TIM6, .rcc = RCC_APB1(TIM6), .inputIrq = 0},
{ .TIMx = TIM7, .rcc = RCC_APB1(TIM7) }, { .TIMx = TIM7, .rcc = RCC_APB1(TIM7), .inputIrq = 0},
{ .TIMx = TIM8, .rcc = RCC_APB2(TIM8) }, #ifndef STM32F411xE
{ .TIMx = TIM9, .rcc = RCC_APB2(TIM9) }, { .TIMx = TIM8, .rcc = RCC_APB2(TIM8), .inputIrq = TIM8_CC_IRQn},
{ .TIMx = TIM10, .rcc = RCC_APB2(TIM10) }, #endif
{ .TIMx = TIM11, .rcc = RCC_APB2(TIM11) }, { .TIMx = TIM9, .rcc = RCC_APB2(TIM9), .inputIrq = TIM1_BRK_TIM9_IRQn},
{ .TIMx = TIM12, .rcc = RCC_APB1(TIM12) }, { .TIMx = TIM10, .rcc = RCC_APB2(TIM10), .inputIrq = TIM1_UP_TIM10_IRQn},
{ .TIMx = TIM13, .rcc = RCC_APB1(TIM13) }, { .TIMx = TIM11, .rcc = RCC_APB2(TIM11), .inputIrq = TIM1_TRG_COM_TIM11_IRQn},
{ .TIMx = TIM14, .rcc = RCC_APB1(TIM14) }, #ifndef STM32F411xE
{ .TIMx = TIM12, .rcc = RCC_APB1(TIM12), .inputIrq = TIM8_BRK_TIM12_IRQn},
{ .TIMx = TIM13, .rcc = RCC_APB1(TIM13), .inputIrq = TIM8_UP_TIM13_IRQn},
{ .TIMx = TIM14, .rcc = RCC_APB1(TIM14), .inputIrq = TIM8_TRG_COM_TIM14_IRQn},
#endif
}; };
/* /*

28
src/main/drivers/timer_stm32f7xx.c
View file

@ -42,20 +42,20 @@
#define CCMR_Offset ((uint16_t)0x0018) #define CCMR_Offset ((uint16_t)0x0018)
const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = { const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
{ .TIMx = TIM1, .rcc = RCC_APB2(TIM1) }, { .TIMx = TIM1, .rcc = RCC_APB2(TIM1), .inputIrq = TIM1_CC_IRQn},
{ .TIMx = TIM2, .rcc = RCC_APB1(TIM2) }, { .TIMx = TIM2, .rcc = RCC_APB1(TIM2), .inputIrq = TIM2_IRQn},
{ .TIMx = TIM3, .rcc = RCC_APB1(TIM3) }, { .TIMx = TIM3, .rcc = RCC_APB1(TIM3), .inputIrq = TIM3_IRQn},
{ .TIMx = TIM4, .rcc = RCC_APB1(TIM4) }, { .TIMx = TIM4, .rcc = RCC_APB1(TIM4), .inputIrq = TIM4_IRQn},
{ .TIMx = TIM5, .rcc = RCC_APB1(TIM5) }, { .TIMx = TIM5, .rcc = RCC_APB1(TIM5), .inputIrq = TIM5_IRQn},
{ .TIMx = TIM6, .rcc = RCC_APB1(TIM6) }, { .TIMx = TIM6, .rcc = RCC_APB1(TIM6), .inputIrq = 0},
{ .TIMx = TIM7, .rcc = RCC_APB1(TIM7) }, { .TIMx = TIM7, .rcc = RCC_APB1(TIM7), .inputIrq = 0},
{ .TIMx = TIM8, .rcc = RCC_APB2(TIM8) }, { .TIMx = TIM8, .rcc = RCC_APB2(TIM8), .inputIrq = TIM8_CC_IRQn},
{ .TIMx = TIM9, .rcc = RCC_APB2(TIM9) }, { .TIMx = TIM9, .rcc = RCC_APB2(TIM9), .inputIrq = TIM1_BRK_TIM9_IRQn},
{ .TIMx = TIM10, .rcc = RCC_APB2(TIM10) }, { .TIMx = TIM10, .rcc = RCC_APB2(TIM10), .inputIrq = TIM1_UP_TIM10_IRQn},
{ .TIMx = TIM11, .rcc = RCC_APB2(TIM11) }, { .TIMx = TIM11, .rcc = RCC_APB2(TIM11), .inputIrq = TIM1_TRG_COM_TIM11_IRQn},
{ .TIMx = TIM12, .rcc = RCC_APB1(TIM12) }, { .TIMx = TIM12, .rcc = RCC_APB1(TIM12), .inputIrq = TIM8_BRK_TIM12_IRQn},
{ .TIMx = TIM13, .rcc = RCC_APB1(TIM13) }, { .TIMx = TIM13, .rcc = RCC_APB1(TIM13), .inputIrq = TIM8_UP_TIM13_IRQn},
{ .TIMx = TIM14, .rcc = RCC_APB1(TIM14) }, { .TIMx = TIM14, .rcc = RCC_APB1(TIM14), .inputIrq = TIM8_TRG_COM_TIM14_IRQn},
}; };
/* /*