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Move some clock initialisation code into the drivers.

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This commit is contained in:
Dominic Clifton 2014-06-04 11:14:13 +01:00
parent b07a284f4e
commit 16528cf0d9
6 changed files with 29 additions and 18 deletions
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23
src/main/drivers/system.c
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@ -81,21 +81,13 @@ void systemInit(bool overclock)
// Turn on clocks for stuff we use
#ifdef STM32F10X_MD
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4 | RCC_APB1Periph_I2C2, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_TIM1 | RCC_APB2Periph_ADC1 | RCC_APB2Periph_USART1, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_TIM1, ENABLE);
#endif
#ifdef STM32F303xC
RCC_ADCCLKConfig(RCC_ADC12PLLCLK_Div256); // 72 MHz divided by 256 = 281.25 kHz
RCC_APB1PeriphClockCmd(
RCC_APB1Periph_TIM2 |
RCC_APB1Periph_TIM3 |
RCC_APB1Periph_TIM4 |
RCC_APB1Periph_I2C2 |
RCC_APB1Periph_USART2,
ENABLE
);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4, ENABLE);
RCC_APB2PeriphClockCmd(
RCC_APB2Periph_TIM1 |
RCC_APB2Periph_TIM8 |
@ -103,21 +95,18 @@ void systemInit(bool overclock)
RCC_APB2Periph_TIM15 |
#endif
RCC_APB2Periph_TIM16 |
RCC_APB2Periph_TIM17 |
RCC_APB2Periph_USART1,
RCC_APB2Periph_TIM17,
ENABLE
);
RCC_AHBPeriphClockCmd(
RCC_AHBPeriph_DMA1 |
RCC_AHBPeriph_GPIOA |
RCC_AHBPeriph_GPIOB |
RCC_AHBPeriph_GPIOC |
RCC_AHBPeriph_GPIOD |
RCC_AHBPeriph_GPIOE |
#ifdef CHEBUZZF3
RCC_AHBPeriph_GPIOF |
#endif
RCC_AHBPeriph_ADC12,
RCC_AHBPeriph_GPIOE,
ENABLE
);
#endif