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Move some clock initialisation code into the drivers.

This commit is contained in:
Dominic Clifton 2014-06-04 11:14:13 +01:00
parent b07a284f4e
commit 16528cf0d9
6 changed files with 29 additions and 18 deletions

View file

@ -68,8 +68,11 @@ void adcInit(drv_adc_config_t *init)
adcConfig[ADC_CURRENT].sampleTime = ADC_SampleTime_239Cycles5; adcConfig[ADC_CURRENT].sampleTime = ADC_SampleTime_239Cycles5;
} }
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
// FIXME ADC driver assumes all the GPIO was already placed in 'AIN' mode
// ADC driver assumes all the GPIO was already placed in 'AIN' mode
DMA_DeInit(DMA1_Channel1); DMA_DeInit(DMA1_Channel1);
dma.DMA_PeripheralBaseAddr = (uint32_t)&ADC1->DR; dma.DMA_PeripheralBaseAddr = (uint32_t)&ADC1->DR;
dma.DMA_MemoryBaseAddr = (uint32_t)adcValues; dma.DMA_MemoryBaseAddr = (uint32_t)adcValues;

View file

@ -52,6 +52,11 @@ void adcInit(drv_adc_config_t *init)
adcConfig[ADC_EXTERNAL1].enabled = true; adcConfig[ADC_EXTERNAL1].enabled = true;
adcChannelCount++; adcChannelCount++;
RCC_ADCCLKConfig(RCC_ADC12PLLCLK_Div256); // 72 MHz divided by 256 = 281.25 kHz
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_ADC12, ENABLE);
// FIXME ADC driver assumes all the GPIO was already placed in 'AIN' mode
DMA_DeInit(DMA1_Channel1); DMA_DeInit(DMA1_Channel1);
DMA_StructInit(&DMA_InitStructure); DMA_StructInit(&DMA_InitStructure);

View file

@ -266,6 +266,8 @@ void i2cInit(I2C_TypeDef *I2C)
I2C_InitTypeDef i2c; I2C_InitTypeDef i2c;
gpio_config_t gpio; gpio_config_t gpio;
RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2 | RCC_APB2Periph_GPIOB, ENABLE);
// Init pins // Init pins
gpio.pin = Pin_10 | Pin_11; gpio.pin = Pin_10 | Pin_11;
gpio.speed = Speed_2MHz; gpio.speed = Speed_2MHz;

View file

@ -50,6 +50,8 @@ uartPort_t *serialUSART1(uint32_t baudRate, portMode_t mode)
s->txDMAChannel = DMA1_Channel4; s->txDMAChannel = DMA1_Channel4;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
// USART1_TX PA9 // USART1_TX PA9
// USART1_RX PA10 // USART1_RX PA10
gpio.speed = Speed_2MHz; gpio.speed = Speed_2MHz;
@ -97,6 +99,8 @@ uartPort_t *serialUSART2(uint32_t baudRate, portMode_t mode)
s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR; s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
// USART2_TX PA2 // USART2_TX PA2
// USART2_RX PA3 // USART2_RX PA3
gpio.speed = Speed_2MHz; gpio.speed = Speed_2MHz;

View file

@ -73,6 +73,9 @@ uartPort_t *serialUSART1(uint32_t baudRate, portMode_t mode)
s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->RDR; s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->RDR;
s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->TDR; s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->TDR;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
@ -137,6 +140,11 @@ uartPort_t *serialUSART2(uint32_t baudRate, portMode_t mode)
s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->TDR; s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->TDR;
#endif #endif
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
#if defined(USE_USART2_TX_DMA) || defined(USE_USART2_RX_DMA)
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
#endif
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

View file

@ -81,21 +81,13 @@ void systemInit(bool overclock)
// Turn on clocks for stuff we use // Turn on clocks for stuff we use
#ifdef STM32F10X_MD #ifdef STM32F10X_MD
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4 | RCC_APB1Periph_I2C2, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_TIM1 | RCC_APB2Periph_ADC1 | RCC_APB2Periph_USART1, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_TIM1, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
#endif #endif
#ifdef STM32F303xC #ifdef STM32F303xC
RCC_ADCCLKConfig(RCC_ADC12PLLCLK_Div256); // 72 MHz divided by 256 = 281.25 kHz
RCC_APB1PeriphClockCmd( RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4, ENABLE);
RCC_APB1Periph_TIM2 |
RCC_APB1Periph_TIM3 |
RCC_APB1Periph_TIM4 |
RCC_APB1Periph_I2C2 |
RCC_APB1Periph_USART2,
ENABLE
);
RCC_APB2PeriphClockCmd( RCC_APB2PeriphClockCmd(
RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM1 |
RCC_APB2Periph_TIM8 | RCC_APB2Periph_TIM8 |
@ -103,21 +95,18 @@ void systemInit(bool overclock)
RCC_APB2Periph_TIM15 | RCC_APB2Periph_TIM15 |
#endif #endif
RCC_APB2Periph_TIM16 | RCC_APB2Periph_TIM16 |
RCC_APB2Periph_TIM17 | RCC_APB2Periph_TIM17,
RCC_APB2Periph_USART1,
ENABLE ENABLE
); );
RCC_AHBPeriphClockCmd( RCC_AHBPeriphClockCmd(
RCC_AHBPeriph_DMA1 |
RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOA |
RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOB |
RCC_AHBPeriph_GPIOC | RCC_AHBPeriph_GPIOC |
RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOD |
RCC_AHBPeriph_GPIOE |
#ifdef CHEBUZZF3 #ifdef CHEBUZZF3
RCC_AHBPeriph_GPIOF | RCC_AHBPeriph_GPIOF |
#endif #endif
RCC_AHBPeriph_ADC12, RCC_AHBPeriph_GPIOE,
ENABLE ENABLE
); );
#endif #endif