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Simplified target timer definitions

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blckmn 2016-11-08 15:47:25 +11:00
parent 657eee6617
commit 1dbd7ee732
3 changed files with 372 additions and 0 deletions
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357
src/main/drivers/tim_def.h Normal file
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@ -0,0 +1,357 @@
/*
* This file is part of Cleanflight.
*
* Cleanflight is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* Cleanflight is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <platform.h>
#include "common/utils.h"
#if defined(STM32F3)
#define DEF_TIM(tim, chan, pin, flags, out) {\
tim,\
IO_TAG(pin),\
EXPAND(DEF_CHAN_ ## chan),\
flags,\
(DEF_CHAN_ ## chan ## _OUTPUT | out),\
EXPAND(GPIO_AF__ ## pin ## _ ## tim ## _ ## chan),\
CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _TYPE),\
CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _HANDLER)\
}
#define DEF_TIM_CHAN(chan) DEF_CHAN_ ## chan
#define DEF_TIM_OUTPUT(chan, out) ( DEF_CHAN_ ## chan ## _OUTPUT | out )
#define DEF_DMA_TYPE(tim, chan) CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _TYPE)
#define DEF_DMA_HANDLER(tim, chan) CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _HANDLER)
/* add the DMA mappings here */
#define DEF_TIM_DMACHAN_TIM1_CH1 DMA1_CH2
#define DEF_TIM_DMACHAN_TIM1_CH2 DMA1_CH3
#define DEF_TIM_DMACHAN_TIM1_CH4 DMA1_CH4
#define DEF_TIM_DMACHAN_TIM1_TRIG DMA1_CH4
#define DEF_TIM_DMACHAN_TIM1_COM DMA1_CH4
#define DEF_TIM_DMACHAN_TIM1_UP DMA1_CH5
#define DEF_TIM_DMACHAN_TIM1_CH3 DMA1_CH6
#define DEF_TIM_DMACHAN_TIM2_CH3 DMA1_CH1
#define DEF_TIM_DMACHAN_TIM2_UP DMA1_CH2
#define DEF_TIM_DMACHAN_TIM2_CH1 DMA1_CH5
#define DEF_TIM_DMACHAN_TIM2_CH2 DMA1_CH7
#define DEF_TIM_DMACHAN_TIM2_CH4 DMA1_CH7
#define DEF_TIM_DMACHAN_TIM3_CH2 DMA_NONE
#define DEF_TIM_DMACHAN_TIM3_CH3 DMA1_CH2
#define DEF_TIM_DMACHAN_TIM3_CH4 DMA1_CH3
#define DEF_TIM_DMACHAN_TIM3_UP DMA1_CH3
#define DEF_TIM_DMACHAN_TIM3_CH1 DMA1_CH6
#define DEF_TIM_DMACHAN_TIM3_TRIG DMA1_CH6
#define DEF_TIM_DMACHAN_TIM4_CH1 DMA1_CH1
#define DEF_TIM_DMACHAN_TIM4_CH2 DMA1_CH4
#define DEF_TIM_DMACHAN_TIM4_CH3 DMA1_CH5
#define DEF_TIM_DMACHAN_TIM4_UP DMA1_CH7
#define DEF_TIM_DMACHAN_TIM4_CH4 DMA_NONE
#define DEF_TIM_DMACHAN_TIM15_CH1 DMA1_CH5
#define DEF_TIM_DMACHAN_TIM15_CH2 DMA_NONE
#define DEF_TIM_DMACHAN_TIM15_UP DMA1_CH5
#define DEF_TIM_DMACHAN_TIM15_TRIG DMA1_CH5
#define DEF_TIM_DMACHAN_TIM15_COM DMA1_CH5
#ifdef DMA_TIMER16_REMAP
#define DEF_TIM_DMACHAN_TIM16_CH1 DMA1_CH6
#define DEF_TIM_DMACHAN_TIM16_UP DMA1_CH6
#else
#define DEF_TIM_DMACHAN_TIM16_CH1 DMA1_CH3
#define DEF_TIM_DMACHAN_TIM16_UP DMA1_CH3
#endif
#ifdef DMA_TIMER17_REMAP
#define DEF_TIM_DMACHAN_TIM17_CH1 DMA1_CH7
#define DEF_TIM_DMACHAN_TIM17_UP DMA1_CH7
#else
#define DEF_TIM_DMACHAN_TIM17_CH1 DMA1_CH1
#define DEF_TIM_DMACHAN_TIM17_UP DMA1_CH1
#endif
#define DEF_TIM_DMACHAN_TIM8_CH3 DMA2_CH1
#define DEF_TIM_DMACHAN_TIM8_UP DMA2_CH1
#define DEF_TIM_DMACHAN_TIM8_CH4 DMA2_CH2
#define DEF_TIM_DMACHAN_TIM8_TRIG DMA2_CH2
#define DEF_TIM_DMACHAN_TIM8_COM DMA2_CH2
#define DEF_TIM_DMACHAN_TIM8_CH1 DMA2_CH3
#define DEF_TIM_DMACHAN_TIM8_CH2 DMA2_CH5
#define DMA1_CH1_TYPE DMA1_Channel1
#define DMA1_CH2_TYPE DMA1_Channel2
#define DMA1_CH3_TYPE DMA1_Channel3
#define DMA1_CH4_TYPE DMA1_Channel4
#define DMA1_CH5_TYPE DMA1_Channel5
#define DMA1_CH6_TYPE DMA1_Channel6
#define DMA1_CH7_TYPE DMA1_Channel7
#define DMA2_CH1_TYPE DMA2_Channel1
#define DMA2_CH2_TYPE DMA2_Channel2
#define DMA2_CH3_TYPE DMA2_Channel3
#define DMA2_CH4_TYPE DMA2_Channel4
#define DMA2_CH5_TYPE DMA2_Channel5
#define DMA2_CH6_TYPE DMA2_Channel6
#define DMA2_CH7_TYPE DMA2_Channel7
#define GPIO_AF(p, t) CONCAT(GPIO_AF__, p, _, t)
#define GPIO_AF__PA0_TIM2_CH1 GPIO_AF_1
#define GPIO_AF__PA1_TIM2_CH2 GPIO_AF_1
#define GPIO_AF__PA2_TIM2_CH3 GPIO_AF_1
#define GPIO_AF__PA3_TIM2_CH3 GPIO_AF_1
#define GPIO_AF__PA5_TIM2_CH1 GPIO_AF_1
#define GPIO_AF__PA6_TIM16_CH1 GPIO_AF_1
#define GPIO_AF__PA7_TIM17_CH1 GPIO_AF_1
#define GPIO_AF__PA12_TIM16_CH1 GPIO_AF_1
#define GPIO_AF__PA13_TIM16_CH1N GPIO_AF_1
#define GPIO_AF__PA15_TIM2_CH1 GPIO_AF_1
#define GPIO_AF__PA4_TIM3_CH2 GPIO_AF_2
#define GPIO_AF__PA6_TIM3_CH1 GPIO_AF_2
#define GPIO_AF__PA7_TIM3_CH2 GPIO_AF_2
#define GPIO_AF__PA15_TIM8_CH1 GPIO_AF_2
#define GPIO_AF__PA7_TIM8_CH1N GPIO_AF_4
#define GPIO_AF__PA14_TIM4_CH2 GPIO_AF_5
#define GPIO_AF__PA7_TIM1_CH1N GPIO_AF_6
#define GPIO_AF__PA8_TIM1_CH1 GPIO_AF_6
#define GPIO_AF__PA9_TIM1_CH2 GPIO_AF_6
#define GPIO_AF__PA10_TIM1_CH3 GPIO_AF_6
#define GPIO_AF__PA11_TIM1_CH1N GPIO_AF_6
#define GPIO_AF__PA12_TIM1_CH2N GPIO_AF_6
#define GPIO_AF__PA1_TIM15_CH1N GPIO_AF_9
#define GPIO_AF__PA2_TIM15_CH1 GPIO_AF_9
#define GPIO_AF__PA3_TIM15_CH2 GPIO_AF_9
#define GPIO_AF__PA9_TIM2_CH3 GPIO_AF_10
#define GPIO_AF__PA10_TIM2_CH4 GPIO_AF_10
#define GPIO_AF__PA11_TIM4_CH1 GPIO_AF_10
#define GPIO_AF__PA12_TIM4_CH2 GPIO_AF_10
#define GPIO_AF__PA13_TIM4_CH3 GPIO_AF_10
#define GPIO_AF__PA11_TIM1_CH4 GPIO_AF_11
#define GPIO_AF__PB3_TIM2_CH2 GPIO_AF_1
#define GPIO_AF__PB4_TIM16_CH1 GPIO_AF_1
#define GPIO_AF__PB6_TIM16_CH1N GPIO_AF_1
#define GPIO_AF__PB7_TIM17_CH1N GPIO_AF_1
#define GPIO_AF__PB8_TIM16_CH1 GPIO_AF_1
#define GPIO_AF__PB9_TIM17_CH1 GPIO_AF_1
#define GPIO_AF__PB10_TIM2_CH3 GPIO_AF_1
#define GPIO_AF__PB11_TIM2_CH4 GPIO_AF_1
#define GPIO_AF__PB14_TIM15_CH1 GPIO_AF_1
#define GPIO_AF__PB15_TIM15_CH2 GPIO_AF_1
#define GPIO_AF__PB0_TIM3_CH3 GPIO_AF_2
#define GPIO_AF__PB1_TIM3_CH4 GPIO_AF_2
#define GPIO_AF__PB4_TIM3_CH1 GPIO_AF_2
#define GPIO_AF__PB5_TIM3_CH2 GPIO_AF_2
#define GPIO_AF__PB6_TIM4_CH1 GPIO_AF_2
#define GPIO_AF__PB7_TIM4_CH2 GPIO_AF_2
#define GPIO_AF__PB8_TIM4_CH3 GPIO_AF_2
#define GPIO_AF__PB9_TIM4_CH4 GPIO_AF_2
#define GPIO_AF__PB15_TIM15_CH1N GPIO_AF_2
#define GPIO_AF__PB0_TIM8_CH2N GPIO_AF_4
#define GPIO_AF__PB1_TIM8_CH3N GPIO_AF_4
#define GPIO_AF__PB3_TIM8_CH1N GPIO_AF_4
#define GPIO_AF__PB4_TIM8_CH2N GPIO_AF_4
#define GPIO_AF__PB15_TIM1_CH3N GPIO_AF_4
#define GPIO_AF__PB6_TIM8_CH1 GPIO_AF_5
#define GPIO_AF__PB0_TIM1_CH2N GPIO_AF_6
#define GPIO_AF__PB1_TIM1_CH3N GPIO_AF_6
#define GPIO_AF__PB13_TIM1_CH1N GPIO_AF_6
#define GPIO_AF__PB14_TIM1_CH2N GPIO_AF_6
#define GPIO_AF__PB5_TIM17_CH1 GPIO_AF_10
#define GPIO_AF__PB7_TIM3_CH4 GPIO_AF_10
#define GPIO_AF__PB8_TIM8_CH2 GPIO_AF_10
#define GPIO_AF__PB9_TIM8_CH3 GPIO_AF_10
#define GPIO_AF__PC6_TIM3_CH1 GPIO_AF_2
#define GPIO_AF__PC7_TIM3_CH2 GPIO_AF_2
#define GPIO_AF__PC8_TIM3_CH3 GPIO_AF_2
#define GPIO_AF__PC9_TIM3_CH4 GPIO_AF_2
#define GPIO_AF__PC6_TIM8_CH1 GPIO_AF_4
#define GPIO_AF__PC7_TIM8_CH2 GPIO_AF_4
#define GPIO_AF__PC8_TIM8_CH3 GPIO_AF_4
#define GPIO_AF__PC9_TIM8_CH4 GPIO_AF_4
#define GPIO_AF__PC10_TIM8_CH1N GPIO_AF_4
#define GPIO_AF__PC11_TIM8_CH2N GPIO_AF_4
#define GPIO_AF__PC12_TIM8_CH3N GPIO_AF_4
#define GPIO_AF__PC13_TIM8_CH1N GPIO_AF_4
#define GPIO_AF__PD3_TIM2_CH1 GPIO_AF_2
#define GPIO_AF__PD4_TIM2_CH2 GPIO_AF_2
#define GPIO_AF__PD6_TIM2_CH4 GPIO_AF_2
#define GPIO_AF__PD7_TIM2_CH3 GPIO_AF_2
#define GPIO_AF__PD12_TIM4_CH1 GPIO_AF_2
#define GPIO_AF__PD13_TIM4_CH2 GPIO_AF_2
#define GPIO_AF__PD14_TIM4_CH3 GPIO_AF_2
#define GPIO_AF__PD15_TIM4_CH4 GPIO_AF_2
#define GPIO_AF__PD1_TIM8_CH4 GPIO_AF_4
#elif defined(STM32F4)
#define DEF_TIM(tim, chan, pin, flags, out, dmaopt) {\
tim,\
IO_TAG(pin),\
EXPAND(DEF_CHAN_ ## chan),\
flags,\
(DEF_CHAN_ ## chan ## _OUTPUT | out),\
EXPAND(GPIO_AF_## tim),\
CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## _ ## tim ## _ ## chan), _TYPE),\
EXPAND(DEF_TIM_DMA_CHN_ ## dmaopt ## _ ## tim ## _ ## chan),\
CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## _ ## tim ## _ ## chan), _HANDLER)\
}
/* F4 Stream Mappings */
#define DEF_TIM_DMA_STR_0_TIM1_CH1 DMA2_ST6
#define DEF_TIM_DMA_STR_1_TIM1_CH1 DMA2_ST1
#define DEF_TIM_DMA_STR_2_TIM1_CH1 DMA2_ST3
#define DEF_TIM_DMA_STR_0_TIM1_CH2 DMA2_ST6
#define DEF_TIM_DMA_STR_1_TIM1_CH2 DMA2_ST2
#define DEF_TIM_DMA_STR_0_TIM1_CH3 DMA2_ST6
#define DEF_TIM_DMA_STR_1_TIM1_CH3 DMA2_ST6
#define DEF_TIM_DMA_STR_0_TIM1_CH4 DMA2_ST4
#define DEF_TIM_DMA_STR_0_TIM2_CH1 DMA1_ST5
#define DEF_TIM_DMA_STR_0_TIM2_CH2 DMA1_ST6
#define DEF_TIM_DMA_STR_0_TIM2_CH3 DMA1_ST1
#define DEF_TIM_DMA_STR_0_TIM2_CH4 DMA1_ST7
#define DEF_TIM_DMA_STR_1_TIM2_CH4 DMA1_ST6
#define DEF_TIM_DMA_STR_0_TIM3_CH1 DMA1_ST4
#define DEF_TIM_DMA_STR_0_TIM3_CH2 DMA1_ST5
#define DEF_TIM_DMA_STR_0_TIM3_CH3 DMA1_ST7
#define DEF_TIM_DMA_STR_0_TIM3_CH4 DMA1_ST2
#define DEF_TIM_DMA_STR_0_TIM4_CH1 DMA1_ST0
#define DEF_TIM_DMA_STR_0_TIM4_CH2 DMA1_ST4
#define DEF_TIM_DMA_STR_0_TIM4_CH3 DMA1_ST7
#define DEF_TIM_DMA_STR_0_TIM4_CH4 DMA1_ST3
#define DEF_TIM_DMA_STR_0_TIM5_CH1 DMA1_ST2
#define DEF_TIM_DMA_STR_0_TIM5_CH2 DMA1_ST4
#define DEF_TIM_DMA_STR_0_TIM5_CH3 DMA1_ST0
#define DEF_TIM_DMA_STR_0_TIM5_CH4 DMA1_ST1
#define DEF_TIM_DMA_STR_1_TIM5_CH4 DMA1_ST3
#define DEF_TIM_DMA_STR_0_TIM8_CH1 DMA2_ST2
#define DEF_TIM_DMA_STR_1_TIM8_CH1 DMA2_ST2
#define DEF_TIM_DMA_STR_0_TIM8_CH2 DMA2_ST3
#define DEF_TIM_DMA_STR_1_TIM8_CH2 DMA2_ST2
#define DEF_TIM_DMA_STR_0_TIM8_CH3 DMA2_ST2
#define DEF_TIM_DMA_STR_0_TIM8_CH4 DMA2_ST7
/* F4 Channel Mappings */
#define DEF_TIM_DMA_CHN_0_TIM1_CH1 DMA_Channel_0
#define DEF_TIM_DMA_CHN_1_TIM1_CH1 DMA_Channel_6
#define DEF_TIM_DMA_CHN_2_TIM1_CH1 DMA_Channel_6
#define DEF_TIM_DMA_CHN_0_TIM1_CH2 DMA_Channel_0
#define DEF_TIM_DMA_CHN_1_TIM1_CH2 DMA_Channel_6
#define DEF_TIM_DMA_CHN_0_TIM1_CH3 DMA_Channel_0
#define DEF_TIM_DMA_CHN_1_TIM1_CH3 DMA_Channel_6
#define DEF_TIM_DMA_CHN_0_TIM1_CH4 DMA_Channel_6
#define DEF_TIM_DMA_CHN_0_TIM2_CH1 DMA_Channel_3
#define DEF_TIM_DMA_CHN_0_TIM2_CH2 DMA_Channel_3
#define DEF_TIM_DMA_CHN_0_TIM2_CH3 DMA_Channel_3
#define DEF_TIM_DMA_CHN_0_TIM2_CH4 DMA_Channel_3
#define DEF_TIM_DMA_CHN_1_TIM2_CH4 DMA_Channel_3
#define DEF_TIM_DMA_CHN_0_TIM3_CH1 DMA_Channel_5
#define DEF_TIM_DMA_CHN_0_TIM3_CH2 DMA_Channel_5
#define DEF_TIM_DMA_CHN_0_TIM3_CH3 DMA_Channel_5
#define DEF_TIM_DMA_CHN_0_TIM3_CH4 DMA_Channel_5
#define DEF_TIM_DMA_CHN_0_TIM4_CH1 DMA_Channel_2
#define DEF_TIM_DMA_CHN_0_TIM4_CH2 DMA_Channel_2
#define DEF_TIM_DMA_CHN_0_TIM4_CH3 DMA_Channel_2
#define DEF_TIM_DMA_CHN_0_TIM4_CH4 DMA_Channel_2
#define DEF_TIM_DMA_CHN_0_TIM5_CH1 DMA_Channel_3
#define DEF_TIM_DMA_CHN_0_TIM5_CH2 DMA_Channel_3
#define DEF_TIM_DMA_CHN_0_TIM5_CH3 DMA_Channel_3
#define DEF_TIM_DMA_CHN_0_TIM5_CH4 DMA_Channel_3
#define DEF_TIM_DMA_CHN_1_TIM5_CH4 DMA_Channel_3
#define DEF_TIM_DMA_CHN_0_TIM8_CH1 DMA_Channel_0
#define DEF_TIM_DMA_CHN_1_TIM8_CH1 DMA_Channel_7
#define DEF_TIM_DMA_CHN_0_TIM8_CH2 DMA_Channel_0
#define DEF_TIM_DMA_CHN_1_TIM8_CH2 DMA_Channel_7
#define DEF_TIM_DMA_CHN_0_TIM8_CH3 DMA_Channel_0
#define DEF_TIM_DMA_CHN_0_TIM8_CH4 DMA_Channel_7
#define DMA1_ST0_TYPE DMA1_Stream0
#define DMA1_ST1_TYPE DMA1_Stream1
#define DMA1_ST2_TYPE DMA1_Stream2
#define DMA1_ST3_TYPE DMA1_Stream3
#define DMA1_ST4_TYPE DMA1_Stream4
#define DMA1_ST5_TYPE DMA1_Stream5
#define DMA1_ST6_TYPE DMA1_Stream6
#define DMA1_ST7_TYPE DMA1_Stream7
#define DMA2_ST0_TYPE DMA2_Stream0
#define DMA2_ST1_TYPE DMA2_Stream1
#define DMA2_ST2_TYPE DMA2_Stream2
#define DMA2_ST3_TYPE DMA2_Stream3
#define DMA2_ST4_TYPE DMA2_Stream4
#define DMA2_ST5_TYPE DMA2_Stream5
#define DMA2_ST6_TYPE DMA2_Stream6
#define DMA2_ST7_TYPE DMA2_Stream7
#endif
/**** Common Defines across all targets ****/
#define NONE 0
#define DMA_NONE_TYPE NULL
#define DMA_NONE_HANDLER 0
#define DEF_CHAN_CH1 TIM_Channel_1
#define DEF_CHAN_CH2 TIM_Channel_2
#define DEF_CHAN_CH3 TIM_Channel_3
#define DEF_CHAN_CH4 TIM_Channel_4
#define DEF_CHAN_CH1N TIM_Channel_1
#define DEF_CHAN_CH2N TIM_Channel_2
#define DEF_CHAN_CH3N TIM_Channel_3
#define DEF_CHAN_CH4N TIM_Channel_4
#define DEF_CHAN_CH1_OUTPUT TIMER_OUTPUT_NONE
#define DEF_CHAN_CH2_OUTPUT TIMER_OUTPUT_NONE
#define DEF_CHAN_CH3_OUTPUT TIMER_OUTPUT_NONE
#define DEF_CHAN_CH4_OUTPUT TIMER_OUTPUT_NONE
#define DEF_CHAN_CH1N_OUTPUT TIMER_OUTPUT_N_CHANNEL
#define DEF_CHAN_CH2N_OUTPUT TIMER_OUTPUT_N_CHANNEL
#define DEF_CHAN_CH3N_OUTPUT TIMER_OUTPUT_N_CHANNEL
#define DEF_CHAN_CH4N_OUTPUT TIMER_OUTPUT_N_CHANNEL

1
src/main/drivers/timer.h
View file

@ -105,6 +105,7 @@ typedef struct timerHardware_s {
} timerHardware_t;
typedef enum {
TIMER_OUTPUT_NONE = 0x00,
TIMER_INPUT_ENABLED = 0x00,
TIMER_OUTPUT_ENABLED = 0x01,
TIMER_OUTPUT_INVERTED = 0x02,

14
src/main/target/BLUEJAYF4/target.c
View file

@ -22,6 +22,9 @@
#include "drivers/timer.h"
#include "drivers/dma.h"
#include "drivers/tim_def.h"
/*
const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
{ TIM8, IO_TAG(PC7), TIM_Channel_2, TIM_USE_PPM, 0, GPIO_AF_TIM8, NULL, 0, 0 }, // PPM IN
{ TIM5, IO_TAG(PA0), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_TIM5, DMA1_Stream2, DMA_Channel_6, DMA1_ST2_HANDLER }, // S1_OUT
@ -31,4 +34,15 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
{ TIM3, IO_TAG(PB1), TIM_Channel_4, TIM_USE_MOTOR | TIM_USE_LED, 1, GPIO_AF_TIM3, DMA1_Stream2, DMA_Channel_5, DMA1_ST2_HANDLER }, // S5_OUT
{ TIM3, IO_TAG(PB0), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_TIM3, DMA1_Stream7, DMA_Channel_5, DMA1_ST7_HANDLER }, // S6_OUT
};
*/
const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
DEF_TIM(TIM8, CH2, PC7, TIM_USE_PPM, 0, 0 ), // PPM IN
DEF_TIM(TIM5, CH1, PA0, TIM_USE_MOTOR, 0, 0 ), // S1_OUT
DEF_TIM(TIM5, CH2, PA1, TIM_USE_MOTOR, 0, 0 ), // S2_OUT
DEF_TIM(TIM2, CH3, PA2, TIM_USE_MOTOR, 0, 0 ), // S3_OUT
DEF_TIM(TIM2, CH4, PA3, TIM_USE_MOTOR, 0, 0 ), // S4_OUT
DEF_TIM(TIM3, CH4, PB1, TIM_USE_MOTOR | TIM_USE_LED, 0, 0 ), // S5_OUT
DEF_TIM(TIM3, CH3, PB0, TIM_USE_MOTOR, 0, 0 ), // S6_OUT
};