mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-15 20:35:33 +03:00
[H7] H723/H725 support
This commit is contained in:
jflyper
parent
4bf3e99e9c
commit
1feb306674
17 changed files with 1260 additions and 19 deletions
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@ -203,6 +203,20 @@ MCU_FLASH_SIZE := FIRMWARE_SIZE
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DEFAULT_LD_SCRIPT = $(LINKER_DIR)/stm32_flash_h7a3_ram_based.ld
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DEFAULT_LD_SCRIPT = $(LINKER_DIR)/stm32_flash_h7a3_ram_based.ld
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endif
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endif
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else ifeq ($(TARGET),$(filter $(TARGET),$(H723xG_TARGETS)))
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DEVICE_FLAGS += -DSTM32H723xx
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DEFAULT_LD_SCRIPT = $(LINKER_DIR)/stm32_flash_h723_1m.ld
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STARTUP_SRC = startup_stm32h723xx.s
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MCU_FLASH_SIZE := 1024
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DEVICE_FLAGS += -DMAX_MPU_REGIONS=16
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else ifeq ($(TARGET),$(filter $(TARGET),$(H725xG_TARGETS)))
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DEVICE_FLAGS += -DSTM32H725xx
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DEFAULT_LD_SCRIPT = $(LINKER_DIR)/stm32_flash_h723_1m.ld
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STARTUP_SRC = startup_stm32h723xx.s
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MCU_FLASH_SIZE := 1024
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DEVICE_FLAGS += -DMAX_MPU_REGIONS=16
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else ifeq ($(TARGET),$(filter $(TARGET),$(H750xB_TARGETS)))
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else ifeq ($(TARGET),$(filter $(TARGET),$(H750xB_TARGETS)))
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DEVICE_FLAGS += -DSTM32H750xx
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DEVICE_FLAGS += -DSTM32H750xx
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DEFAULT_LD_SCRIPT = $(LINKER_DIR)/stm32_flash_h750_128k.ld
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DEFAULT_LD_SCRIPT = $(LINKER_DIR)/stm32_flash_h750_128k.ld
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@ -19,7 +19,7 @@ endif
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F4_TARGETS := $(F405_TARGETS) $(F411_TARGETS) $(F446_TARGETS)
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F4_TARGETS := $(F405_TARGETS) $(F411_TARGETS) $(F446_TARGETS)
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F7_TARGETS := $(F7X2RE_TARGETS) $(F7X5XE_TARGETS) $(F7X5XG_TARGETS) $(F7X5XI_TARGETS) $(F7X6XG_TARGETS)
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F7_TARGETS := $(F7X2RE_TARGETS) $(F7X5XE_TARGETS) $(F7X5XG_TARGETS) $(F7X5XI_TARGETS) $(F7X6XG_TARGETS)
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G4_TARGETS := $(G4X3_TARGETS)
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G4_TARGETS := $(G4X3_TARGETS)
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H7_TARGETS := $(H743xI_TARGETS) $(H750xB_TARGETS) $(H7A3xI_TARGETS) $(H7A3xIQ_TARGETS)
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H7_TARGETS := $(H743xI_TARGETS) $(H750xB_TARGETS) $(H7A3xI_TARGETS) $(H7A3xIQ_TARGETS) $(H723xG_TARGETS) $(H725xG_TARGETS)
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ifeq ($(filter $(TARGET),$(VALID_TARGETS)),)
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ifeq ($(filter $(TARGET),$(VALID_TARGETS)),)
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$(error Target '$(TARGET)' is not valid, must be one of $(VALID_TARGETS). Have you prepared a valid target.mk?)
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$(error Target '$(TARGET)' is not valid, must be one of $(VALID_TARGETS). Have you prepared a valid target.mk?)
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304
src/link/stm32_flash_h723_1m.ld
Normal file
304
src/link/stm32_flash_h723_1m.ld
Normal file
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@ -0,0 +1,304 @@
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/*
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*****************************************************************************
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**
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** File : stm32_flash_h723_1m.ld
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**
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** Abstract : Linker script for STM32H723xG and STM32H725xG Device with
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** 320K AXI-SRAM mapped onto AXI bus on D1 domain
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(Shared AXI/I-TCM 192KB is all configured as AXI-SRAM)
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** 16K SRAM1 mapped on D2 domain
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** 16K SRAM2 mapped on D2 domain
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** 16K SRAM mapped on D3 domain
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** 64K ITCM
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** 128K DTCM
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**
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*****************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/*
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0x00000000 to 0x0000FFFF 64K ITCM
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0x20000000 to 0x2001FFFF 128K DTCM
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0x24000000 to 0x2404FFFF 320K AXI SRAM, D1 domain, main RAM
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0x30000000 to 0x30003FFF 16K SRAM1, D2 domain
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0x30004000 to 0x30007FFF 16K SRAM2, D2 domain
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0x38000000 to 0x38003FFF 16K SRAM4, D3 domain, unused
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0x38800000 to 0x38800FFF 4K BACKUP SRAM, Backup domain, unused
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XXX TODO join isr vector, startup and firmware to save some space
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0x08000000 to 0x080FFFFF 1024K full flash,
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0x08000000 to 0x0801FFFF 128K isr vector, startup code
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0x08020000 to 0x080DFFFF 768K firmware
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0x080E0000 to 0x080FFFFF 128K config
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*/
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/* Specify the memory areas */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
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FLASH_CONFIG (r) : ORIGIN = 0x080E0000, LENGTH = 128K
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FLASH1 (rx) : ORIGIN = 0x08020000, LENGTH = 768K
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ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
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DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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RAM (rwx) : ORIGIN = 0x24000000, LENGTH = 320K
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D2_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 32K /* SRAM1 + SRAM2 */
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MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
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}
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REGION_ALIAS("STACKRAM", DTCM_RAM)
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REGION_ALIAS("FASTRAM", DTCM_RAM)
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/* INCLUDE "stm32_flash_f7_split.ld" */
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/*
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*****************************************************************************
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**
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** File : stm32_flash_f7_split.ld
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**
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** Abstract : Common linker script for STM32 devices.
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**
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*****************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = ORIGIN(STACKRAM) + LENGTH(STACKRAM) - 8; /* Reserve 2 x 4bytes for info across reset */
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/* Base address where the config is stored. */
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__config_start = ORIGIN(FLASH_CONFIG);
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__config_end = ORIGIN(FLASH_CONFIG) + LENGTH(FLASH_CONFIG);
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/* Generate a link error if heap and stack don't fit into RAM */
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_Min_Heap_Size = 0; /* required amount of heap */
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_Min_Stack_Size = 0x800; /* required amount of stack */
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/* Define output sections */
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SECTIONS
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{
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/* The startup code goes first into FLASH */
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.isr_vector :
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{
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. = ALIGN(512);
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PROVIDE (isr_vector_table_base = .);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} >FLASH
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/* The program code and other data goes into FLASH */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >FLASH1
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/* Critical program code goes into ITCM RAM */
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/* Copy specific fast-executing code to ITCM RAM */
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tcm_code = LOADADDR(.tcm_code);
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.tcm_code :
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{
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. = ALIGN(4);
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tcm_code_start = .;
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*(.tcm_code)
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*(.tcm_code*)
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. = ALIGN(4);
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tcm_code_end = .;
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} >ITCM_RAM AT >FLASH1
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} >FLASH
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.ARM :
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{
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__exidx_start = .;
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*(.ARM.exidx*) __exidx_end = .;
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} >FLASH
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.pg_registry :
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{
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PROVIDE_HIDDEN (__pg_registry_start = .);
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KEEP (*(.pg_registry))
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KEEP (*(SORT(.pg_registry.*)))
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PROVIDE_HIDDEN (__pg_registry_end = .);
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} >FLASH
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.pg_resetdata :
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{
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PROVIDE_HIDDEN (__pg_resetdata_start = .);
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KEEP (*(.pg_resetdata))
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PROVIDE_HIDDEN (__pg_resetdata_end = .);
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} >FLASH
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/* used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* Initialized data sections goes into RAM, load LMA copy after code */
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.data :
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{
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. = ALIGN(4);
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_sdata = .; /* create a global symbol at data start */
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*(.data) /* .data sections */
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*(.data*) /* .data* sections */
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. = ALIGN(4);
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_edata = .; /* define a global symbol at data end */
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} >RAM AT >FLASH
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/* Uninitialized data section */
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. = ALIGN(4);
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.bss (NOLOAD) :
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{
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/* This is used by the startup in order to initialize the .bss secion */
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_sbss = .; /* define a global symbol at bss start */
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__bss_start__ = _sbss;
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*(.bss)
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*(SORT_BY_ALIGNMENT(.bss*))
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*(COMMON)
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. = ALIGN(4);
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_ebss = .; /* define a global symbol at bss end */
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__bss_end__ = _ebss;
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} >RAM
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/* Uninitialized data section */
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. = ALIGN(4);
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.sram2 (NOLOAD) :
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{
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/* This is used by the startup in order to initialize the .sram2 secion */
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_ssram2 = .; /* define a global symbol at sram2 start */
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__sram2_start__ = _ssram2;
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*(.sram2)
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*(SORT_BY_ALIGNMENT(.sram2*))
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. = ALIGN(4);
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_esram2 = .; /* define a global symbol at sram2 end */
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__sram2_end__ = _esram2;
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} >RAM
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/* used during startup to initialized fastram_data */
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_sfastram_idata = LOADADDR(.fastram_data);
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/* Initialized FAST_DATA section for unsuspecting developers */
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.fastram_data :
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{
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. = ALIGN(4);
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_sfastram_data = .; /* create a global symbol at data start */
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*(.fastram_data) /* .data sections */
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*(.fastram_data*) /* .data* sections */
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. = ALIGN(4);
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_efastram_data = .; /* define a global symbol at data end */
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} >FASTRAM AT >FLASH
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. = ALIGN(4);
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.fastram_bss (NOLOAD) :
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{
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_sfastram_bss = .;
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__fastram_bss_start__ = _sfastram_bss;
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*(.fastram_bss)
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*(SORT_BY_ALIGNMENT(.fastram_bss*))
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. = ALIGN(4);
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_efastram_bss = .;
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__fastram_bss_end__ = _efastram_bss;
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} >FASTRAM
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.DMA_RAM (NOLOAD) :
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{
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. = ALIGN(32);
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PROVIDE(dmaram_start = .);
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_sdmaram = .;
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_dmaram_start__ = _sdmaram;
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KEEP(*(.DMA_RAM))
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PROVIDE(dmaram_end = .);
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_edmaram = .;
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_dmaram_end__ = _edmaram;
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} >D2_RAM
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.DMA_RW_D2 (NOLOAD) :
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{
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. = ALIGN(32);
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PROVIDE(dmarw_start = .);
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_sdmarw = .;
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_dmarw_start__ = _sdmarw;
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KEEP(*(.DMA_RW))
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PROVIDE(dmarw_end = .);
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_edmarw = .;
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_dmarw_end__ = _edmarw;
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} >D2_RAM
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.DMA_RW_AXI (NOLOAD) :
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{
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. = ALIGN(32);
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PROVIDE(dmarwaxi_start = .);
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_sdmarwaxi = .;
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_dmarwaxi_start__ = _sdmarwaxi;
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KEEP(*(.DMA_RW_AXI))
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PROVIDE(dmarwaxi_end = .);
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_edmarwaxi = .;
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_dmarwaxi_end__ = _edmarwaxi;
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} >RAM
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.persistent_data (NOLOAD) :
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{
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__persistent_data_start__ = .;
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*(.persistent_data)
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. = ALIGN(4);
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__persistent_data_end__ = .;
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} >RAM
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/* User_heap_stack section, used to check that there is enough RAM left */
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_heap_stack_end = ORIGIN(STACKRAM)+LENGTH(STACKRAM) - 8; /* 8 bytes to allow for alignment */
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_heap_stack_begin = _heap_stack_end - _Min_Stack_Size - _Min_Heap_Size;
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. = _heap_stack_begin;
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._user_heap_stack :
|
||||||
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{
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. = ALIGN(4);
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PROVIDE ( end = . );
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PROVIDE ( _end = . );
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. = . + _Min_Heap_Size;
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. = . + _Min_Stack_Size;
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. = ALIGN(4);
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} >STACKRAM = 0xa5
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/* MEMORY_bank1 section, code must be located here explicitly */
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/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
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.memory_b1_text :
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{
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*(.mb1text) /* .mb1text sections (code) */
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*(.mb1text*) /* .mb1text* sections (code) */
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*(.mb1rodata) /* read-only data (constants) */
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*(.mb1rodata*)
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} >MEMORY_B1
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/* Remove information from the standard libraries */
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/DISCARD/ :
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{
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|
libc.a ( * )
|
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libm.a ( * )
|
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|
libgcc.a ( * )
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}
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.ARM.attributes 0 : { *(.ARM.attributes) }
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}
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@ -74,6 +74,8 @@ mcuTypeId_e getMcuTypeId(void)
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}
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}
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#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
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#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
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return MCU_TYPE_H7A3;
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return MCU_TYPE_H7A3;
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#elif defined(STM32H723xx) || defined(STM32H725xx)
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return MCU_TYPE_H723_725;
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#else
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#else
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return MCU_TYPE_UNKNOWN;
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return MCU_TYPE_UNKNOWN;
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#endif
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#endif
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||||||
|
|
@ -58,6 +58,7 @@ typedef enum {
|
||||||
MCU_TYPE_H743_REV_X,
|
MCU_TYPE_H743_REV_X,
|
||||||
MCU_TYPE_H743_REV_V,
|
MCU_TYPE_H743_REV_V,
|
||||||
MCU_TYPE_H7A3,
|
MCU_TYPE_H7A3,
|
||||||
|
MCU_TYPE_H723_725,
|
||||||
MCU_TYPE_UNKNOWN = 255,
|
MCU_TYPE_UNKNOWN = 255,
|
||||||
} mcuTypeId_e;
|
} mcuTypeId_e;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -306,6 +306,7 @@ static const char *mcuTypeNames[] = {
|
||||||
"H743 (Rev.X)",
|
"H743 (Rev.X)",
|
||||||
"H743 (Rev.V)",
|
"H743 (Rev.V)",
|
||||||
"H7A3",
|
"H7A3",
|
||||||
|
"H723/H725",
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *configurationStates[] = { "UNCONFIGURED", "CUSTOM DEFAULTS", "CONFIGURED" };
|
static const char *configurationStates[] = { "UNCONFIGURED", "CUSTOM DEFAULTS", "CONFIGURED" };
|
||||||
|
|
|
||||||
|
|
@ -70,7 +70,7 @@ uint8_t eepromData[EEPROM_SIZE];
|
||||||
# elif defined(UNIT_TEST)
|
# elif defined(UNIT_TEST)
|
||||||
# define FLASH_PAGE_SIZE (0x400)
|
# define FLASH_PAGE_SIZE (0x400)
|
||||||
// H7
|
// H7
|
||||||
# elif defined(STM32H743xx) || defined(STM32H750xx)
|
# elif defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
# define FLASH_PAGE_SIZE ((uint32_t)0x20000) // 128K sectors
|
# define FLASH_PAGE_SIZE ((uint32_t)0x20000) // 128K sectors
|
||||||
# elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
# elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
||||||
# define FLASH_PAGE_SIZE ((uint32_t)0x2000) // 8K sectors
|
# define FLASH_PAGE_SIZE ((uint32_t)0x2000) // 8K sectors
|
||||||
|
|
@ -274,7 +274,7 @@ static uint32_t getFLASHSectorForEEPROM(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#elif defined(STM32H743xx) || defined(STM32G4) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
#elif defined(STM32H743xx) || defined(STM32G4) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
/*
|
/*
|
||||||
MCUs with uniform array of equal size sectors, handled in two banks having contiguous address.
|
MCUs with uniform array of equal size sectors, handled in two banks having contiguous address.
|
||||||
(Devices with non-contiguous flash layout is not currently useful anyways.)
|
(Devices with non-contiguous flash layout is not currently useful anyways.)
|
||||||
|
|
@ -284,6 +284,10 @@ H743
|
||||||
Bank 1 0x08000000 - 0x080FFFFF 128KB * 8
|
Bank 1 0x08000000 - 0x080FFFFF 128KB * 8
|
||||||
Bank 2 0x08100000 - 0x081FFFFF 128KB * 8
|
Bank 2 0x08100000 - 0x081FFFFF 128KB * 8
|
||||||
|
|
||||||
|
H743
|
||||||
|
1 bank * 8 sector/bank * 128K/sector (1MB)
|
||||||
|
Bank 1 0x08000000 - 0x080FFFFF 128KB * 8
|
||||||
|
|
||||||
H7A3
|
H7A3
|
||||||
2 bank * 128 sector/bank * 8KB/sector (2MB)
|
2 bank * 128 sector/bank * 8KB/sector (2MB)
|
||||||
Bank 1 0x08000000 - 0x080FFFFF 8KB * 128
|
Bank 1 0x08000000 - 0x080FFFFF 8KB * 128
|
||||||
|
|
@ -299,7 +303,7 @@ bank operation mode. The code assumes dual bank operation, in which case the
|
||||||
FLASH_BANK_SIZE constant is set to one half of the available flash size in HAL.
|
FLASH_BANK_SIZE constant is set to one half of the available flash size in HAL.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(STM32H743xx)
|
#if defined(STM32H743xx) || defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
#define FLASH_PAGE_PER_BANK 8
|
#define FLASH_PAGE_PER_BANK 8
|
||||||
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
||||||
#define FLASH_PAGE_PER_BANK 128
|
#define FLASH_PAGE_PER_BANK 128
|
||||||
|
|
@ -312,12 +316,19 @@ FLASH_BANK_SIZE constant is set to one half of the available flash size in HAL.
|
||||||
|
|
||||||
static void getFLASHSectorForEEPROM(uint32_t address, uint32_t *bank, uint32_t *sector)
|
static void getFLASHSectorForEEPROM(uint32_t address, uint32_t *bank, uint32_t *sector)
|
||||||
{
|
{
|
||||||
|
#if defined(FLASH_BANK2_BASE)
|
||||||
if (address >= FLASH_BANK1_BASE && address < FLASH_BANK2_BASE) {
|
if (address >= FLASH_BANK1_BASE && address < FLASH_BANK2_BASE) {
|
||||||
*bank = FLASH_BANK_1;
|
*bank = FLASH_BANK_1;
|
||||||
} else if (address >= FLASH_BANK2_BASE && address < FLASH_BANK2_BASE + FLASH_BANK_SIZE) {
|
} else if (address >= FLASH_BANK2_BASE && address < FLASH_BANK2_BASE + FLASH_BANK_SIZE) {
|
||||||
*bank = FLASH_BANK_2;
|
*bank = FLASH_BANK_2;
|
||||||
address -= FLASH_BANK_SIZE;
|
address -= FLASH_BANK_SIZE;
|
||||||
} else {
|
}
|
||||||
|
#else
|
||||||
|
if (address >= FLASH_BANK1_BASE && address < FLASH_BANK1_BASE + FLASH_BANK_SIZE) {
|
||||||
|
*bank = FLASH_BANK_1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
else {
|
||||||
// Not good
|
// Not good
|
||||||
while (1) {
|
while (1) {
|
||||||
failureMode(FAILURE_CONFIG_STORE_FAILURE);
|
failureMode(FAILURE_CONFIG_STORE_FAILURE);
|
||||||
|
|
|
||||||
|
|
@ -29,7 +29,7 @@
|
||||||
#ifdef CONFIG_IN_EXTERNAL_FLASH
|
#ifdef CONFIG_IN_EXTERNAL_FLASH
|
||||||
#define CONFIG_STREAMER_BUFFER_SIZE 8 // Must not be greater than the smallest flash page size of all compiled-in flash devices.
|
#define CONFIG_STREAMER_BUFFER_SIZE 8 // Must not be greater than the smallest flash page size of all compiled-in flash devices.
|
||||||
typedef uint32_t config_streamer_buffer_align_type_t;
|
typedef uint32_t config_streamer_buffer_align_type_t;
|
||||||
#elif defined(STM32H743xx) || defined(STM32H750xx)
|
#elif defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
#define CONFIG_STREAMER_BUFFER_SIZE 32 // Flash word = 256-bits
|
#define CONFIG_STREAMER_BUFFER_SIZE 32 // Flash word = 256-bits
|
||||||
typedef uint64_t config_streamer_buffer_align_type_t;
|
typedef uint64_t config_streamer_buffer_align_type_t;
|
||||||
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
||||||
|
|
|
||||||
|
|
@ -95,7 +95,7 @@ const adcDevice_t adcHardware[ADCDEV_COUNT] = {
|
||||||
|
|
||||||
adcDevice_t adcDevice[ADCDEV_COUNT];
|
adcDevice_t adcDevice[ADCDEV_COUNT];
|
||||||
|
|
||||||
#if defined(STM32H743xx) || defined(STM32H750xx)
|
#if defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
#define ADC_DEVICE_FOR_INTERNAL ADC_DEVICES_3
|
#define ADC_DEVICE_FOR_INTERNAL ADC_DEVICES_3
|
||||||
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
||||||
#define ADC_DEVICE_FOR_INTERNAL ADC_DEVICES_2
|
#define ADC_DEVICE_FOR_INTERNAL ADC_DEVICES_2
|
||||||
|
|
@ -110,8 +110,14 @@ const adcTagMap_t adcTagMap[] = {
|
||||||
// Keep these at the beginning for easy indexing by ADC_TAG_MAP_{VREFINT,TEMPSENSOR}
|
// Keep these at the beginning for easy indexing by ADC_TAG_MAP_{VREFINT,TEMPSENSOR}
|
||||||
#define ADC_TAG_MAP_VREFINT 0
|
#define ADC_TAG_MAP_VREFINT 0
|
||||||
#define ADC_TAG_MAP_TEMPSENSOR 1
|
#define ADC_TAG_MAP_TEMPSENSOR 1
|
||||||
|
|
||||||
|
#if defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
||||||
|
{ DEFIO_TAG_E__NONE, ADC_DEVICE_FOR_INTERNAL, ADC_CHANNEL_VREFINT, 18 },
|
||||||
|
{ DEFIO_TAG_E__NONE, ADC_DEVICE_FOR_INTERNAL, ADC_CHANNEL_TEMPSENSOR, 17 },
|
||||||
|
#elif defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
{ DEFIO_TAG_E__NONE, ADC_DEVICE_FOR_INTERNAL, ADC_CHANNEL_VREFINT, 18 },
|
{ DEFIO_TAG_E__NONE, ADC_DEVICE_FOR_INTERNAL, ADC_CHANNEL_VREFINT, 18 },
|
||||||
{ DEFIO_TAG_E__NONE, ADC_DEVICE_FOR_INTERNAL, ADC_CHANNEL_TEMPSENSOR, 19 },
|
{ DEFIO_TAG_E__NONE, ADC_DEVICE_FOR_INTERNAL, ADC_CHANNEL_TEMPSENSOR, 19 },
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
// Inputs available for all packages
|
// Inputs available for all packages
|
||||||
{ DEFIO_TAG_E__PC0, ADC_DEVICES_123, ADC_CHANNEL_10, 10 },
|
{ DEFIO_TAG_E__PC0, ADC_DEVICES_123, ADC_CHANNEL_10, 10 },
|
||||||
|
|
@ -198,7 +204,19 @@ void adcInitDevice(adcDevice_t *adcdev, int channelCount)
|
||||||
hadc->Init.NbrOfDiscConversion = 1; // Don't care
|
hadc->Init.NbrOfDiscConversion = 1; // Don't care
|
||||||
hadc->Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
hadc->Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
||||||
hadc->Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; // Don't care
|
hadc->Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; // Don't care
|
||||||
|
|
||||||
|
// Enable circular DMA.
|
||||||
|
// ADC3 of H72X and H73X has a special way of doing this.
|
||||||
|
#if defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
|
if (adcdev->ADCx == ADC3) {
|
||||||
|
hadc->Init.DMAContinuousRequests = ENABLE;
|
||||||
|
} else
|
||||||
|
#else
|
||||||
|
{
|
||||||
hadc->Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_CIRCULAR;
|
hadc->Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_CIRCULAR;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
hadc->Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
|
hadc->Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
|
||||||
hadc->Init.OversamplingMode = DISABLE;
|
hadc->Init.OversamplingMode = DISABLE;
|
||||||
|
|
||||||
|
|
@ -225,11 +243,21 @@ int adcFindTagMapEntry(ioTag_t tag)
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// H743, H750 and H7A3 seems to use 16-bit precision value,
|
||||||
|
// while H723 and H725 seems to use 12-bit precision value.
|
||||||
|
#if defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
||||||
|
#define VREFINT_CAL_SHIFT 4
|
||||||
|
#elif defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
|
#define VREFINT_CAL_SHIFT 0
|
||||||
|
#else
|
||||||
|
#error Unknown MCU
|
||||||
|
#endif
|
||||||
|
|
||||||
void adcInitCalibrationValues(void)
|
void adcInitCalibrationValues(void)
|
||||||
{
|
{
|
||||||
adcVREFINTCAL = *VREFINT_CAL_ADDR >> 4;
|
adcVREFINTCAL = *VREFINT_CAL_ADDR >> VREFINT_CAL_SHIFT;
|
||||||
adcTSCAL1 = *TEMPSENSOR_CAL1_ADDR >> 4;
|
adcTSCAL1 = *TEMPSENSOR_CAL1_ADDR >> VREFINT_CAL_SHIFT;
|
||||||
adcTSCAL2 = *TEMPSENSOR_CAL2_ADDR >> 4;
|
adcTSCAL2 = *TEMPSENSOR_CAL2_ADDR >> VREFINT_CAL_SHIFT;
|
||||||
adcTSSlopeK = (TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) * 1000 / (adcTSCAL2 - adcTSCAL1);
|
adcTSSlopeK = (TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) * 1000 / (adcTSCAL2 - adcTSCAL1);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -228,7 +228,7 @@ static const dmaPeripheralMapping_t dmaPeripheralMapping[] = {
|
||||||
#ifdef USE_ADC
|
#ifdef USE_ADC
|
||||||
REQMAP(ADC, 1),
|
REQMAP(ADC, 1),
|
||||||
REQMAP(ADC, 2),
|
REQMAP(ADC, 2),
|
||||||
#if defined(STM32H743xx) || defined(STM32H750xx)
|
#if defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
REQMAP(ADC, 3),
|
REQMAP(ADC, 3),
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -90,7 +90,9 @@ const struct ioPortDef_s ioPortDefs[] = {
|
||||||
{ RCC_AHB4(GPIOF) },
|
{ RCC_AHB4(GPIOF) },
|
||||||
{ RCC_AHB4(GPIOG) },
|
{ RCC_AHB4(GPIOG) },
|
||||||
{ RCC_AHB4(GPIOH) },
|
{ RCC_AHB4(GPIOH) },
|
||||||
|
#if !(defined(STM32H723xx) || defined(STM32H725xx))
|
||||||
{ RCC_AHB4(GPIOI) },
|
{ RCC_AHB4(GPIOI) },
|
||||||
|
#endif
|
||||||
};
|
};
|
||||||
#elif defined(STM32G4)
|
#elif defined(STM32G4)
|
||||||
const struct ioPortDef_s ioPortDefs[] = {
|
const struct ioPortDef_s ioPortDefs[] = {
|
||||||
|
|
|
||||||
|
|
@ -84,6 +84,9 @@ void systemInit(void)
|
||||||
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
||||||
__HAL_RCC_AHBSRAM1_CLK_ENABLE();
|
__HAL_RCC_AHBSRAM1_CLK_ENABLE();
|
||||||
__HAL_RCC_AHBSRAM2_CLK_ENABLE();
|
__HAL_RCC_AHBSRAM2_CLK_ENABLE();
|
||||||
|
#elif defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
|
__HAL_RCC_D2SRAM1_CLK_ENABLE();
|
||||||
|
__HAL_RCC_D2SRAM2_CLK_ENABLE();
|
||||||
#else
|
#else
|
||||||
#error Unknown MCU
|
#error Unknown MCU
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -136,7 +139,7 @@ void systemResetToBootloader(bootloaderRequestType_e requestType)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#if defined(STM32H743xx) || defined(STM32H750xx)
|
#if defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
#define SYSMEMBOOT_VECTOR_TABLE ((uint32_t *)0x1ff09800)
|
#define SYSMEMBOOT_VECTOR_TABLE ((uint32_t *)0x1ff09800)
|
||||||
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
||||||
#define SYSMEMBOOT_VECTOR_TABLE ((uint32_t *)0x1ff0a000)
|
#define SYSMEMBOOT_VECTOR_TABLE ((uint32_t *)0x1ff0a000)
|
||||||
|
|
|
||||||
|
|
@ -827,6 +827,18 @@
|
||||||
|
|
||||||
#define DEF_TIM_DMA__BTCH_TIM17_CH1 DEF_TIM_DMA_FULL
|
#define DEF_TIM_DMA__BTCH_TIM17_CH1 DEF_TIM_DMA_FULL
|
||||||
|
|
||||||
|
#if defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
|
#define DEF_TIM_DMA__BTCH_TIM23_CH1 DEF_TIM_DMA_FULL
|
||||||
|
#define DEF_TIM_DMA__BTCH_TIM23_CH2 DEF_TIM_DMA_FULL
|
||||||
|
#define DEF_TIM_DMA__BTCH_TIM23_CH3 DEF_TIM_DMA_FULL
|
||||||
|
#define DEF_TIM_DMA__BTCH_TIM23_CH4 DEF_TIM_DMA_FULL
|
||||||
|
|
||||||
|
#define DEF_TIM_DMA__BTCH_TIM24_CH1 DEF_TIM_DMA_FULL
|
||||||
|
#define DEF_TIM_DMA__BTCH_TIM24_CH2 DEF_TIM_DMA_FULL
|
||||||
|
#define DEF_TIM_DMA__BTCH_TIM24_CH3 DEF_TIM_DMA_FULL
|
||||||
|
#define DEF_TIM_DMA__BTCH_TIM24_CH4 DEF_TIM_DMA_FULL
|
||||||
|
#endif
|
||||||
|
|
||||||
// TIM_UP table
|
// TIM_UP table
|
||||||
#define DEF_TIM_DMA__BTCH_TIM1_UP DEF_TIM_DMA_FULL
|
#define DEF_TIM_DMA__BTCH_TIM1_UP DEF_TIM_DMA_FULL
|
||||||
#define DEF_TIM_DMA__BTCH_TIM2_UP DEF_TIM_DMA_FULL
|
#define DEF_TIM_DMA__BTCH_TIM2_UP DEF_TIM_DMA_FULL
|
||||||
|
|
@ -843,6 +855,11 @@
|
||||||
#define DEF_TIM_DMA__BTCH_TIM16_UP DEF_TIM_DMA_FULL
|
#define DEF_TIM_DMA__BTCH_TIM16_UP DEF_TIM_DMA_FULL
|
||||||
#define DEF_TIM_DMA__BTCH_TIM17_UP DEF_TIM_DMA_FULL
|
#define DEF_TIM_DMA__BTCH_TIM17_UP DEF_TIM_DMA_FULL
|
||||||
|
|
||||||
|
#if defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
|
#define DEF_TIM_DMA__BTCH_TIM23_UP DEF_TIM_DMA_FULL
|
||||||
|
#define DEF_TIM_DMA__BTCH_TIM24_UP DEF_TIM_DMA_FULL
|
||||||
|
#endif
|
||||||
|
|
||||||
// TIMx_CHy request table
|
// TIMx_CHy request table
|
||||||
|
|
||||||
// This is not defined in stm32h7xx_hal_timer.h
|
// This is not defined in stm32h7xx_hal_timer.h
|
||||||
|
|
@ -892,6 +909,18 @@
|
||||||
|
|
||||||
#define DEF_TIM_DMA_REQ__BTCH_TIM17_CH1 DMA_REQUEST_TIM17_CH1
|
#define DEF_TIM_DMA_REQ__BTCH_TIM17_CH1 DMA_REQUEST_TIM17_CH1
|
||||||
|
|
||||||
|
#if defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
|
#define DEF_TIM_DMA_REQ__BTCH_TIM23_CH1 DMA_REQUEST_TIM23_CH1
|
||||||
|
#define DEF_TIM_DMA_REQ__BTCH_TIM23_CH2 DMA_REQUEST_TIM23_CH2
|
||||||
|
#define DEF_TIM_DMA_REQ__BTCH_TIM23_CH3 DMA_REQUEST_TIM23_CH3
|
||||||
|
#define DEF_TIM_DMA_REQ__BTCH_TIM23_CH4 DMA_REQUEST_TIM23_CH4
|
||||||
|
|
||||||
|
#define DEF_TIM_DMA_REQ__BTCH_TIM24_CH1 DMA_REQUEST_TIM24_CH1
|
||||||
|
#define DEF_TIM_DMA_REQ__BTCH_TIM24_CH2 DMA_REQUEST_TIM24_CH2
|
||||||
|
#define DEF_TIM_DMA_REQ__BTCH_TIM24_CH3 DMA_REQUEST_TIM24_CH3
|
||||||
|
#define DEF_TIM_DMA_REQ__BTCH_TIM24_CH4 DMA_REQUEST_TIM24_CH4
|
||||||
|
#endif
|
||||||
|
|
||||||
// TIM_UP request table
|
// TIM_UP request table
|
||||||
#define DEF_TIM_DMA_REQ__BTCH_TIM1_UP DMA_REQUEST_TIM1_UP
|
#define DEF_TIM_DMA_REQ__BTCH_TIM1_UP DMA_REQUEST_TIM1_UP
|
||||||
#define DEF_TIM_DMA_REQ__BTCH_TIM2_UP DMA_REQUEST_TIM2_UP
|
#define DEF_TIM_DMA_REQ__BTCH_TIM2_UP DMA_REQUEST_TIM2_UP
|
||||||
|
|
@ -908,6 +937,11 @@
|
||||||
#define DEF_TIM_DMA_REQ__BTCH_TIM16_UP DMA_REQUEST_TIM16_UP
|
#define DEF_TIM_DMA_REQ__BTCH_TIM16_UP DMA_REQUEST_TIM16_UP
|
||||||
#define DEF_TIM_DMA_REQ__BTCH_TIM17_UP DMA_REQUEST_TIM17_UP
|
#define DEF_TIM_DMA_REQ__BTCH_TIM17_UP DMA_REQUEST_TIM17_UP
|
||||||
|
|
||||||
|
#if defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
|
#define DEF_TIM_DMA_REQ__BTCH_TIM23_UP DMA_REQUEST_TIM23_UP
|
||||||
|
#define DEF_TIM_DMA_REQ__BTCH_TIM24_UP DMA_REQUEST_TIM24_UP
|
||||||
|
#endif
|
||||||
|
|
||||||
// AF table
|
// AF table
|
||||||
|
|
||||||
// NONE
|
// NONE
|
||||||
|
|
@ -1015,6 +1049,22 @@
|
||||||
#define DEF_TIM_AF__PF8__TCH_TIM13_CH1N D(9, 13)
|
#define DEF_TIM_AF__PF8__TCH_TIM13_CH1N D(9, 13)
|
||||||
#define DEF_TIM_AF__PF9__TCH_TIM14_CH1N D(9, 14)
|
#define DEF_TIM_AF__PF9__TCH_TIM14_CH1N D(9, 14)
|
||||||
|
|
||||||
|
#if defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
|
#define DEF_TIM_AF__PF0__TCH_TIM23_CH1 D(13, 23)
|
||||||
|
#define DEF_TIM_AF__PF1__TCH_TIM23_CH2 D(13, 23)
|
||||||
|
#define DEF_TIM_AF__PF2__TCH_TIM23_CH3 D(13, 23)
|
||||||
|
#define DEF_TIM_AF__PF3__TCH_TIM23_CH4 D(13, 23)
|
||||||
|
#define DEF_TIM_AF__PF6__TCH_TIM23_CH1 D(13, 23)
|
||||||
|
#define DEF_TIM_AF__PF7__TCH_TIM23_CH2 D(13, 23)
|
||||||
|
#define DEF_TIM_AF__PF8__TCH_TIM23_CH3 D(13, 23)
|
||||||
|
#define DEF_TIM_AF__PF9__TCH_TIM23_CH4 D(13, 23)
|
||||||
|
|
||||||
|
#define DEF_TIM_AF__PF11__TCH_TIM24_CH1 D(14, 24)
|
||||||
|
#define DEF_TIM_AF__PF12__TCH_TIM24_CH2 D(14, 24)
|
||||||
|
#define DEF_TIM_AF__PF13__TCH_TIM24_CH3 D(14, 24)
|
||||||
|
#define DEF_TIM_AF__PF14__TCH_TIM24_CH4 D(14, 24)
|
||||||
|
#endif
|
||||||
|
|
||||||
//PORTH
|
//PORTH
|
||||||
#define DEF_TIM_AF__PH6__TCH_TIM12_CH1 D(2, 12)
|
#define DEF_TIM_AF__PH6__TCH_TIM12_CH1 D(2, 12)
|
||||||
#define DEF_TIM_AF__PH9__TCH_TIM12_CH2 D(2, 12)
|
#define DEF_TIM_AF__PH9__TCH_TIM12_CH2 D(2, 12)
|
||||||
|
|
|
||||||
|
|
@ -173,7 +173,7 @@ uint32_t timerClock(TIM_TypeDef *tim)
|
||||||
// "Ratio between clock timer and pclk"
|
// "Ratio between clock timer and pclk"
|
||||||
// (Tables are the same, just D2 or CD difference)
|
// (Tables are the same, just D2 or CD difference)
|
||||||
|
|
||||||
#if defined(STM32H743xx) || defined(STM32H750xx)
|
#if defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
#define PERIPH_PRESCALER(bus) ((RCC->D2CFGR & RCC_D2CFGR_D2PPRE ## bus) >> RCC_D2CFGR_D2PPRE ## bus ## _Pos)
|
#define PERIPH_PRESCALER(bus) ((RCC->D2CFGR & RCC_D2CFGR_D2PPRE ## bus) >> RCC_D2CFGR_D2PPRE ## bus ## _Pos)
|
||||||
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
||||||
#define PERIPH_PRESCALER(bus) ((RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE ## bus) >> RCC_CDCFGR2_CDPPRE ## bus ## _Pos)
|
#define PERIPH_PRESCALER(bus) ((RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE ## bus) >> RCC_CDCFGR2_CDPPRE ## bus ## _Pos)
|
||||||
|
|
|
||||||
|
|
@ -49,7 +49,7 @@
|
||||||
#define STM32G4
|
#define STM32G4
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
#elif defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
#include "stm32h7xx.h"
|
#include "stm32h7xx.h"
|
||||||
#include "stm32h7xx_hal.h"
|
#include "stm32h7xx_hal.h"
|
||||||
#include "system_stm32h7xx.h"
|
#include "system_stm32h7xx.h"
|
||||||
|
|
|
||||||
796
src/main/startup/startup_stm32h723xx.s
Normal file
796
src/main/startup/startup_stm32h723xx.s
Normal file
|
|
@ -0,0 +1,796 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_stm32h723xx.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief STM32H723xx Devices vector table for GCC based toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m7
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
ldr sp, =_estack /* set stack pointer */
|
||||||
|
|
||||||
|
bl persistentObjectInit
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/*-----*/
|
||||||
|
ldr r2, =_ssram2
|
||||||
|
b LoopFillZerosram2
|
||||||
|
/* Zero fill the sram2 segment. */
|
||||||
|
FillZerosram2:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerosram2:
|
||||||
|
ldr r3, = _esram2
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerosram2
|
||||||
|
|
||||||
|
ldr r2, =_sfastram_bss
|
||||||
|
b LoopFillZerofastram_bss
|
||||||
|
/* Zero fill the fastram_bss segment. */
|
||||||
|
FillZerofastram_bss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerofastram_bss:
|
||||||
|
ldr r3, = _efastram_bss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerofastram_bss
|
||||||
|
/*-----*/
|
||||||
|
|
||||||
|
/* Mark the heap and stack */
|
||||||
|
ldr r2, =_heap_stack_begin
|
||||||
|
b LoopMarkHeapStack
|
||||||
|
|
||||||
|
MarkHeapStack:
|
||||||
|
movs r3, 0xa5a5a5a5
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopMarkHeapStack:
|
||||||
|
ldr r3, = _heap_stack_end
|
||||||
|
cmp r2, r3
|
||||||
|
bcc MarkHeapStack
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
|
||||||
|
/* External Interrupts */
|
||||||
|
.word WWDG_IRQHandler /* Window WatchDog */
|
||||||
|
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
|
||||||
|
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
|
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
|
.word FLASH_IRQHandler /* FLASH */
|
||||||
|
.word RCC_IRQHandler /* RCC */
|
||||||
|
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
|
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
|
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||||
|
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
|
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
|
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
|
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
|
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
|
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
|
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
|
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
|
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
|
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
|
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
|
||||||
|
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
|
||||||
|
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
|
||||||
|
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
|
||||||
|
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
|
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
|
||||||
|
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
|
||||||
|
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
|
||||||
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
|
.word TIM4_IRQHandler /* TIM4 */
|
||||||
|
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word USART2_IRQHandler /* USART2 */
|
||||||
|
.word USART3_IRQHandler /* USART3 */
|
||||||
|
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
|
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||||
|
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||||
|
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||||
|
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
|
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||||
|
.word FMC_IRQHandler /* FMC */
|
||||||
|
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||||
|
.word TIM5_IRQHandler /* TIM5 */
|
||||||
|
.word SPI3_IRQHandler /* SPI3 */
|
||||||
|
.word UART4_IRQHandler /* UART4 */
|
||||||
|
.word UART5_IRQHandler /* UART5 */
|
||||||
|
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||||
|
.word TIM7_IRQHandler /* TIM7 */
|
||||||
|
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||||
|
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||||
|
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||||
|
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||||
|
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||||
|
.word ETH_IRQHandler /* Ethernet */
|
||||||
|
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||||
|
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||||
|
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||||
|
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||||
|
.word USART6_IRQHandler /* USART6 */
|
||||||
|
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||||
|
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||||
|
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||||
|
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||||
|
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||||
|
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||||
|
.word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word RNG_IRQHandler /* Rng */
|
||||||
|
.word FPU_IRQHandler /* FPU */
|
||||||
|
.word UART7_IRQHandler /* UART7 */
|
||||||
|
.word UART8_IRQHandler /* UART8 */
|
||||||
|
.word SPI4_IRQHandler /* SPI4 */
|
||||||
|
.word SPI5_IRQHandler /* SPI5 */
|
||||||
|
.word SPI6_IRQHandler /* SPI6 */
|
||||||
|
.word SAI1_IRQHandler /* SAI1 */
|
||||||
|
.word LTDC_IRQHandler /* LTDC */
|
||||||
|
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||||
|
.word DMA2D_IRQHandler /* DMA2D */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word OCTOSPI1_IRQHandler /* OCTOSPI1 */
|
||||||
|
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||||
|
.word CEC_IRQHandler /* HDMI_CEC */
|
||||||
|
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||||
|
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||||
|
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||||
|
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||||
|
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||||
|
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||||
|
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||||
|
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||||
|
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||||
|
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||||
|
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||||
|
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word ADC3_IRQHandler /* ADC3 global Interrupt */
|
||||||
|
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||||
|
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
|
||||||
|
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
|
||||||
|
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
|
||||||
|
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
|
||||||
|
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
|
||||||
|
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
|
||||||
|
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
|
||||||
|
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
|
||||||
|
.word COMP1_IRQHandler /* COMP1 global Interrupt */
|
||||||
|
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||||
|
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||||
|
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
|
||||||
|
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
|
||||||
|
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||||
|
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||||
|
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||||
|
.word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||||
|
.word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word FMAC_IRQHandler /* FMAC Interrupt */
|
||||||
|
.word CORDIC_IRQHandler /* CORDIC Interrupt */
|
||||||
|
.word UART9_IRQHandler /* UART9 Interrupt */
|
||||||
|
.word USART10_IRQHandler /* UART10 Interrupt */
|
||||||
|
.word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */
|
||||||
|
.word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */
|
||||||
|
.word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */
|
||||||
|
.word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */
|
||||||
|
.word TIM23_IRQHandler /* TIM23 global interrupt */
|
||||||
|
.word TIM24_IRQHandler /* TIM24 global interrupt */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_AVD_IRQHandler
|
||||||
|
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMP_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_TIM12_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_TIM13_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC1_IRQHandler
|
||||||
|
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_IRQHandler
|
||||||
|
.thumb_set ETH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_WKUP_IRQHandler
|
||||||
|
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN_CAL_IRQHandler
|
||||||
|
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART6_IRQHandler
|
||||||
|
.thumb_set USART6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_EV_IRQHandler
|
||||||
|
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_ER_IRQHandler
|
||||||
|
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_IRQHandler
|
||||||
|
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DCMI_PSSI_IRQHandler
|
||||||
|
.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RNG_IRQHandler
|
||||||
|
.thumb_set RNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART7_IRQHandler
|
||||||
|
.thumb_set UART7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART8_IRQHandler
|
||||||
|
.thumb_set UART8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI4_IRQHandler
|
||||||
|
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI5_IRQHandler
|
||||||
|
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI6_IRQHandler
|
||||||
|
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI1_IRQHandler
|
||||||
|
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_IRQHandler
|
||||||
|
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_ER_IRQHandler
|
||||||
|
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2D_IRQHandler
|
||||||
|
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OCTOSPI1_IRQHandler
|
||||||
|
.thumb_set OCTOSPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM1_IRQHandler
|
||||||
|
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CEC_IRQHandler
|
||||||
|
.thumb_set CEC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_EV_IRQHandler
|
||||||
|
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_ER_IRQHandler
|
||||||
|
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPDIF_RX_IRQHandler
|
||||||
|
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX1_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT0_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT1_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT2_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT3_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SWPMI1_IRQHandler
|
||||||
|
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM15_IRQHandler
|
||||||
|
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM16_IRQHandler
|
||||||
|
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM17_IRQHandler
|
||||||
|
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_WKUP_IRQHandler
|
||||||
|
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_IRQHandler
|
||||||
|
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDMA_IRQHandler
|
||||||
|
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC2_IRQHandler
|
||||||
|
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HSEM1_IRQHandler
|
||||||
|
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC3_IRQHandler
|
||||||
|
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX2_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel0_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel1_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel2_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel3_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel4_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel5_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel6_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel7_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP1_IRQHandler
|
||||||
|
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM2_IRQHandler
|
||||||
|
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM3_IRQHandler
|
||||||
|
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM4_IRQHandler
|
||||||
|
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM5_IRQHandler
|
||||||
|
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPUART1_IRQHandler
|
||||||
|
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CRS_IRQHandler
|
||||||
|
.thumb_set CRS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ECC_IRQHandler
|
||||||
|
.thumb_set ECC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI4_IRQHandler
|
||||||
|
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DTS_IRQHandler
|
||||||
|
.thumb_set DTS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak WAKEUP_PIN_IRQHandler
|
||||||
|
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OCTOSPI2_IRQHandler
|
||||||
|
.thumb_set OCTOSPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMAC_IRQHandler
|
||||||
|
.thumb_set FMAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CORDIC_IRQHandler
|
||||||
|
.thumb_set CORDIC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART9_IRQHandler
|
||||||
|
.thumb_set UART9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART10_IRQHandler
|
||||||
|
.thumb_set USART10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C5_EV_IRQHandler
|
||||||
|
.thumb_set I2C5_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C5_ER_IRQHandler
|
||||||
|
.thumb_set I2C5_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN3_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN3_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM23_IRQHandler
|
||||||
|
.thumb_set TIM23_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM24_IRQHandler
|
||||||
|
.thumb_set TIM24_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
|
|
@ -282,6 +282,29 @@ pllConfig_t pll1Config7A3 = {
|
||||||
// Source for CRS input
|
// Source for CRS input
|
||||||
#define MCU_RCC_CRS_SYNC_SOURCE RCC_CRS_SYNC_SOURCE_USB1
|
#define MCU_RCC_CRS_SYNC_SOURCE RCC_CRS_SYNC_SOURCE_USB1
|
||||||
|
|
||||||
|
#elif defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
|
|
||||||
|
// Nominal max 550MHz
|
||||||
|
|
||||||
|
pllConfig_t pll1Config72x = {
|
||||||
|
.clockMhz = 550,
|
||||||
|
.m = 4,
|
||||||
|
.n = 275,
|
||||||
|
.p = 1,
|
||||||
|
.q = 2,
|
||||||
|
.r = 2,
|
||||||
|
.vos = PWR_REGULATOR_VOLTAGE_SCALE0,
|
||||||
|
.vciRange = RCC_PLL1VCIRANGE_1,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define MCU_HCLK_DIVIDER RCC_HCLK_DIV2
|
||||||
|
|
||||||
|
// RM0468 (Rev.2) Table 16.
|
||||||
|
// 550MHz (AXI Interface clock) at VOS0 is 3WS
|
||||||
|
#define MCU_FLASH_LATENCY FLASH_LATENCY_3
|
||||||
|
|
||||||
|
#define MCU_RCC_CRS_SYNC_SOURCE RCC_CRS_SYNC_SOURCE_USB1
|
||||||
|
|
||||||
#else
|
#else
|
||||||
#error Unknown MCU type
|
#error Unknown MCU type
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -313,6 +336,8 @@ static void SystemClockHSE_Config(void)
|
||||||
pll1Config = (HAL_GetREVID() == REV_ID_V) ? &pll1ConfigRevV : &pll1ConfigRevY;
|
pll1Config = (HAL_GetREVID() == REV_ID_V) ? &pll1ConfigRevV : &pll1ConfigRevY;
|
||||||
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
|
||||||
pll1Config = &pll1Config7A3;
|
pll1Config = &pll1Config7A3;
|
||||||
|
#elif defined(STM32H723xx) || defined(STM32H725xx)
|
||||||
|
pll1Config = &pll1Config72x;
|
||||||
#else
|
#else
|
||||||
#error Unknown MCU type
|
#error Unknown MCU type
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -425,7 +450,7 @@ void SystemClock_Config(void)
|
||||||
{
|
{
|
||||||
// Configure power supply
|
// Configure power supply
|
||||||
|
|
||||||
#if defined(STM32H743xx) || defined(STM32H750xx)
|
#if defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx)
|
||||||
|
|
||||||
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
|
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
|
||||||
|
|
||||||
|
|
@ -434,10 +459,14 @@ void SystemClock_Config(void)
|
||||||
|
|
||||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||||||
|
|
||||||
#elif defined(STM32H7A3xxQ)
|
#elif defined(STM32H7A3xxQ) || defined(STM32H725xx)
|
||||||
|
|
||||||
// Nucleo-H7A3ZI-Q is preconfigured for power supply configuration 2 (Direct SMPS)
|
// We assume all SMPS equipped devices use this mode (Direct SMPS).
|
||||||
// Here we assume that all boards with SMPS equipped devices use this mode.
|
// - All STM32H7A3xxQ devices.
|
||||||
|
// - All STM32H725xx devices (Note STM32H725RG is Direct SMPS only - no LDO).
|
||||||
|
//
|
||||||
|
// - Nucleo-H7A3ZI-Q is preconfigured for power supply configuration 2 (Direct SMPS).
|
||||||
|
// - Nucleo-H723ZI-Q transplanted with STM32H725ZG is the same as above.
|
||||||
|
|
||||||
HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
|
HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue