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[H7] Add USE_TIMER_MGMT to H7
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jflyper
parent
ad00c6b66b
commit
22d046c879
6 changed files with 146 additions and 10 deletions
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@ -24,6 +24,10 @@
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#include "common/utils.h"
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#include "drivers/dma.h"
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#include "drivers/io.h"
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#include "drivers/timer_def.h"
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#include "stm32h7xx.h"
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#include "rcc.h"
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#include "timer.h"
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@ -45,6 +49,116 @@ const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
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{ .TIMx = TIM17, .rcc = RCC_APB2(TIM17), .inputIrq = TIM17_IRQn},
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};
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#if defined(USE_TIMER_MGMT)
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const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
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// Auto-generated from 'timer_def.h'
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// Port A
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DEF_TIM(TIM2, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM2, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM2, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM2, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM2, CH1, PA5, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH1, PA8, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH2, PA9, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH3, PA10, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH4, PA11, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM2, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM5, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM5, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM3, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM3, CH2, PA7, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM8, CH1N, PA5, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM8, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM13, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM14, CH1, PA7, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM15, CH1N, PA1, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM15, CH1, PA2, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM15, CH2, PA2, TIM_USE_ANY, 0, 0, 0),
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// Port B
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DEF_TIM(TIM1, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM2, CH2, PB3, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM16, CH1N, PB6, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM17, CH1N, PB7, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM16, CH1, PB8, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM17, CH1, PB9, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH1N, PB13, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM3, CH3, PB0, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM3, CH4, PB1, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM3, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM3, CH2, PB5, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM4, CH1, PB6, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM4, CH2, PB7, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM4, CH3, PB8, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM4, CH4, PB9, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM12, CH1, PB14, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM12, CH2, PB15, TIM_USE_ANY, 0, 0, 0),
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// Port C
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DEF_TIM(TIM3, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM3, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM3, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM3, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM8, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM8, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM8, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM8, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
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// Port D
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DEF_TIM(TIM4, CH1, PD12, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM4, CH2, PD13, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM4, CH3, PD14, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM4, CH4, PD15, TIM_USE_ANY, 0, 0, 0),
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// Port E
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DEF_TIM(TIM1, CH1N, PE8, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH1, PE9, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH2N, PE10, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH2, PE11, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH3N, PE12, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH3, PE13, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM1, CH4, PE14, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM15, CH1N, PE4, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM15, CH1, PE5, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM15, CH2, PE6, TIM_USE_ANY, 0, 0, 0),
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// Port F
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DEF_TIM(TIM16, CH1, PF6, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM17, CH1, PF7, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM16, CH1N, PF8, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM17, CH1N, PF9, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM13, CH1N, PF8, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM14, CH1N, PF9, TIM_USE_ANY, 0, 0, 0),
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// Port H
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DEF_TIM(TIM12, CH1, PH6, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM12, CH2, PH9, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM5, CH1, PH10, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM5, CH2, PH11, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM5, CH3, PH12, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM8, CH1N, PH13, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM8, CH2N, PH14, TIM_USE_ANY, 0, 0, 0),
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DEF_TIM(TIM8, CH3N, PH15, TIM_USE_ANY, 0, 0, 0),
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};
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#endif
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uint32_t timerClock(TIM_TypeDef *tim)
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{
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int timpre;
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