Adding RP2350 SDK and target framework (#13988)

* Adding RP2350 SDK and target framework * Spacing * Removing board definitions
2025-07-23 08:15:30 +03:00 · 2024-10-23 10:02:48 +11:00 · 2024-10-23 10:02:48 +11:00 · 2dd6f95aad
commit 2dd6f95aad
parent 462cb05930
576 changed files with 435012 additions and 0 deletions
--- a/lib/main/pico-sdk/host/README.md
+++ b/lib/main/pico-sdk/host/README.md
@ -0,0 +1,14 @@
+This is a basic set of replacement library implementations sufficient to get simple applications
+running on your computer (Raspberry Pi OS, Linux, macOS or Windows using Cygwin or Windows Subsystem for Linux).
+It is selected by `PICO_PLATFORM=host` in your CMake build
+
+This can be extremely useful for testing and debugging higher level application code, or porting code which is not yet small enough 
+to run on the RP2040 or RP2350 device itself.
+
+This base level host library provides a minimal environment to compile programs, but is likely sufficient for programs
+that don't access hardware directly.
+
+It is possible however to inject additional SDK library implementations/simulations to provide 
+more complete functionality. For an example of this see the [pico-host-sdl](https://github.com/raspberrypi/pico-host-sdl) 
+which uses the SDL2 library to add additional library support for pico_multicore, timers/alarms in pico-time and 
+pico-audio/pico-scanvideo from [pico-extras](https://github.com/raspberrypi/pico-extras)
--- a/lib/main/pico-sdk/host/boot_stage2.c
+++ b/lib/main/pico-sdk/host/boot_stage2.c
@ -0,0 +1,3 @@
+int main() {
+
+}
--- a/lib/main/pico-sdk/host/hardware_divider/divider.c
+++ b/lib/main/pico-sdk/host/hardware_divider/divider.c
@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/divider.h"
+
+__thread uint64_t hw_divider_result_threadlocal;
--- a/lib/main/pico-sdk/host/hardware_divider/include/hardware/divider.h
+++ b/lib/main/pico-sdk/host/hardware_divider/include/hardware/divider.h
@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_DIVIDER_H
+#define _HARDWARE_DIVIDER_H
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint64_t divmod_result_t;
+
+static inline int __sign_of(int32_t v) {
+    return v > 0 ? 1 : (v < 0 ? -1 : 0);
+}
+
+/*! \brief Do an unsigned HW divide and wait for result
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Results of divide as a 32p32 fixed point value.
+ */
+static inline divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b)  {
+    if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-1); // todo check this
+    return (((uint64_t)(a%b))<<32u) | (a/b);
+}
+
+/*! \brief Do a signed HW divide and wait for result
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Results of divide as a 32p32 fixed point value.
+ */
+static inline divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b) {
+    if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-__sign_of(a));
+    return (((uint64_t)(a%b))<<32u) | (uint32_t)(a/b);
+}
+
+extern __thread divmod_result_t hw_divider_result_threadlocal;
+
+/*! \brief Start a signed asynchronous divide
+ *  \ingroup hardware_divider
+ *
+ * Start a divide of the specified signed parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set
+ * (hw_divider_wait_ready()) prior to reading the results.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ */
+static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) {
+    hw_divider_result_threadlocal = hw_divider_divmod_s32(a, b);
+}
+
+/*! \brief Start an unsigned asynchronous divide
+ *  \ingroup hardware_divider
+ *
+ * Start a divide of the specified unsigned parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set
+ * (hw_divider_wait_ready()) prior to reading the results.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ */
+static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) {
+    hw_divider_result_threadlocal = hw_divider_divmod_u32(a, b);
+}
+
+/*! \brief Return result of last asynchronous HW divide
+ *  \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient.
+ */
+static inline divmod_result_t hw_divider_result_wait(void) {
+    return hw_divider_result_threadlocal;
+}
+
+/*! \brief Return result of HW divide, nowait
+ *  \ingroup hardware_divider
+ *
+ * \note This is UNSAFE in that the calculation may not have been completed.
+ *
+ * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient.
+ */
+static inline divmod_result_t hw_divider_result_nowait(void) {
+    return hw_divider_result_threadlocal;
+}
+
+/*! \brief Wait for a divide to complete
+ *  \ingroup hardware_divider
+ *
+ * Wait for a divide to complete
+ */
+static inline void hw_divider_wait_ready(void) {}
+
+
+/*! \brief Efficient extraction of unsigned quotient from 32p32 fixed point
+ *  \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Unsigned quotient
+ */
+inline static uint32_t to_quotient_u32(divmod_result_t r) {
+    return (uint32_t) r;
+}
+
+/*! \brief Efficient extraction of signed quotient from 32p32 fixed point
+ *  \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Unsigned quotient
+ */
+inline static int32_t to_quotient_s32(divmod_result_t r) {
+    return (int32_t)(uint32_t)r;
+}
+
+/*! \brief Efficient extraction of unsigned remainder from 32p32 fixed point
+ *  \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Unsigned remainder
+ *
+ * \note On Arm this is just a 32 bit register move or a nop
+ */
+inline static uint32_t to_remainder_u32(divmod_result_t r) {
+    return (uint32_t)(r >> 32u);
+}
+
+/*! \brief Efficient extraction of signed remainder from 32p32 fixed point
+ *  \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Signed remainder
+ *
+ * \note On arm this is just a 32 bit register move or a nop
+ */
+inline static int32_t to_remainder_s32(divmod_result_t r) {
+    return (int32_t)(r >> 32u);
+}
+
+static inline void hw_divider_pause(void) {}
+
+/*! \brief Do an unsigned HW divide, wait for result, return quotient
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient results of the divide
+ */
+static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) {
+    return b ? (a / b) : (uint32_t)(-1);
+}
+
+/*! \brief Do an unsigned HW divide, wait for result, return remainder
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder results of the divide
+ */
+static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) {
+    return b ? (a % b) : a;
+}
+
+/*! \brief Do a signed HW divide, wait for result, return quotient
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient results of the divide
+ */
+static inline int32_t hw_divider_quotient_s32(int32_t a, int32_t b) {
+    return to_quotient_s32(hw_divider_divmod_s32(a, b));
+}
+
+/*! \brief Do a signed HW divide, wait for result, return remainder
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder results of the divide
+ */
+static inline int32_t hw_divider_remainder_s32(int32_t a, int32_t b) {
+    return b ? (a % b) : a;
+}
+
+/*! \brief Return result of last asynchronous HW divide, unsigned quotient only
+ *  \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current unsigned quotient result.
+ */
+static inline uint32_t hw_divider_u32_quotient_wait(void) {
+    return to_quotient_u32(hw_divider_result_wait());
+}
+
+/*! \brief Return result of last asynchronous HW divide, signed quotient only
+ *  \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current signed quotient result.
+ */
+static inline int32_t hw_divider_s32_quotient_wait(void) {
+    return to_remainder_u32(hw_divider_result_wait());
+}
+
+/*! \brief Return result of last asynchronous HW divide, unsigned remainder only
+ *  \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current unsigned remainder result.
+ */
+static inline uint32_t hw_divider_u32_remainder_wait(void) {
+    return to_quotient_s32(hw_divider_result_wait());
+}
+
+/*! \brief Return result of last asynchronous HW divide, signed remainder only
+ *  \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current remainder results.
+ */
+static inline int32_t hw_divider_s32_remainder_wait(void) {
+    return to_remainder_s32(hw_divider_result_wait());
+}
+
+/*! \brief Do a hardware unsigned HW divide, wait for result, return quotient
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient result of the divide
+ */
+static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) {
+    return hw_divider_u32_quotient(a,b);
+}
+
+/*! \brief Do a hardware unsigned HW divide, wait for result, return remainder
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder result of the divide
+ */
+static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) {
+    return hw_divider_u32_remainder(a,b);
+}
+
+/*! \brief Do a hardware signed HW divide, wait for result, return quotient
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient result of the divide
+ */
+static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) {
+    return hw_divider_quotient_s32(a,b);
+}
+
+/*! \brief Do a hardware signed HW divide, wait for result, return remainder
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder result of the divide
+ */
+static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) {
+    return hw_divider_remainder_s32(a,b);
+}
+
+typedef uint64_t hw_divider_state_t;
+
+/*! \brief Save the calling cores hardware divider state
+ *  \ingroup hardware_divider
+ *
+ * Copy the current core's hardware divider state into the provided structure. This method
+ * waits for the divider results to be stable, then copies them to memory.
+ * They can be restored via hw_divider_restore_state()
+ *
+ * \param dest the location to store the divider state
+ */
+ static inline void hw_divider_save_state(hw_divider_state_t *dest) {
+    *dest = hw_divider_result_threadlocal;
+}
+
+/*! \brief Load a saved hardware divider state into the current core's hardware divider
+ *  \ingroup hardware_divider
+ *
+ * Copy the passed hardware divider state into the hardware divider.
+ *
+ * \param src the location to load the divider state from
+ */
+ static inline void hw_divider_restore_state(hw_divider_state_t *src) {
+    hw_divider_result_threadlocal = *src;
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _HARDWARE_DIVIDER_H
--- a/lib/main/pico-sdk/host/hardware_gpio/gpio.c
+++ b/lib/main/pico-sdk/host/hardware_gpio/gpio.c
@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/gpio.h"
+
+// todo weak or replace? probably weak
+void gpio_set_function(uint gpio, enum gpio_function fn) {
+
+}
+
+void gpio_pull_up(uint gpio) {
+
+}
+
+void gpio_pull_down(uint gpio) {
+
+}
+
+void gpio_disable_pulls(uint gpio) {
+
+}
+
+void gpio_set_pulls(uint gpio, bool up, bool down) {
+
+}
+
+void gpio_set_irqover(uint gpio, uint value) {
+
+}
+
+void gpio_set_outover(uint gpio, uint value) {
+
+}
+
+void gpio_set_inover(uint gpio, uint value) {
+
+}
+
+void gpio_set_oeover(uint gpio, uint value) {
+
+}
+
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled){
+
+}
+
+bool gpio_is_input_hysteresis_enabled(uint gpio){
+    return true;
+}
+
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew){
+
+}
+
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio){
+    return GPIO_SLEW_RATE_FAST;
+}
+
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive){
+
+}
+
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio){
+    return GPIO_DRIVE_STRENGTH_4MA;
+}
+
+
+void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enable) {
+
+}
+
+void gpio_acknowledge_irq(uint gpio, uint32_t events) {
+
+}
+
+void gpio_init(uint gpio) {
+
+}
+
+PICO_WEAK_FUNCTION_DEF(gpio_get)
+
+bool PICO_WEAK_FUNCTION_IMPL_NAME(gpio_get)(uint gpio) {
+    return 0;
+}
+
+uint32_t gpio_get_all() {
+    return 0;
+}
+
+void gpio_set_mask(uint32_t mask) {
+
+}
+
+void gpio_clr_mask(uint32_t mask) {
+
+}
+
+void gpio_xor_mask(uint32_t mask) {
+
+}
+
+void gpio_put_masked(uint32_t mask, uint32_t value) {
+
+}
+
+void gpio_put_all(uint32_t value) {
+
+}
+
+void gpio_put(uint gpio, int value) {
+
+}
+
+void gpio_set_dir_out_masked(uint32_t mask) {
+
+}
+
+void gpio_set_dir_in_masked(uint32_t mask) {
+
+}
+
+void gpio_set_dir_masked(uint32_t mask, uint32_t value) {
+
+}
+
+void gpio_set_dir_all_bits(uint32_t value) {
+
+}
+
+void gpio_set_dir(uint gpio, bool out) {
+
+}
+
+void gpio_debug_pins_init() {
+
+}
+
+void gpio_set_input_enabled(uint gpio, bool enable) {
+
+}
+
+void gpio_init_mask(uint gpio_mask) {
+
+}
--- a/lib/main/pico-sdk/host/hardware_gpio/include/hardware/gpio.h
+++ b/lib/main/pico-sdk/host/hardware_gpio/include/hardware/gpio.h
@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_GPIO_H
+#define _HARDWARE_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "pico.h"
+
+enum gpio_function {
+    GPIO_FUNC_XIP = 0,
+    GPIO_FUNC_SPI = 1,
+    GPIO_FUNC_UART = 2,
+    GPIO_FUNC_I2C = 3,
+    GPIO_FUNC_PWM = 4,
+    GPIO_FUNC_SIO = 5,
+    GPIO_FUNC_PIO0 = 6,
+    GPIO_FUNC_PIO1 = 7,
+    GPIO_FUNC_GPCK = 8,
+    GPIO_FUNC_USB = 9,
+    GPIO_FUNC_NULL = 0xf,
+};
+
+enum gpio_slew_rate {
+    GPIO_SLEW_RATE_SLOW = 0,  ///< Slew rate limiting enabled
+    GPIO_SLEW_RATE_FAST = 1   ///< Slew rate limiting disabled
+};
+
+enum gpio_drive_strength {
+    GPIO_DRIVE_STRENGTH_2MA = 0, ///< 2 mA nominal drive strength
+    GPIO_DRIVE_STRENGTH_4MA = 1, ///< 4 mA nominal drive strength
+    GPIO_DRIVE_STRENGTH_8MA = 2, ///< 8 mA nominal drive strength
+    GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength
+};
+
+#define GPIO_OUT 1
+#define GPIO_IN 0
+
+// ----------------------------------------------------------------------------
+// Pad Controls + IO Muxing
+// ----------------------------------------------------------------------------
+// Declarations for gpio.c
+
+void gpio_set_function(uint gpio, enum gpio_function fn);
+
+enum gpio_function gpio_get_function(uint gpio);
+
+void gpio_pull_up(uint gpio);
+
+void gpio_pull_down(uint gpio);
+
+void gpio_disable_pulls(uint gpio);
+
+void gpio_set_pulls(uint gpio, bool up, bool down);
+
+void gpio_set_irqover(uint gpio, uint value);
+
+void gpio_set_outover(uint gpio, uint value);
+
+void gpio_set_inover(uint gpio, uint value);
+
+void gpio_set_oeover(uint gpio, uint value);
+
+void gpio_set_input_enabled(uint gpio, bool enable);
+
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled);
+
+bool gpio_is_input_hysteresis_enabled(uint gpio);
+
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew);
+
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio);
+
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive);
+
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio);
+
+// Configure a GPIO for direct input/output from software
+void gpio_init(uint gpio);
+
+void gpio_init_mask(uint gpio_mask);
+
+// ----------------------------------------------------------------------------
+// Input
+// ----------------------------------------------------------------------------
+
+// Get the value of a single GPIO
+bool gpio_get(uint gpio);
+
+// Get raw value of all
+uint32_t gpio_get_all();
+
+// ----------------------------------------------------------------------------
+// Output
+// ----------------------------------------------------------------------------
+
+// Drive high every GPIO appearing in mask
+void gpio_set_mask(uint32_t mask);
+
+void gpio_clr_mask(uint32_t mask);
+
+// Toggle every GPIO appearing in mask
+void gpio_xor_mask(uint32_t mask);
+
+
+// For each 1 bit in "mask", drive that pin to the value given by
+// corresponding bit in "value", leaving other pins unchanged.
+// Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ
+// bashing different pins from the same core.
+void gpio_put_masked(uint32_t mask, uint32_t value);
+
+// Drive all pins simultaneously
+void gpio_put_all(uint32_t value);
+
+
+// Drive a single GPIO high/low
+void gpio_put(uint gpio, int value);
+
+// ----------------------------------------------------------------------------
+// Direction
+// ----------------------------------------------------------------------------
+
+// Switch all GPIOs in "mask" to output
+void gpio_set_dir_out_masked(uint32_t mask);
+
+// Switch all GPIOs in "mask" to input
+void gpio_set_dir_in_masked(uint32_t mask);
+
+// For each 1 bit in "mask", switch that pin to the direction given by
+// corresponding bit in "value", leaving other pins unchanged.
+// E.g. gpio_set_dir_masked(0x3, 0x2); -> set pin 0 to input, pin 1 to output,
+// simultaneously.
+void gpio_set_dir_masked(uint32_t mask, uint32_t value);
+
+// Set direction of all pins simultaneously.
+// For each bit in value,
+// 1 = out
+// 0 = in
+void gpio_set_dir_all_bits(uint32_t value);
+
+// Set a single GPIO to input/output.
+// true = out
+// 0 = in
+void gpio_set_dir(uint gpio, bool out);
+
+// debugging
+#ifndef PICO_DEBUG_PIN_BASE
+#define PICO_DEBUG_PIN_BASE 19u
+#endif
+
+// note these two macros may only be used once per compilation unit
+#define CU_REGISTER_DEBUG_PINS(p, ...)
+#define CU_SELECT_DEBUG_PINS(x)
+#define DEBUG_PINS_ENABLED(p) false
+
+#define DEBUG_PINS_SET(p, v) ((void)0)
+#define DEBUG_PINS_CLR(p, v) ((void)0)
+#define DEBUG_PINS_XOR(p, v) ((void)0)
+
+void gpio_debug_pins_init();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/lib/main/pico-sdk/host/hardware_irq/include/hardware/irq.h
+++ b/lib/main/pico-sdk/host/hardware_irq/include/hardware/irq.h
@ -0,0 +1,381 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_IRQ_H
+#define _HARDWARE_IRQ_H
+
+// These two config items are also used by assembler, so keeping separate
+// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq
+#ifndef PICO_MAX_SHARED_IRQ_HANDLERS
+#define PICO_MAX_SHARED_IRQ_HANDLERS 4
+#endif
+
+// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq
+#ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS
+#define PICO_DISABLE_SHARED_IRQ_HANDLERS 0
+#endif
+
+// PICO_CONFIG: PICO_VTABLE_PER_CORE, User is using separate vector tables per core, type=bool, default=0, group=hardware_irq
+#ifndef PICO_VTABLE_PER_CORE
+#define PICO_VTABLE_PER_CORE 0
+#endif
+
+#include "pico.h"
+#include "hardware/regs/intctrl.h"
+
+/** \file irq.h
+ *  \defgroup hardware_irq hardware_irq
+ *
+ * \brief Hardware interrupt handling
+ *
+ * The RP2040 uses the standard ARM nested vectored interrupt controller (NVIC).
+ *
+ * Interrupts are identified by a number from 0 to 31.
+ *
+ * On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing).
+ *
+ * There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts
+ * where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be
+ * interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank.
+ *
+ * \note That all IRQ APIs affect the executing core only (i.e. the core calling the function).
+ *
+ * \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions
+ * or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one core does not disable interrupts
+ * on the other core.
+ *
+ * There are three different ways to set handlers for an IRQ:
+ *  - Calling irq_add_shared_handler() at runtime to add a handler for a multiplexed interrupt (e.g. GPIO bank) on the current core. Each handler, should check and clear the relevant hardware interrupt source
+ *  - Calling irq_set_exclusive_handler() at runtime to install a single handler for the interrupt on the current core
+ *  - Defining the interrupt handler explicitly in your application (e.g. by defining void `isr_dma_0` will make that function the handler for the DMA_IRQ_0 on core 0, and
+ *    you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used).
+ *
+ * \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will
+ * be in register r0.
+ *
+ * \section interrupt_nums Interrupt Numbers
+ *
+ * Interrupts are numbered as follows, a set of defines is available (intctrl.h) with these names to avoid using the numbers directly.
+ *
+ * IRQ | Interrupt Source
+ * ----|-----------------
+ *  0 | TIMER_IRQ_0
+ *  1 | TIMER_IRQ_1
+ *  2 | TIMER_IRQ_2
+ *  3 | TIMER_IRQ_3
+ *  4 | PWM_IRQ_WRAP
+ *  5 | USBCTRL_IRQ
+ *  6 | XIP_IRQ
+ *  7 | PIO0_IRQ_0
+ *  8 | PIO0_IRQ_1
+ *  9 | PIO1_IRQ_0
+ * 10 | PIO1_IRQ_1
+ * 11 | DMA_IRQ_0
+ * 12 | DMA_IRQ_1
+ * 13 | IO_IRQ_BANK0
+ * 14 | IO_IRQ_QSPI
+ * 15 | SIO_IRQ_PROC0
+ * 16 | SIO_IRQ_PROC1
+ * 17 | CLOCKS_IRQ
+ * 18 | SPI0_IRQ
+ * 19 | SPI1_IRQ
+ * 20 | UART0_IRQ
+ * 21 | UART1_IRQ
+ * 22 | ADC0_IRQ_FIFO
+ * 23 | I2C0_IRQ
+ * 24 | I2C1_IRQ
+ * 25 | RTC_IRQ
+ *
+ */
+
+// PICO_CONFIG: PICO_DEFAULT_IRQ_PRIORITY, Define the default IRQ priority, default=0x80, group=hardware_irq
+#ifndef PICO_DEFAULT_IRQ_PRIORITY
+#define PICO_DEFAULT_IRQ_PRIORITY 0x80
+#endif
+
+#define PICO_LOWEST_IRQ_PRIORITY 0xff
+#define PICO_HIGHEST_IRQ_PRIORITY 0x00
+
+// PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq
+#ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
+#define PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY 0x80
+#endif
+
+#define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff
+#define PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY 0x00
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ, Enable/disable assertions in the hardware_irq module, type=bool, default=0, group=hardware_irq
+#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ
+#ifdef PARAM_ASSERTIONS_ENABLED_IRQ // backwards compatibility with SDK < 2.0.0
+#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ PARAM_ASSERTIONS_ENABLED_IRQ
+#else
+#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ 0
+#endif
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Interrupt handler function type
+ *  \ingroup hardware_irq
+ *
+ * All interrupts handlers should be of this type, and follow normal ARM EABI register saving conventions
+ */
+typedef void (*irq_handler_t)(void);
+
+static inline void check_irq_param(__unused uint num) {
+    invalid_params_if(HARDWARE_IRQ, num >= NUM_IRQS);
+}
+
+/*! \brief Set specified interrupt's priority
+ *  \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param hardware_priority Priority to set.
+ * Numerically-lower values indicate a higher priority. Hardware priorities
+ * range from 0 (highest priority) to 255 (lowest priority) though only the
+ * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify
+ * higher or lower priorities than the default, all IRQ priorities are
+ * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
+ * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80
+ */
+void irq_set_priority(uint num, uint8_t hardware_priority);
+
+/*! \brief Get specified interrupt's priority
+ *  \ingroup hardware_irq
+ *
+ * Numerically-lower values indicate a higher priority. Hardware priorities
+ * range from 0 (highest priority) to 255 (lowest priority) though only the
+ * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify
+ * higher or lower priorities than the default, all IRQ priorities are
+ * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
+ * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \return the IRQ priority
+ */
+uint irq_get_priority(uint num);
+
+/*! \brief Enable or disable a specific interrupt on the executing core
+ *  \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param enabled true to enable the interrupt, false to disable
+ */
+void irq_set_enabled(uint num, bool enabled);
+
+/*! \brief Determine if a specific interrupt is enabled on the executing core
+ *  \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \return true if the interrupt is enabled
+ */
+bool irq_is_enabled(uint num);
+
+/*! \brief Enable/disable multiple interrupts on the executing core
+ *  \ingroup hardware_irq
+ *
+ * \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums
+ * \param enabled true to enable the interrupts, false to disable them.
+ */
+void irq_set_mask_enabled(uint32_t mask, bool enabled);
+
+/*! \brief Enable/disable multiple interrupts on the executing core
+ *  \ingroup hardware_irq
+ *
+ * \param n the index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc.
+ * \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums
+ * \param enabled true to enable the interrupts, false to disable them.
+ */
+void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled);
+
+/*! \brief  Set an exclusive interrupt handler for an interrupt on the executing core.
+ *  \ingroup hardware_irq
+ *
+ * Use this method to set a handler for single IRQ source interrupts, or when
+ * your code, use case or performance requirements dictate that there should
+ * no other handlers for the interrupt.
+ *
+ * This method will assert if there is already any sort of interrupt handler installed
+ * for the specified irq number.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param handler The handler to set. See \ref irq_handler_t
+ * \see irq_add_shared_handler()
+ */
+void irq_set_exclusive_handler(uint num, irq_handler_t handler);
+
+/*! \brief  Get the exclusive interrupt handler for an interrupt on the executing core.
+ *  \ingroup hardware_irq
+ *
+ * This method will return an exclusive IRQ handler set on this core
+ * by irq_set_exclusive_handler if there is one.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \see irq_set_exclusive_handler()
+ * \return handler The handler if an exclusive handler is set for the IRQ,
+ *                 NULL if no handler is set or shared/shareable handlers are installed
+ */
+irq_handler_t irq_get_exclusive_handler(uint num);
+
+/*! \brief Add a shared interrupt handler for an interrupt on the executing core
+ *  \ingroup hardware_irq
+ *
+ * Use this method to add a handler on an irq number shared between multiple distinct hardware sources (e.g. GPIO, DMA or PIO IRQs).
+ * Handlers added by this method will all be called in sequence from highest order_priority to lowest. The
+ * irq_set_exclusive_handler() method should be used instead if you know there will or should only ever be one handler for the interrupt.
+ *
+ * This method will assert if there is an exclusive interrupt handler set for this irq number on this core, or if
+ * the (total across all IRQs on both cores) maximum (configurable via PICO_MAX_SHARED_IRQ_HANDLERS) number of shared handlers
+ * would be exceeded.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param handler The handler to set. See \ref irq_handler_t
+ * \param order_priority The order priority controls the order that handlers for the same IRQ number on the core are called.
+ * The shared irq handlers for an interrupt are all called when an IRQ fires, however the order of the calls is based
+ * on the order_priority (higher priorities are called first, identical priorities are called in undefined order). A good
+ * rule of thumb is to use PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY if you don't much care, as it is in the middle of
+ * the priority range by default.
+ *
+ * \note The order_priority uses \em higher values for higher priorities which is the \em opposite of the CPU interrupt priorities passed
+ * to irq_set_priority() which use lower values for higher priorities.
+ *
+ * \see irq_set_exclusive_handler()
+ */
+void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority);
+
+/*! \brief Remove a specific interrupt handler for the given irq number on the executing core
+ *  \ingroup hardware_irq
+ *
+ * This method may be used to remove an irq set via either irq_set_exclusive_handler() or
+ * irq_add_shared_handler(), and will assert if the handler is not currently installed for the given
+ * IRQ number
+ *
+ * \note This method may *only* be called from user (non IRQ code) or from within the handler
+ * itself (i.e. an IRQ handler may remove itself as part of handling the IRQ). Attempts to call
+ * from another IRQ will cause an assertion.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param handler The handler to removed.
+ * \see irq_set_exclusive_handler()
+ * \see irq_add_shared_handler()
+ */
+void irq_remove_handler(uint num, irq_handler_t handler);
+
+/*! \brief Determine if the current handler for the given number is shared
+ *  \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \return true if the specified IRQ has a shared handler
+ */
+bool irq_has_shared_handler(uint num);
+
+/*! \brief Get the current IRQ handler for the specified IRQ from the currently installed hardware vector table (VTOR)
+ * of the execution core
+ *  \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \return the address stored in the VTABLE for the given irq number
+ */
+irq_handler_t irq_get_vtable_handler(uint num);
+
+/*! \brief Clear a specific interrupt on the executing core
+ *  \ingroup hardware_irq
+ *
+ * This method is only useful for "software" IRQs that are not connected to hardware (i.e. IRQs 26-31)
+ * as the the NVIC always reflects the current state of the IRQ state of the hardware for hardware IRQs, and clearing
+ * of the IRQ state of the hardware is performed via the hardware's registers instead.
+ *
+ * \param int_num Interrupt number \ref interrupt_nums
+ */
+void irq_clear(uint int_num);
+
+/*! \brief Force an interrupt to be pending on the executing core
+ *  \ingroup hardware_irq
+ *
+ * This should generally not be used for IRQs connected to hardware.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ */
+void irq_set_pending(uint num);
+
+
+/*! \brief Perform IRQ priority initialization for the current core
+ *
+ * \note This is an internal method and user should generally not call it.
+ */
+void irq_init_priorities(void);
+
+/*! \brief Claim ownership of a user IRQ on the calling core
+ *  \ingroup hardware_irq
+ *  
+ * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending.
+ *
+ * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions
+ * dealing with Uer IRQs affect only the calling core
+ * 
+ * This method explicitly claims ownership of a user IRQ, so other code can know it is being used.
+ *
+ * \param irq_num the user IRQ to claim
+ */
+void user_irq_claim(uint irq_num);
+
+/*! \brief Mark a user IRQ as no longer used on the calling core
+ *  \ingroup hardware_irq
+ *
+ * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending.
+ *
+ * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions
+ * dealing with Uer IRQs affect only the calling core
+ * 
+ * This method explicitly releases ownership of a user IRQ, so other code can know it is free to use.
+ * 
+ * \note it is customary to have disabled the irq and removed the handler prior to calling this method.
+ *
+ * \param irq_num the irq irq_num to unclaim
+ */
+void user_irq_unclaim(uint irq_num);
+
+/*! \brief Claim ownership of a free user IRQ on the calling core
+ *  \ingroup hardware_irq
+ *  
+ * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending.
+ *
+ * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions
+ * dealing with Uer IRQs affect only the calling core
+ * 
+ * This method explicitly claims ownership of an unused user IRQ if there is one, so other code can know it is being used.
+ *
+ * \param required if true the function will panic if none are available
+ * \return the user IRQ number or -1 if required was false, and none were free
+ */
+int user_irq_claim_unused(bool required);
+
+/*
+*! \brief Check if a user IRQ is in use on the calling core
+ *  \ingroup hardware_irq
+ *  
+ * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending.
+ *
+ * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions
+ * dealing with Uer IRQs affect only the calling core
+ *
+ * \param irq_num the irq irq_num
+ * \return true if the irq_num is claimed, false otherwise
+ * \sa user_irq_claim
+ * \sa user_irq_unclaim
+ * \sa user_irq_claim_unused
+ */
+bool user_irq_is_claimed(uint irq_num);
+
+void __unhandled_user_irq(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/lib/main/pico-sdk/host/hardware_irq/irq.c
+++ b/lib/main/pico-sdk/host/hardware_irq/irq.c
@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/irq.h"
+#include "hardware/claim.h"
+
+// totally non-functional IRQ
+
+#if PICO_VTABLE_PER_CORE
+static uint8_t user_irq_claimed[NUM_CORES];
+static inline uint8_t *user_irq_claimed_ptr(void) {
+    return &user_irq_claimed[get_core_num()];
+}
+#else
+static uint8_t user_irq_claimed;
+static inline uint8_t *user_irq_claimed_ptr(void) {
+    return &user_irq_claimed;
+}
+#endif
+
+PICO_WEAK_FUNCTION_DEF(irq_set_enabled)
+void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_enabled)(uint num, bool enabled) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_is_enabled)
+bool PICO_WEAK_FUNCTION_IMPL_NAME(irq_is_enabled)(uint num) {
+    return false;
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_set_mask_enabled)
+void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_mask_enabled)(uint32_t mask, bool enabled) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_set_mask_n_enabled)
+void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_mask_n_enabled)(uint n, uint32_t mask, bool enabled) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_set_pending)
+void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_pending)(uint num) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_has_shared_handler)
+bool PICO_WEAK_FUNCTION_IMPL_NAME(irq_has_shared_handler)(uint irq_num) {
+    return false;
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_get_vtable_handler)
+irq_handler_t PICO_WEAK_FUNCTION_IMPL_NAME(irq_get_vtable_handler)(uint num) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_set_exclusive_handler)
+void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_exclusive_handler)(uint num, irq_handler_t handler) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_get_exclusive_handler)
+irq_handler_t PICO_WEAK_FUNCTION_IMPL_NAME(irq_get_exclusive_handler)(uint num) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_add_shared_handler)
+void PICO_WEAK_FUNCTION_IMPL_NAME(irq_add_shared_handler)(uint num, irq_handler_t handler, uint8_t order_priority) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_remove_handler)
+void PICO_WEAK_FUNCTION_IMPL_NAME(irq_remove_handler)(uint num, irq_handler_t handler) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_set_priority)
+void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_priority)(uint num, uint8_t hardware_priority) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_get_priority)
+uint PICO_WEAK_FUNCTION_IMPL_NAME(irq_get_priority)(uint num) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_clear)
+void PICO_WEAK_FUNCTION_IMPL_NAME(irq_clear)(uint int_num) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(irq_init_priorities)
+void PICO_WEAK_FUNCTION_IMPL_NAME(irq_init_priorities)() {
+}
+
+static uint get_user_irq_claim_index(uint irq_num) {
+    invalid_params_if(HARDWARE_IRQ, irq_num < FIRST_USER_IRQ || irq_num >= NUM_IRQS);
+    // we count backwards from the last, to match the existing hard coded uses of user IRQs in the SDK which were previously using 31
+    static_assert(NUM_IRQS - FIRST_USER_IRQ <= 8, ""); // we only use a single byte's worth of claim bits today.
+    return NUM_IRQS - irq_num  - 1u;
+}
+
+PICO_WEAK_FUNCTION_DEF(user_irq_claim)
+void PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_claim)(uint irq_num) {
+    hw_claim_or_assert(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num), "User IRQ is already claimed");
+}
+
+PICO_WEAK_FUNCTION_DEF(user_irq_unclaim)
+void PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_unclaim)(uint irq_num) {
+    hw_claim_clear(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num));
+}
+
+PICO_WEAK_FUNCTION_DEF(user_irq_claim_unused)
+int PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_claim_unused)(bool required) {
+    int bit = hw_claim_unused_from_range(user_irq_claimed_ptr(), required, 0, NUM_USER_IRQS - 1, "No user IRQs are available");
+    if (bit >= 0) bit =  (int)NUM_IRQS - bit - 1;
+    return bit;
+}
+
+PICO_WEAK_FUNCTION_DEF(user_irq_is_claimed)
+bool PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_is_claimed)(uint irq_num) {
+    return hw_is_claimed(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num));
+}
--- a/lib/main/pico-sdk/host/hardware_sync/include/hardware/sync.h
+++ b/lib/main/pico-sdk/host/hardware_sync/include/hardware/sync.h
@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_SYNC_H
+#define _HARDWARE_SYNC_H
+
+#include "pico.h"
+
+#ifndef __cplusplus
+
+#if (__STDC_VERSION__ >= 201112L)
+#include <stdatomic.h>
+#else
+enum {
+    memory_order_acquire, memory_order_release
+};
+static inline void atomic_thread_fence(uint x) {}
+#endif
+
+#else
+
+#include <atomic>
+
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_ATOMIC, Spinlock ID for atomics, min=0, max=31, default=8, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_ATOMIC
+#define PICO_SPINLOCK_ID_ATOMIC 8
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_IRQ, Spinlock ID for IRQ protection, min=0, max=31, default=9, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_IRQ
+#define PICO_SPINLOCK_ID_IRQ 9
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_TIMER, Spinlock ID for Timer protection, min=0, max=31, default=10, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_TIMER
+#define PICO_SPINLOCK_ID_TIMER 10
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_HARDWARE_CLAIM, Spinlock ID for Hardware claim protection, min=0, max=31, default=11, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_HARDWARE_CLAIM
+#define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_RAND, Spinlock ID for Random Number Generator, min=0, max=31, default=12, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_RAND
+#define PICO_SPINLOCK_ID_RAND 12
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_OS1
+#define PICO_SPINLOCK_ID_OS1 14
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_OS2
+#define PICO_SPINLOCK_ID_OS2 15
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_STRIPED_FIRST
+#define PICO_SPINLOCK_ID_STRIPED_FIRST 16
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_STRIPED_LAST
+#define PICO_SPINLOCK_ID_STRIPED_LAST 23
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST
+#define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24
+#endif
+
+#ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END
+#warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_LAST, Highest Spinlock ID in the 'claim free' range, min=0, max=31, default=31, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_LAST
+#define PICO_SPINLOCK_ID_CLAIM_FREE_LAST 31
+#endif
+
+typedef struct _spin_lock_t spin_lock_t;
+
+inline static void __mem_fence_acquire() {
+#ifndef __cplusplus
+    atomic_thread_fence(memory_order_acquire);
+#else
+    std::atomic_thread_fence(std::memory_order_acquire);
+#endif
+}
+
+inline static void __mem_fence_release() {
+#ifndef __cplusplus
+    atomic_thread_fence(memory_order_release);
+#else
+    std::atomic_thread_fence(std::memory_order_release);
+#endif
+}
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void __sev();
+
+void __wev();
+
+void __wfi();
+
+void __wfe();
+
+uint32_t save_and_disable_interrupts();
+
+void restore_interrupts(uint32_t status);
+
+void restore_interrupts_from_disabled(uint32_t status);
+
+uint spin_lock_get_num(spin_lock_t *lock);
+
+spin_lock_t *spin_lock_instance(uint lock_num);
+
+void spin_lock_unsafe_blocking(spin_lock_t *lock);
+
+void spin_unlock_unsafe(spin_lock_t *lock);
+
+uint32_t spin_lock_blocking(spin_lock_t *lock);
+
+bool is_spin_locked(const spin_lock_t *lock);
+
+void spin_unlock(spin_lock_t *lock, uint32_t saved_irq);
+
+spin_lock_t *spin_lock_init(uint lock_num);
+
+void clear_spin_locks(void);
+#define spin_locks_reset() clear_spin_locks()
+
+uint next_striped_spin_lock_num();
+
+void spin_lock_claim(uint lock_num);
+void spin_lock_claim_mask(uint32_t lock_num_mask);
+void spin_lock_unclaim(uint lock_num);
+int spin_lock_claim_unused(bool required);
+uint spin_lock_num(spin_lock_t *lock);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/lib/main/pico-sdk/host/hardware_sync/sync_core0_only.c
+++ b/lib/main/pico-sdk/host/hardware_sync/sync_core0_only.c
@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/sync.h"
+#include "hardware/platform_defs.h"
+
+// This is a dummy implementation that is single threaded
+
+static struct _spin_lock_t {
+    bool locked;
+} _spinlocks[NUM_SPIN_LOCKS];
+
+PICO_WEAK_FUNCTION_DEF(save_and_disable_interrupts)
+
+//static uint8_t striped_spin_lock_num;
+
+uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(save_and_disable_interrupts)() {
+    return 0;
+}
+
+PICO_WEAK_FUNCTION_DEF(restore_interrupts)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(restore_interrupts)(uint32_t status) {
+}
+
+PICO_WEAK_FUNCTION_DEF(restore_interrupts_from_disabled)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(restore_interrupts_from_disabled)(uint32_t status) {
+}
+
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_instance)
+
+spin_lock_t *PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_instance)(uint lock_num) {
+    assert(lock_num < NUM_SPIN_LOCKS);
+    return &_spinlocks[lock_num];
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_get_num)
+
+uint PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_get_num)(spin_lock_t *lock) {
+    return lock - _spinlocks;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_init)
+
+spin_lock_t *PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_init)(uint lock_num) {
+    spin_lock_t *lock = spin_lock_instance(lock_num);
+    spin_unlock_unsafe(lock);
+    return lock;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_unsafe_blocking)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_unsafe_blocking)(spin_lock_t *lock) {
+    lock->locked = true;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_blocking)
+
+uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_blocking)(spin_lock_t *lock) {
+    spin_lock_unsafe_blocking(lock);
+    return 1; // todo wrong value
+}
+
+PICO_WEAK_FUNCTION_DEF(is_spin_locked)
+
+bool PICO_WEAK_FUNCTION_IMPL_NAME(is_spin_locked)(const spin_lock_t *lock) {
+    return lock->locked;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_unlock_unsafe)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_unlock_unsafe)(spin_lock_t *lock) {
+    lock->locked = false;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_unlock)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_unlock)(spin_lock_t *lock, uint32_t saved_irq) {
+    spin_unlock_unsafe(lock);
+}
+
+PICO_WEAK_FUNCTION_DEF(__sev)
+
+volatile bool event_fired;
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(__sev)() {
+    event_fired = true;
+}
+
+PICO_WEAK_FUNCTION_DEF(__wfi)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(__wfi)() {
+    panic("Can't wait on irq for host core0 only implementation");
+}
+
+PICO_WEAK_FUNCTION_DEF(__wfe)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(__wfe)() {
+    while (!event_fired) tight_loop_contents();
+}
+
+PICO_WEAK_FUNCTION_DEF(clear_spin_locks)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(clear_spin_locks)(void) {
+    for (uint i = 0; i < NUM_SPIN_LOCKS; i++) {
+        spin_unlock_unsafe(spin_lock_instance(i));
+    }
+}
+
+PICO_WEAK_FUNCTION_DEF(next_striped_spin_lock_num)
+uint PICO_WEAK_FUNCTION_IMPL_NAME(next_striped_spin_lock_num)() {
+    return 0;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_claim)
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim)(uint lock_num) {
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_claim_mask)
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim_mask)(uint32_t mask) {
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_unclaim)
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_unclaim)(uint lock_num) {
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_claim_unused)
+int PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim_unused)(bool required) {
+    return 0;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_num)
+uint PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_num)(spin_lock_t *lock) {
+    return 0;
+}
--- a/lib/main/pico-sdk/host/hardware_timer/include/hardware/timer.h
+++ b/lib/main/pico-sdk/host/hardware_timer/include/hardware/timer.h
@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_TIMER_H
+#define _HARDWARE_TIMER_H
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER, Enable/disable assertions in the hardware_timer module, type=bool, default=0, group=hardware_timer
+#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER
+#ifdef PARAM_ASSERTIONS_ENABLED_TIMER // backwards compatibility with SDK < 2.0.0
+#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER PARAM_ASSERTIONS_ENABLED_TIMER
+#else
+#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER 0
+#endif
+#endif
+
+static inline void check_hardware_alarm_num_param(uint alarm_num) {
+    invalid_params_if(HARDWARE_TIMER, alarm_num >= NUM_ALARMS);
+}
+
+uint32_t time_us_32();
+uint64_t time_us_64();
+void busy_wait_us_32(uint32_t delay_us);
+void busy_wait_us(uint64_t delay_us);
+void busy_wait_ms(uint32_t delay_m);
+void busy_wait_until(absolute_time_t t);
+bool time_reached(absolute_time_t t);
+typedef void (*hardware_alarm_callback_t)(uint alarm_num);
+void hardware_alarm_claim(uint alarm_num);
+void hardware_alarm_unclaim(uint alarm_num);
+int hardware_alarm_claim_unused(bool required);
+void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback);
+bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t);
+void hardware_alarm_cancel(uint alarm_num);
+void hardware_alarm_force_irq(uint alarm_num);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/lib/main/pico-sdk/host/hardware_timer/timer.c
+++ b/lib/main/pico-sdk/host/hardware_timer/timer.c
@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/timer.h"
+#if defined(__unix__) || defined(__APPLE__)
+#include <unistd.h>
+#include <sys/time.h>
+#include <time.h>
+
+#endif
+
+// in our case not a busy wait
+PICO_WEAK_FUNCTION_DEF(busy_wait_us_32)
+void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_us_32)(uint32_t delay_us) {
+#if defined(__unix__) || defined(__APPLE__)
+    usleep(delay_us);
+#else
+    assert(false);
+#endif
+}
+
+PICO_WEAK_FUNCTION_DEF(busy_wait_us)
+void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_us)(uint64_t delay_us) {
+    absolute_time_t t;
+    update_us_since_boot(&t, time_us_64() + delay_us);
+    busy_wait_until(t);
+}
+
+PICO_WEAK_FUNCTION_DEF(busy_wait_ms)
+void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_ms)(uint32_t delay_ms) {
+#if defined(__unix__) || defined(__APPLE__)
+    usleep(delay_ms * 1000);
+#else
+    assert(false);
+#endif
+}
+
+// this may or may not wrap
+PICO_WEAK_FUNCTION_DEF(time_us_64)
+uint64_t PICO_WEAK_FUNCTION_IMPL_NAME(time_us_64)() {
+#if defined(__unix__) || defined(__APPLE__)
+//    struct timeval tv;
+//    gettimeofday(&tv, NULL);
+//    return tv.tv_sec * (uint64_t) 1000000 + tv.tv_usec;
+    struct timespec ts;
+    clock_gettime(CLOCK_MONOTONIC, &ts);
+    return ts.tv_sec * (uint64_t) 1000000 + ts.tv_nsec / 1000;
+#else
+    panic_unsupported();
+#endif
+}
+
+PICO_WEAK_FUNCTION_DEF(timer_us_32)
+uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(timer_us_32)() {
+    return (uint32_t) time_us_64();
+}
+
+PICO_WEAK_FUNCTION_DEF(time_reached)
+bool PICO_WEAK_FUNCTION_IMPL_NAME(time_reached)(absolute_time_t t) {
+    uint64_t target = to_us_since_boot(t);
+    return time_us_64() >= target;
+}
+
+PICO_WEAK_FUNCTION_DEF(busy_wait_until)
+void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_until)(absolute_time_t target) {
+#if defined(__unix__)
+    struct timespec tspec;
+    tspec.tv_sec = to_us_since_boot(target) / 1000000;
+    tspec.tv_nsec = (to_us_since_boot(target) % 1000000) * 1000;
+    clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &tspec, NULL);
+#else
+    const int chunk = 1u<<30u;
+    uint64_t target_us = to_us_since_boot(target);
+    uint64_t time_us = time_us_64();
+    while ((int64_t)(target_us - time_us) >= chunk) {
+        busy_wait_us_32(chunk);
+        time_us = time_us_64();
+    }
+    if (target_us > time_us) {
+        busy_wait_us_32(target_us - time_us);
+    }
+#endif
+}
+
+static uint8_t claimed_alarms;
+
+void hardware_alarm_claim(uint alarm_num) {
+    assert(!(claimed_alarms & (1u << alarm_num)));
+    claimed_alarms |= 1u <<alarm_num;
+}
+
+void hardware_alarm_unclaim(uint alarm_num) {
+    assert(claimed_alarms & (1u << alarm_num));
+    claimed_alarms &= ~(1u <<alarm_num);
+}
+
+int hardware_alarm_claim_unused(bool required) {
+    int alarm_id = claimed_alarms ? __builtin_clz(~claimed_alarms) : 1;
+    if (alarm_id >= NUM_ALARMS) return -1;
+    claimed_alarms |= 1u << alarm_id;
+    return alarm_id;
+}
+
+PICO_WEAK_FUNCTION_DEF(hardware_alarm_set_callback)
+void PICO_WEAK_FUNCTION_IMPL_NAME(hardware_alarm_set_callback)(uint alarm_num, hardware_alarm_callback_t callback) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(hardware_alarm_set_target)
+bool PICO_WEAK_FUNCTION_IMPL_NAME(hardware_alarm_set_target)(uint alarm_num, absolute_time_t target) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(hardware_alarm_cancel)
+void PICO_WEAK_FUNCTION_IMPL_NAME(hardware_alarm_cancel)(uint alarm_num) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(hardware_alarm_force_irq)
+void PICO_WEAK_FUNCTION_IMPL_NAME(hardware_alarm_force_irq)(uint alarm_num) {
+    panic_unsupported();
+}
--- a/lib/main/pico-sdk/host/hardware_uart/include/hardware/uart.h
+++ b/lib/main/pico-sdk/host/hardware_uart/include/hardware/uart.h
@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_UART_H
+#define _HARDWARE_UART_H
+
+#include "pico.h"
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_UART, Enable/disable assertions in the hardware_uart module, type=bool, default=0, group=hardware_uart
+#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_UART
+#ifdef PARAM_ASSERTIONS_ENABLED_UART // backwards compatibility with SDK < 2.0.0
+#define PARAM_ASSERTIONS_ENABLED_HARDWARE_UART PARAM_ASSERTIONS_ENABLED_UART
+#else
+#define PARAM_ASSERTIONS_ENABLED_HARDWARE_UART 0
+#endif
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct uart_inst uart_inst_t;
+
+extern uart_inst_t * const uart0;
+extern uart_inst_t * const uart1;
+#define uart_default uart0
+
+typedef enum {
+    UART_PARITY_NONE,
+    UART_PARITY_EVEN,
+    UART_PARITY_ODD
+} uart_parity_t;
+
+// ----------------------------------------------------------------------------
+// Setup
+
+// Put the UART into a known state, and enable it. Must be called before other
+// functions.
+uint uart_init(uart_inst_t *uart, uint baudrate);
+
+// Disable the UART if it is no longer used. Must be reinitialised before
+// being used again.
+void uart_deinit(uart_inst_t *uart);
+
+// Set baud rate as close as possible to requested, and return actual rate.
+uint uart_set_baudrate(uart_inst_t *uart, uint baudrate);
+
+// cts: enable flow control of TX by clear-to-send input
+// rts: enable assertion of request-to-send output by RX flow control
+void uart_set_hw_flow(uart_inst_t *uart, bool cts, bool rts);
+
+// Configure how the UART serialises and deserialises data on the wire
+void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity);
+
+// Enable the UART's interrupt output. Need to install an interrupt handler first.
+void uart_set_irqs_enabled(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data);
+
+// ----------------------------------------------------------------------------
+// Generic input/output
+
+// If returns 0, no space is available in the UART to write more data.
+// If returns nonzero, at least that many bytes can be written without blocking.
+bool uart_is_writable(uart_inst_t *uart);
+
+// If returns 0, no data is available to be read from UART.
+// If returns nonzero, at least that many bytes can be written without blocking.
+bool uart_is_readable(uart_inst_t *uart);
+
+// Write len bytes directly from src to the UART
+void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len);
+
+// Read len bytes directly from the UART to dst
+void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len);
+
+// ----------------------------------------------------------------------------
+// UART-specific operations and aliases
+
+void uart_putc(uart_inst_t *uart, char c);
+
+void uart_putc_raw(uart_inst_t *uart, char c);
+
+void uart_puts(uart_inst_t *uart, const char *s);
+
+char uart_getc(uart_inst_t *uart);
+
+// en: assert break condition (TX held low) if true. Clear break condition if false.
+void uart_set_break(uart_inst_t *uart, bool en);
+
+void uart_default_tx_wait_blocking();
+
+#define UART_FUNCSEL_NUM(uart, gpio) 0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/lib/main/pico-sdk/host/hardware_uart/uart.c
+++ b/lib/main/pico-sdk/host/hardware_uart/uart.c
@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include "hardware/uart.h"
+
+#if defined(__unix) || defined(__APPLE__)
+#define _XOPEN_SOURCE 600 /* for ONLCR */
+#define __BSD_VISIBLE 1 /* for ONLCR in *BSD */
+
+#include <unistd.h>
+#include <termios.h>
+#include <fcntl.h>
+#include <stdlib.h>
+
+#ifndef FNONBLOCK
+#define FNONBLOCK O_NONBLOCK
+#endif
+
+struct termios _tty;
+static tcflag_t _res_oflg = 0;
+static tcflag_t _res_lflg = 0;
+
+void _resettty(void) {
+    if (!isatty(STDIN_FILENO))
+        return;
+
+    /* reset tty: */
+    _tty.c_oflag = _res_oflg;
+    _tty.c_lflag = _res_lflg;
+    tcsetattr(STDIN_FILENO, TCSADRAIN, &_tty);
+}
+
+void _inittty(void) {
+    if (!isatty(STDIN_FILENO))
+        return;
+
+    /* save tty: */
+    tcgetattr(STDIN_FILENO, &_tty);
+    _res_oflg = _tty.c_oflag;
+    _res_lflg = _tty.c_lflag;
+
+    /* set raw: */
+    _tty.c_lflag &= ~(ICANON | ICRNL);// | ISIG);
+    //_tty.c_oflag &= ~ONLCR;
+    tcsetattr(STDIN_FILENO, TCSANOW, &_tty);
+
+    fcntl(STDIN_FILENO, F_SETFL, FNONBLOCK);
+    atexit(_resettty);
+}
+
+#else
+void _inittty() {}
+#endif
+
+typedef struct {
+    bool dummy;
+} uart_hw_t;
+
+uart_inst_t *const uart0;
+uart_inst_t *const uart1;
+
+static int _nextchar = EOF;
+
+static bool _peekchar() {
+    if (_nextchar == EOF) {
+        _nextchar = getchar();
+    }
+    return _nextchar != EOF;
+}
+
+uint uart_init(uart_inst_t *uart, uint baud_rate) {
+    _inittty();
+    return baud_rate;
+}
+
+bool uart_is_writable(uart_inst_t *uart) {
+    return 1;
+}
+
+// If returns 0, no data is available to be read from UART.
+// If returns nonzero, at least that many bytes can be written without blocking.
+bool uart_is_readable(uart_inst_t *uart) {
+    return _peekchar() ? 1 : 0;
+}
+
+// Write len bytes directly from src to the UART
+void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len) {
+    for (size_t i = 0; i < len; i++) {
+        uart_putc(uart, src[i]);
+    }
+}
+
+// Read len bytes directly from the UART to dst
+void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len) {
+    for (size_t i = 0; i < len; i++) {
+        dst[i] = uart_getc(uart);
+    }
+}
+
+// ----------------------------------------------------------------------------
+// UART-specific operations and aliases
+
+void uart_putc(uart_inst_t *uart, char c) {
+    putchar(c);
+}
+
+void uart_putc_raw(uart_inst_t *uart, char c) {
+    putchar(c);
+}
+
+void uart_puts(uart_inst_t *uart, const char *s) {
+    puts(s);
+}
+
+char uart_getc(uart_inst_t *uart) {
+    while (!_peekchar()) {
+        tight_loop_contents();
+    }
+    char rc = (char) _nextchar;
+    _nextchar = EOF;
+    return rc;
+}
+
+void uart_default_tx_wait_blocking() {
+
+}
--- a/lib/main/pico-sdk/host/pico_bit_ops/bit_ops.c
+++ b/lib/main/pico-sdk/host/pico_bit_ops/bit_ops.c
@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/bit_ops.h"
+
+uint32_t __rev(uint32_t v) {
+    v = ((v & 0x55555555u) << 1u) | ((v >> 1u) & 0x55555555u);
+    v = ((v & 0x33333333u) << 2u) | ((v >> 2u) & 0x33333333u);
+    v = ((v & 0x0f0f0f0fu) << 4u) | ((v >> 4u) & 0x0f0f0f0fu);
+    return (v << 24u) | ((v & 0xff00u) << 8u) | ((v >> 8u) & 0xff00u) | (v >> 24u);
+}
+
+uint64_t __revll(uint64_t v) {
+    v = ((v & 0x5555555555555555u) << 1u) | ((v >> 1u) & 0x5555555555555555u);
+    v = ((v & 0x3333333333333333u) << 2u) | ((v >> 2u) & 0x3333333333333333u);
+    v = ((v & 0x0f0f0f0f0f0f0f0fu) << 4u) | ((v >> 4u) & 0x0f0f0f0f0f0f0f0fu);
+    v = ((v & 0x00ff00ff00ff00ffu) << 8u) | ((v >> 8u) & 0x00ff00ff00ff00ffu);
+    return (v << 48u) | ((v & 0xffff0000u) << 16u) | ((v >> 16u) & 0xffff0000u) | (v >> 48u);
+}
--- a/lib/main/pico-sdk/host/pico_divider/divider.c
+++ b/lib/main/pico-sdk/host/pico_divider/divider.c
@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/divider.h"
+
+// These functions save/restore divider state, so are safe to call from interrupts
+int32_t div_s32s32(int32_t a, int32_t b) {
+    return hw_divider_quotient_s32(a, b);
+}
+
+divmod_result_t divmod_s32s32(int32_t a, int32_t b) {
+    return hw_divider_divmod_s32(a, b);
+}
+
+uint32_t div_u32u32(uint32_t a, uint32_t b) {
+    return hw_divider_u32_quotient(a, b);
+}
+
+divmod_result_t divmod_u32u32(uint32_t a, uint32_t b) {
+    return hw_divider_divmod_u32(a, b);
+}
+
+static inline int __sign_of_64(int32_t v) {
+    return v > 0 ? 1 : (v < 0 ? -1 : 0);
+}
+
+typedef struct {
+    uint64_t quotient;
+    uint64_t remainder;
+} qr_u64;
+
+typedef struct {
+    int64_t quotient;
+    int64_t remainder;
+} qr_s64;
+
+// divides unsigned values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0
+static inline qr_u64 udiv64(uint64_t a, uint64_t b) {
+    qr_u64 rc;
+    if (!b) {
+        rc.quotient = (uint64_t)-1; // todo check this
+        rc.remainder = a;
+    } else {
+        rc.quotient = a/b;
+        rc.remainder = a%b;
+    }
+    return rc;
+}
+
+// divides signed values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0
+static inline qr_s64 div64(int64_t a, int64_t b) {
+    qr_s64 rc;
+    if (!b) {
+        rc.quotient = (uint64_t)(-__sign_of_64(a));
+        rc.remainder = a;
+    } else {
+        rc.quotient = a/b;
+        rc.remainder = a%b;
+    }
+    return rc;
+}
+
+int64_t div_s64s64(int64_t a, int64_t b) {
+    qr_s64 qr = div64(a, b);
+    return qr.quotient;
+}
+
+int64_t divmod_s64s64_rem(int64_t a, int64_t b, int64_t *rem) {
+    qr_s64 qr = div64(a, b);
+    *rem = qr.remainder;
+    return qr.quotient;
+}
+
+int64_t divmod_s64s64(int64_t a, int64_t b) {
+    qr_s64 qr = div64(a, b);
+    return qr.quotient;
+}
+
+uint64_t div_u64u64(uint64_t a, uint64_t b) {
+    qr_u64 qr = udiv64(a, b);
+    return qr.quotient;
+}
+
+uint64_t divmod_u64u64_rem(uint64_t a, uint64_t b, uint64_t *rem) {
+    qr_u64 qr = udiv64(a, b);
+    *rem = qr.remainder;
+    return qr.quotient;
+}
+
+uint64_t divmod_u64u64(uint64_t a, uint64_t b) {
+    qr_u64 qr = udiv64(a, b);
+    return qr.quotient;
+}
+
+// these functions are slightly faster, but unsafe the divider state, so are not generally safe to be called from interrupts
+
+int32_t div_s32s32_unsafe(int32_t a, int32_t b) { return div_s32s32(a,b); }
+int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem) { return divmod_s32s32_rem(a, b, rem); }
+divmod_result_t divmod_s32s32_unsafe(int32_t a, int32_t b) { return divmod_s32s32(a, b); }
+
+uint32_t div_u32u32_unsafe(uint32_t a, uint32_t b) { return div_u32u32(a, b); }
+uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem) { return divmod_u32u32_rem(a, b, rem); }
+uint64_t divmod_u32u32_unsafe(uint32_t a, uint32_t b) { return divmod_u32u32(a, b); }
+
+int64_t div_s64s64_unsafe(int64_t a, int64_t b) { return div_s64s64(a, b); }
+int64_t divmod_s64s64_rem_unsafe(int64_t a, int64_t b, int64_t *rem) { return divmod_s64s64_rem(a, b, rem); }
+int64_t divmod_s64s64_unsafe(int64_t a, int64_t b) { return divmod_s64s64(a, b); }
+
+uint64_t div_u64u64_unsafe(uint64_t a, uint64_t b) { return div_u64u64(a, b); }
+uint64_t divmod_u64u64_rem_unsafe(uint64_t a, uint64_t b, uint64_t *rem) { return divmod_u64u64_rem(a, b, rem); }
+uint64_t divmod_u64u64_unsafe(uint64_t a, uint64_t b) { return divmod_u64u64(a, b); }
--- a/lib/main/pico-sdk/host/pico_multicore/include/pico/multicore.h
+++ b/lib/main/pico-sdk/host/pico_multicore/include/pico/multicore.h
@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_MULTICORE_H
+#define _PICO_MULTICORE_H
+
+#include "pico/types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void multicore_reset_core1(void);
+void multicore_launch_core1(void (*entry)(void));
+void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes);
+void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table);
+
+bool multicore_fifo_rvalid(void);
+bool multicore_fifo_wready(void);
+void multicore_fifo_push_blocking(uint32_t data);
+bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us);
+uint32_t multicore_fifo_pop_blocking();
+bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out);
+void multicore_fifo_drain(void);
+void multicore_fifo_clear_irq(void);
+uint32_t multicore_fifo_get_status(void);
+
+// call this from the lockout victim thread
+void multicore_lockout_victim_init(void);
+
+// start locking out the other core (it will be
+bool multicore_lockout_start_timeout_us(uint64_t timeout_us);
+void multicore_lockout_start_blocking(void);
+
+bool multicore_lockout_end_timeout_us(uint64_t timeout_us);
+void multicore_lockout_end_blocking(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/lib/main/pico-sdk/host/pico_platform/include/hardware/platform_defs.h
+++ b/lib/main/pico-sdk/host/pico_platform/include/hardware/platform_defs.h
@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PLATFORM_DEFS_H
+#define _HARDWARE_PLATFORM_DEFS_H
+
+#define NUM_CORES 2u
+
+#define NUM_DMA_CHANNELS 12u
+
+#define NUM_GENERIC_TIMERS 1u
+#define NUM_ALARMS 4u
+
+#define NUM_IRQS 32u
+
+#define NUM_SPIN_LOCKS 32u
+
+#define XOSC_HZ 12000000u
+
+#define NUM_SPIN_LOCKS 32u
+
+#define NUM_BANK0_GPIOS 30
+
+#ifndef _u
+#define _u(x) x ## u
+#endif
+
+#endif
--- a/lib/main/pico-sdk/host/pico_platform/include/pico/platform.h
+++ b/lib/main/pico-sdk/host/pico_platform/include/pico/platform.h
@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_PLATFORM_H
+#define _PICO_PLATFORM_H
+
+#include "hardware/platform_defs.h"
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __unix__
+
+#include <sys/cdefs.h>
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __not_in_flash(group)
+#define __not_in_flash_func(func) func
+#define __no_inline_not_in_flash_func(func) func
+#define __in_flash(group)
+#define __scratch_x(group)
+#define __scratch_y(group)
+
+#ifndef _MSC_VER
+#define __packed __attribute__((packed))
+#define __packed_aligned __packed __attribute((aligned))
+#else
+// MSVC requires #pragma pack which isn't compatible with a single attribute style define
+#define __packed
+#define __packed_aligned
+#endif
+
+#define __time_critical_func(x) x
+#define __after_data(group)
+
+//int running_on_fpga() { return false; }
+extern void tight_loop_contents();
+
+#ifndef __STRING
+#define __STRING(x) #x
+#endif
+
+#if !defined(_MSC_VER) || defined(__clang__)
+#ifndef __noreturn
+#define __noreturn __attribute((noreturn))
+#endif
+
+#ifndef __unused
+#define __unused __attribute__((unused))
+#endif
+
+#ifndef __noinline
+#define __noinline __attribute__((noinline))
+#endif
+
+#ifndef __aligned
+#define __aligned(x) __attribute__((aligned(x)))
+#endif
+
+#define PICO_WEAK_FUNCTION_DEF(x) _Pragma(__STRING(weak x))
+#define PICO_WEAK_FUNCTION_IMPL_NAME(x) x
+
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif
+#else
+#ifndef __noreturn
+#define __noreturn __declspec(noreturn)
+#endif
+
+#ifndef __unused
+#define __unused
+#endif
+
+#ifndef __noinline
+#define __noinline __declspec(noinline)
+#endif
+
+#ifndef __aligned
+#define __aligned(x) __declspec(align(x))
+#endif
+
+#ifndef __CONCAT
+#define __CONCAT(x,y) x ## y
+#endif
+
+#define __thread __declspec( thread )
+
+#define PICO_WEAK_FUNCTION_DEF(x) __pragma(comment(linker, __STRING(/alternatename:_##x=_##x##__weak)));
+#define PICO_WEAK_FUNCTION_IMPL_NAME(x) x ## __weak
+
+static __noreturn void __builtin_unreachable() {
+}
+
+#include <intrin.h>
+#define __builtin_clz __lzcnt
+#endif
+
+#ifndef count_of
+#define count_of(a) (sizeof(a)/sizeof((a)[0]))
+#endif
+
+#ifndef MAX
+#define MAX(a, b) ((a)>(b)?(a):(b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) ((b)>(a)?(a):(b))
+#endif
+
+// abort in our case
+void __noreturn __breakpoint();
+
+void __noreturn panic_unsupported();
+
+void __noreturn panic(const char *fmt, ...);
+
+// arggggghhhh there is a weak function called sem_init used by SDL
+#define sem_init sem_init_alternative
+
+extern uint32_t host_safe_hw_ptr_impl(uintptr_t x);
+// return a 32 bit handle for a raw ptr; DMA chaining for example embeds pointers in 32 bit values
+// which of course does not work if we're running the code natively on a 64 bit platforms. Therefore
+// we provide this macro which allows that code to provide a 64->32 bit mapping in host mode
+#define host_safe_hw_ptr(x) host_safe_hw_ptr_impl((uintptr_t)(x))
+void *decode_host_safe_hw_ptr(uint32_t ptr);
+
+#define __fast_mul(a,b) ((a)*(b))
+
+typedef unsigned int uint;
+
+static inline int32_t __mul_instruction(int32_t a,int32_t b)
+{
+    return a*b;
+}
+
+static inline void __compiler_memory_barrier(void) {
+}
+
+uint get_core_num();
+
+static inline uint __get_current_exception(void) {
+    return 0;
+
+}
+
+void busy_wait_at_least_cycles(uint32_t minimum_cycles);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/lib/main/pico-sdk/host/pico_platform/platform_base.c
+++ b/lib/main/pico-sdk/host/pico_platform/platform_base.c
@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stdarg.h>
+#include <stdio.h>
+
+#include "pico.h"
+#include "hardware/timer.h"
+
+PICO_WEAK_FUNCTION_DEF(tight_loop_contents)
+void PICO_WEAK_FUNCTION_IMPL_NAME(tight_loop_contents)() {
+
+}
+
+
+PICO_WEAK_FUNCTION_DEF(get_core_num)
+uint PICO_WEAK_FUNCTION_IMPL_NAME(get_core_num)() {
+    return 0;
+}
+
+void __noreturn panic_unsupported() {
+    panic("not supported");
+}
+
+void panic(const char *fmt, ...) {
+    va_list args;
+
+    puts("*** PANIC ***\n");
+    if (fmt) {
+        va_start(args, fmt);
+        vprintf(fmt, args);
+        va_end(args);
+    }
+
+    puts("\n");
+
+    __breakpoint();
+}
+
+void __breakpoint() {
+    #ifdef _MSC_VER
+        __debugbreak();
+    #else
+        __builtin_trap();
+    #endif
+}
+
+PICO_WEAK_FUNCTION_DEF(busy_wait_at_least_cycles)
+void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_at_least_cycles)(uint32_t cycles) {
+    // fairly arbitrary; we'll use 125Mhz as a reference
+    busy_wait_us((cycles + 124)/125);
+}
--- a/lib/main/pico-sdk/host/pico_runtime/include/pico/runtime.h
+++ b/lib/main/pico-sdk/host/pico_runtime/include/pico/runtime.h
@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_RUNTIME_H
+#define _PICO_RUNTIME_H
+
+#include "pico.h"
+
+/** \file runtime.h
+* \defgroup pico_runtime pico_runtime
+* \brief Basic runtime support for running pre-main initializers provided by other libraries
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PICO_RUNTIME_INIT_TYPE_HW                 0
+#define PICO_RUNTIME_INIT_TYPE_RUNTIME            1
+#define PICO_RUNTIME_INIT_TYPE_PER_CORE           2
+
+#ifndef PICO_RUNTIME_INIT_FUNC_FLAGS
+#define PICO_RUNTIME_INIT_FUNC_FLAGS(func, flags, priority_string1, priority_string2)
+#endif
+#define PICO_RUNTIME_INIT_FUNC_HW(func, priority_string1, priority_string2) PICO_RUNTIME_INIT_FUNC_FLAGS(func, PICO_RUNTIME_INIT_TYPE_HW, priority_string1, priority_string2)
+#define PICO_RUNTIME_INIT_FUNC_RUNTIME(func, priority_string1, priority_string2) PICO_RUNTIME_INIT_FUNC_FLAGS(func, PICO_RUNTIME_INIT_TYPE_RUNTIME, priority_string1, priority_string2)
+#define PICO_RUNTIME_INIT_FUNC_PER_CORE(func, priority_string1, priority_string2) PICO_RUNTIME_INIT_FUNC_FLAGS(func, PICO_RUNTIME_INIT_TYPE_PER_CORE, priority_string1, priority_string2)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/lib/main/pico-sdk/host/pico_runtime/include/pico/runtime_init.h
+++ b/lib/main/pico-sdk/host/pico_runtime/include/pico/runtime_init.h
@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2024 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_RUNTIME_INIT_H
+#define _PICO_RUNTIME_INIT_H
+
+#include "pico.h"
+#include "pico/runtime.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * The runtime initialization is registration based.
+ *
+ * For each step of the initialization there is a 5 digit ordinal which indicates
+ * the ordering (alphabetic increasing sort of the 5 digits) of the steps.
+ *
+ * e.g. for the step "bootrom_reset", there is:
+ *
+ * \code
+ * #ifndef PICO_RUNTIME_INIT_BOOTROM_RESET
+ * #define PICO_RUNTIME_INIT_BOOTROM_RESET   "00050"
+ * #endif
+ * \endcode
+ *
+ * The user can override the order if they wish, by redefining PICO_RUNTIME_INIT_BOOTROM_RESET
+ *
+ * For each step, the automatic initialization may be skipped by defining (in this case)
+ * PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET = 1. The user can then choose to either omit the step
+ * completely or register their own replacement initialization.
+ *
+ * The default method used to perform the initialization is provided, in case the user
+ * wishes to call it manually; in this case:
+ *
+ * \code
+ * void runtime_init_bootrom_reset(void);
+ * \endcode
+ *
+ * If PICO_RUNTIME_NO_INIT_BOOTOROM_RESET define is set (NO vs SKIP above), then the function
+ * is not defined, allowing the user to provide a replacement (and also avoiding
+ * cases where the default implementation won't compile due to missing dependencies)
+ */
+
+// must have no dependency on any other initialization code
+#define PICO_RUNTIME_INIT_EARLIEST              "00001"
+
+#define PICO_RUNTIME_INIT_LATEST                "99999"
+
+// not supported on host at, (needs custom section)
+#define PICO_RUNTIME_NO_INIT_MUTEX 1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/lib/main/pico-sdk/host/pico_runtime/runtime.c
+++ b/lib/main/pico-sdk/host/pico_runtime/runtime.c
@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/runtime.h"
+
+void __weak hard_assertion_failure(void) {
+    panic("Hard assert");
+}
--- a/lib/main/pico-sdk/host/pico_stdio/include/pico/stdio.h
+++ b/lib/main/pico-sdk/host/pico_stdio/include/pico/stdio.h
@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _PICO_STDIO_H
+#define _PICO_STDIO_H
+
+typedef struct stdio_driver stdio_driver_t;
+
+#define STDIO_ERROR -1
+#define STDIO_NO_INPUT -2
+
+static inline void stdio_usb_init() {}
+void stdio_uart_init();
+static inline void stdio_init_all() { stdio_uart_init(); }
+static inline void stdio_filter_driver(stdio_driver_t *driver) {}
+static inline void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) {}
+static inline bool stdio_usb_connected(void) { return true; }
+int getchar_timeout_us(uint32_t timeout_us);
+#define puts_raw puts
+#define putchar_raw putchar
+
+#endif
--- a/lib/main/pico-sdk/host/pico_stdio/stdio.c
+++ b/lib/main/pico-sdk/host/pico_stdio/stdio.c
@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/stdlib.h"
+#include "hardware/uart.h"
+
+int getchar_timeout_us(uint32_t timeout_us) {
+    absolute_time_t t = make_timeout_time_us(timeout_us);
+    while (!uart_is_readable(uart_default)) {
+        if (absolute_time_diff_us(t, get_absolute_time()) > 0) {
+            return STDIO_NO_INPUT;
+        }
+        sleep_ms(1);
+    }
+    return uart_getc(uart_default);
+}
+
+void stdio_uart_init() {
+    uart_init(uart_default, 0);
+}
--- a/lib/main/pico-sdk/host/pico_stdlib/stdlib.c
+++ b/lib/main/pico-sdk/host/pico_stdlib/stdlib.c
@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/stdlib.h"
+
+void setup_default_uart() {
+
+}
+
+void set_sys_clock_48mhz() {
+
+}
+
+bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, uint *postdiv2_out) {
+    *vco_out = 1000000;
+    *postdiv1_out = 0;
+    *postdiv2_out = 0;
+    return true;
+}
+
+void set_sys_clock_pll(__unused uint32_t vco_freq, __unused uint post_div1, __unused uint post_div2) {
+
+}
+
--- a/lib/main/pico-sdk/host/pico_time_adapter/include/pico/time_adapter.h
+++ b/lib/main/pico-sdk/host/pico_time_adapter/include/pico/time_adapter.h
@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2024 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_TIME_ADAPTER_H
+#define _PICO_TIME_ADAPTER_H
+
+#ifndef TA_NUM_TIMERS
+#define TA_NUM_TIMERS 1
+#endif
+
+#ifndef TA_NUM_TIMER_ALARMS
+#define TA_NUM_TIMER_ALARMS 4
+#endif
+
+void ta_clear_force_irq(alarm_pool_timer_t *timer, uint hardware_alarm_num);
+void ta_clear_irq(alarm_pool_timer_t *timer, uint hardware_alarm_num);
+void ta_force_irq(alarm_pool_timer_t *timer, uint hardware_alarm_num);
+void ta_set_timeout(alarm_pool_timer_t *timer, uint hardware_alarm_num, int64_t target);
+void ta_wakes_up_on_or_before(alarm_pool_timer_t *timer, uint alarm_num, int64_t target);
+void ta_enable_irq_handler(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void));
+void ta_disable_irq_handler(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void));
+void ta_hardware_alarm_claim(alarm_pool_timer_t *timer, uint hardware_alarm_num);
+int ta_hardware_alarm_claim_unused(alarm_pool_timer_t *timer, bool required);
+alarm_pool_timer_t *ta_from_current_irq(uint *alarm_num);
+uint ta_timer_num(alarm_pool_timer_t *timer);
+static inline uint64_t ta_time_us_64(__unused alarm_pool_timer_t *timer) {
+    return time_us_64();
+}
+alarm_pool_timer_t *ta_timer_instance(uint instance_num);
+alarm_pool_timer_t *ta_default_timer_instance(void);
+
+#endif
--- a/lib/main/pico-sdk/host/pico_time_adapter/time_adapter.c
+++ b/lib/main/pico-sdk/host/pico_time_adapter/time_adapter.c
@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2024 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/time.h"
+#include "pico/time_adapter.h"
+
+PICO_WEAK_FUNCTION_DEF(ta_clear_force_irq)
+void PICO_WEAK_FUNCTION_IMPL_NAME(ta_clear_force_irq)(alarm_pool_timer_t *timer, uint hardware_alarm_num) {
+    panic_unsupported();
+}
+PICO_WEAK_FUNCTION_DEF(ta_clear_irq)
+void PICO_WEAK_FUNCTION_IMPL_NAME(ta_clear_irq)(alarm_pool_timer_t *timer, uint hardware_alarm_num) {
+    panic_unsupported();
+}
+PICO_WEAK_FUNCTION_DEF(ta_force_irq)
+void PICO_WEAK_FUNCTION_IMPL_NAME(ta_force_irq)(alarm_pool_timer_t *timer, uint hardware_alarm_num) {
+    panic_unsupported();
+}
+PICO_WEAK_FUNCTION_DEF(ta_get_handler_hardware_alarm_num)
+int PICO_WEAK_FUNCTION_IMPL_NAME(ta_get_handler_hardware_alarm_num)() {
+    panic_unsupported();
+}
+PICO_WEAK_FUNCTION_DEF(ta_set_timeout)
+void PICO_WEAK_FUNCTION_IMPL_NAME(ta_set_timeout)(alarm_pool_timer_t *timer, uint hardware_alarm_num, int64_t target) {
+    panic_unsupported();
+}
+PICO_WEAK_FUNCTION_DEF(ta_wakes_up_on_or_before)
+void PICO_WEAK_FUNCTION_IMPL_NAME(ta_wakes_up_on_or_before)(alarm_pool_timer_t *timer, uint hardware_alarm_num, int64_t target) {
+    panic_unsupported();
+}
+PICO_WEAK_FUNCTION_DEF(ta_enable_irq_handler)
+void PICO_WEAK_FUNCTION_IMPL_NAME(ta_enable_irq_handler)(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void)) {
+    panic_unsupported();
+}
+PICO_WEAK_FUNCTION_DEF(ta_disable_irq_handler)
+void PICO_WEAK_FUNCTION_IMPL_NAME(ta_disable_irq_handler)(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void)) {
+    panic_unsupported();
+}
+PICO_WEAK_FUNCTION_DEF(ta_hardware_alarm_claim)
+void PICO_WEAK_FUNCTION_IMPL_NAME(ta_hardware_alarm_claim)(alarm_pool_timer_t *timer, uint hardware_alaram_num) {
+    panic_unsupported();
+}
+PICO_WEAK_FUNCTION_DEF(ta_hardware_alarm_claim_unused)
+int PICO_WEAK_FUNCTION_IMPL_NAME(ta_hardware_alarm_claim_unused)(alarm_pool_timer_t *timer, bool required) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(ta_from_current_irq);
+alarm_pool_timer_t *PICO_WEAK_FUNCTION_IMPL_NAME(ta_from_current_irq)(uint *alarm_num) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(ta_timer_num);
+uint ta_timer_num(alarm_pool_timer_t *timer) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(ta_timer_instance);
+alarm_pool_timer_t *ta_timer_instance(uint instance_num) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(ta_default_timer_instance);
+alarm_pool_timer_t *ta_default_timer_instance(void) {
+    panic_unsupported();
+
+}
+