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Adding RP2350 SDK and target framework (#13988)
* Adding RP2350 SDK and target framework * Spacing * Removing board definitions
This commit is contained in:
J Blackman
GitHub
parent
462cb05930
commit
2dd6f95aad
576 changed files with 435012 additions and 0 deletions
6
lib/main/pico-sdk/rp2040/README.md
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6
lib/main/pico-sdk/rp2040/README.md
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@ -0,0 +1,6 @@
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This directory contains files specific to the RP2040 hardware. It is only used when building for the RP2040 platforms i.e. `PICO_PLATFORM=rp2040`
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`hardware_regs` contains low level hardware register #defines autogenerated from the RP2040 chip definition itself.
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`hardware_structs` contains C structures for accessing memory mapped registers
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/*
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _BOOT2_HELPER_EXIT_FROM_BOOT2
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#define _BOOT2_HELPER_EXIT_FROM_BOOT2
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#include "hardware/regs/m0plus.h"
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// If entered from the bootrom, lr (which we earlier pushed) will be 0,
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// and we vector through the table at the start of the main flash image.
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// Any regular function call will have a nonzero value for lr.
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check_return:
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pop {r0}
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cmp r0, #0
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beq vector_into_flash
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bx r0
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vector_into_flash:
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ldr r0, =(XIP_BASE + 0x100)
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ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
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str r0, [r1]
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ldmia r0, {r0, r1}
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msr msp, r0
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bx r1
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#endif
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@ -0,0 +1,30 @@
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/*
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _BOOT2_HELPER_READ_FLASH_SREG
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#define _BOOT2_HELPER_READ_FLASH_SREG
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#include "boot2_helpers/wait_ssi_ready.S"
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// Pass status read cmd into r0.
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// Returns status value in r0.
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.global read_flash_sreg
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.type read_flash_sreg,%function
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.thumb_func
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read_flash_sreg:
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push {r1, lr}
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str r0, [r3, #SSI_DR0_OFFSET]
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// Dummy byte:
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str r0, [r3, #SSI_DR0_OFFSET]
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bl wait_ssi_ready
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// Discard first byte and combine the next two
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ldr r0, [r3, #SSI_DR0_OFFSET]
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ldr r0, [r3, #SSI_DR0_OFFSET]
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pop {r1, pc}
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#endif
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@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _BOOT2_HELPER_WAIT_SSI_READY
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#define _BOOT2_HELPER_WAIT_SSI_READY
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wait_ssi_ready:
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push {r0, r1, lr}
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// Command is complete when there is nothing left to send
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// (TX FIFO empty) and SSI is no longer busy (CSn deasserted)
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1:
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ldr r1, [r3, #SSI_SR_OFFSET]
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movs r0, #SSI_SR_TFE_BITS
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tst r1, r0
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beq 1b
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movs r0, #SSI_SR_BUSY_BITS
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tst r1, r0
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bne 1b
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pop {r0, r1, pc}
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#endif
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282
lib/main/pico-sdk/rp2040/boot_stage2/boot2_at25sf128a.S
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282
lib/main/pico-sdk/rp2040/boot_stage2/boot2_at25sf128a.S
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// ----------------------------------------------------------------------------
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// Second stage boot code
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// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Device: Adesto AT25SF128A
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// Based on W25Q080 code: main difference is the QE bit is being set
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// via command 0x31
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//
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// Description: Configures AT25SF128A to run in Quad I/O continuous read XIP mode
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//
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// Details: * Check status register 2 to determine if QSPI mode is enabled,
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// and perform an SR2 programming cycle if necessary.
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// * Use SSI to perform a dummy 0xEB read command, with the mode
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// continuation bits set, so that the flash will not require
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// 0xEB instruction prefix on subsequent reads.
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// * Configure SSI to write address, mode bits, but no instruction.
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// SSI + flash are now jointly in a state where continuous reads
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// can take place.
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// * Jump to exit pointer passed in via lr. Bootrom passes null,
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// in which case this code uses a default 256 byte flash offset
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//
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// Building: * This code must be position-independent, and use stack only
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// * The code will be padded to a size of 256 bytes, including a
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// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
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// ----------------------------------------------------------------------------
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#include "pico/asm_helper.S"
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#include "hardware/regs/addressmap.h"
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#include "hardware/regs/ssi.h"
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#include "hardware/regs/pads_qspi.h"
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// ----------------------------------------------------------------------------
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// Config section
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// ----------------------------------------------------------------------------
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// It should be possible to support most flash devices by modifying this section
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// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
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// This must be a positive, even integer.
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// The bootrom is very conservative with SPI frequency, but here we should be
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// as aggressive as possible.
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#ifndef PICO_FLASH_SPI_CLKDIV
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#define PICO_FLASH_SPI_CLKDIV 4
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#endif
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#if PICO_FLASH_SPI_CLKDIV & 1
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#error PICO_FLASH_SPI_CLKDIV must be even
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#endif
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// Define interface width: single/dual/quad IO
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#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
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// For W25Q080 this is the "Read data fast quad IO" instruction:
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#define CMD_READ 0xeb
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// "Mode bits" are 8 special bits sent immediately after
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// the address bits in a "Read Data Fast Quad I/O" command sequence.
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// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
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// next read does not require the 0xeb instruction prefix.
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#define MODE_CONTINUOUS_READ 0x20
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// The number of address + mode bits, divided by 4 (always 4, not function of
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// interface width).
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#define ADDR_L 8
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// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
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// are required.
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#define WAIT_CYCLES 4
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// If defined, we will read status reg, compare to SREG_DATA, and overwrite
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// with our value if the SR doesn't match.
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// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to
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// SR2 (31h cmd) as the latter command isn't supported by WX25Q080.
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// This isn't great because it will remove block protections.
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// A better solution is to use a volatile SR write if your device supports it.
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#define PROGRAM_STATUS_REG
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#define CMD_WRITE_ENABLE 0x06
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#define CMD_READ_STATUS 0x05
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#define CMD_READ_STATUS2 0x35
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#define CMD_WRITE_STATUS 0x01
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#define CMD_WRITE_STATUS2 0x31
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#define SREG_DATA 0x02 // Enable quad-SPI mode
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// ----------------------------------------------------------------------------
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// Start of 2nd Stage Boot Code
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// ----------------------------------------------------------------------------
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pico_default_asm_setup
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.section .text
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// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected
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// to continue into the binary via the vector table at 0x10000100.
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//
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// lr will be non-zero on entry if this code has been copied into RAM by user code and called
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// from there, and the boot_stage2 should just return normally.
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//
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// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used.
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regular_func _stage2_boot
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push {lr}
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// Set pad configuration:
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// - SCLK 8mA drive, no slew limiting
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// - SDx disable input Schmitt to reduce delay
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ldr r3, =PADS_QSPI_BASE
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movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS)
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str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
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ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
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movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS
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bics r0, r1
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str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
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str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
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str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
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str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
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ldr r3, =XIP_SSI_BASE
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// Disable SSI to allow further config
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movs r1, #0
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str r1, [r3, #SSI_SSIENR_OFFSET]
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// Set baud rate
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movs r1, #PICO_FLASH_SPI_CLKDIV
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str r1, [r3, #SSI_BAUDR_OFFSET]
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// Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
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// if the flash launches data on SCLK posedge, we capture it at the time that
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// the next SCLK posedge is launched. This is shortly before that posedge
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// arrives at the flash, so data hold time should be ok. For
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// PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
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movs r1, #1
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movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance
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str r1, [r3, r2]
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// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
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// (i.e. turn WPn and HOLDn into IO2/IO3)
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#ifdef PROGRAM_STATUS_REG
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program_sregs:
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#define CTRL0_SPI_TXRX \
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(7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
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(SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
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ldr r1, =(CTRL0_SPI_TXRX)
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str r1, [r3, #SSI_CTRLR0_OFFSET]
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// Enable SSI and select slave 0
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movs r1, #1
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str r1, [r3, #SSI_SSIENR_OFFSET]
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// Check whether SR needs updating
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movs r0, #CMD_READ_STATUS2
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bl read_flash_sreg
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movs r2, #SREG_DATA
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cmp r0, r2
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beq skip_sreg_programming
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// Send write enable command
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movs r1, #CMD_WRITE_ENABLE
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str r1, [r3, #SSI_DR0_OFFSET]
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// Poll for completion and discard RX
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bl wait_ssi_ready
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ldr r1, [r3, #SSI_DR0_OFFSET]
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// Send status write command followed by data bytes
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movs r1, #CMD_WRITE_STATUS2
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str r1, [r3, #SSI_DR0_OFFSET]
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str r2, [r3, #SSI_DR0_OFFSET]
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bl wait_ssi_ready
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ldr r1, [r3, #SSI_DR0_OFFSET]
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ldr r1, [r3, #SSI_DR0_OFFSET]
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ldr r1, [r3, #SSI_DR0_OFFSET]
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// Poll status register for write completion
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1:
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movs r0, #CMD_READ_STATUS
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bl read_flash_sreg
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movs r1, #1
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tst r0, r1
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bne 1b
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skip_sreg_programming:
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// Disable SSI again so that it can be reconfigured
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movs r1, #0
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str r1, [r3, #SSI_SSIENR_OFFSET]
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#endif
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// Currently the flash expects an 8 bit serial command prefix on every
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// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O
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// command, with mode bits set such that the flash will not expect a serial
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// command prefix on *subsequent* transfers. We don't care about the results
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// of the read, the important part is the mode bits.
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dummy_read:
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#define CTRLR0_ENTER_XIP \
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(FRAME_FORMAT /* Quad I/O mode */ \
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<< SSI_CTRLR0_SPI_FRF_LSB) | \
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(31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \
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(SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \
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<< SSI_CTRLR0_TMOD_LSB)
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ldr r1, =(CTRLR0_ENTER_XIP)
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str r1, [r3, #SSI_CTRLR0_OFFSET]
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movs r1, #0x0 // NDF=0 (single 32b read)
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str r1, [r3, #SSI_CTRLR1_OFFSET]
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#define SPI_CTRLR0_ENTER_XIP \
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(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \
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(WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
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(SSI_SPI_CTRLR0_INST_L_VALUE_8B \
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<< SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \
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(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \
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<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
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ldr r1, =(SPI_CTRLR0_ENTER_XIP)
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ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
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str r1, [r0]
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movs r1, #1 // Re-enable SSI
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str r1, [r3, #SSI_SSIENR_OFFSET]
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movs r1, #CMD_READ
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str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
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movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
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str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
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// Poll for completion
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bl wait_ssi_ready
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// The flash is in a state where we can blast addresses in parallel, and get
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// parallel data back. Now configure the SSI to translate XIP bus accesses
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// into QSPI transfers of this form.
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movs r1, #0
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str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
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// Note that the INST_L field is used to select what XIP data gets pushed into
|
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// the TX FIFO:
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// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD
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// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD
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configure_ssi:
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#define SPI_CTRLR0_XIP \
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(MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \
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<< SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
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(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \
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(WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
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(SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
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<< SSI_SPI_CTRLR0_INST_L_LSB) | \
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(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
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<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
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ldr r1, =(SPI_CTRLR0_XIP)
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ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
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str r1, [r0]
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movs r1, #1
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str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI
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// Bus accesses to the XIP window will now be transparently serviced by the
|
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// external flash on cache miss. We are ready to run code from flash.
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// Pull in standard exit routine
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#include "boot2_helpers/exit_from_boot2.S"
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// Common functions
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#include "boot2_helpers/wait_ssi_ready.S"
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#ifdef PROGRAM_STATUS_REG
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#include "boot2_helpers/read_flash_sreg.S"
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#endif
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.global literals
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literals:
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.ltorg
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.end
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106
lib/main/pico-sdk/rp2040/boot_stage2/boot2_generic_03h.S
Normal file
106
lib/main/pico-sdk/rp2040/boot_stage2/boot2_generic_03h.S
Normal file
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// ----------------------------------------------------------------------------
|
||||
// Second stage boot code
|
||||
// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
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//
|
||||
// Device: Anything which responds to 03h serial read command
|
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//
|
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// Details: * Configure SSI to translate each APB read into a 03h command
|
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// * 8 command clocks, 24 address clocks and 32 data clocks
|
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// * This enables you to boot from almost anything: you can pretty
|
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// much solder a potato to your PCB, or a piece of cheese
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// * The tradeoff is performance around 3x worse than QSPI XIP
|
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//
|
||||
// Building: * This code must be position-independent, and use stack only
|
||||
// * The code will be padded to a size of 256 bytes, including a
|
||||
// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include "pico/asm_helper.S"
|
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#include "hardware/regs/addressmap.h"
|
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#include "hardware/regs/ssi.h"
|
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|
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pico_default_asm_setup
|
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|
||||
// ----------------------------------------------------------------------------
|
||||
// Config section
|
||||
// ----------------------------------------------------------------------------
|
||||
// It should be possible to support most flash devices by modifying this section
|
||||
|
||||
// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
|
||||
// This must be a positive, even integer.
|
||||
// The bootrom is very conservative with SPI frequency, but here we should be
|
||||
// as aggressive as possible.
|
||||
#ifndef PICO_FLASH_SPI_CLKDIV
|
||||
#define PICO_FLASH_SPI_CLKDIV 4
|
||||
#endif
|
||||
|
||||
#define CMD_READ 0x03
|
||||
|
||||
// Value is number of address bits divided by 4
|
||||
#define ADDR_L 6
|
||||
|
||||
#define CTRLR0_XIP \
|
||||
(SSI_CTRLR0_SPI_FRF_VALUE_STD << SSI_CTRLR0_SPI_FRF_LSB) | /* Standard 1-bit SPI serial frames */ \
|
||||
(31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 clocks per data frame */ \
|
||||
(SSI_CTRLR0_TMOD_VALUE_EEPROM_READ << SSI_CTRLR0_TMOD_LSB) /* Send instr + addr, receive data */
|
||||
|
||||
#define SPI_CTRLR0_XIP \
|
||||
(CMD_READ << SSI_SPI_CTRLR0_XIP_CMD_LSB) | /* Value of instruction prefix */ \
|
||||
(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \
|
||||
(2 << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8 bit command prefix (field value is bits divided by 4) */ \
|
||||
(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) /* command and address both in serial format */
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Start of 2nd Stage Boot Code
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
.section .text
|
||||
|
||||
// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected
|
||||
// to continue into the binary via the vector table at 0x10000100.
|
||||
//
|
||||
// lr will be non-zero on entry if this code has been copied into RAM by user code and called
|
||||
// from there, and the boot_stage2 should just return normally.
|
||||
//
|
||||
// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used.
|
||||
regular_func _stage2_boot
|
||||
push {lr}
|
||||
|
||||
ldr r3, =XIP_SSI_BASE // Use as base address where possible
|
||||
|
||||
// Disable SSI to allow further config
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
// Set baud rate
|
||||
movs r1, #PICO_FLASH_SPI_CLKDIV
|
||||
str r1, [r3, #SSI_BAUDR_OFFSET]
|
||||
|
||||
ldr r1, =(CTRLR0_XIP)
|
||||
str r1, [r3, #SSI_CTRLR0_OFFSET]
|
||||
|
||||
ldr r1, =(SPI_CTRLR0_XIP)
|
||||
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
|
||||
str r1, [r0]
|
||||
|
||||
// NDF=0 (single 32b read)
|
||||
movs r1, #0x0
|
||||
str r1, [r3, #SSI_CTRLR1_OFFSET]
|
||||
|
||||
// Re-enable SSI
|
||||
movs r1, #1
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
// We are now in XIP mode. Any bus accesses to the XIP address window will be
|
||||
// translated by the SSI into 03h read commands to the external flash (if cache is missed),
|
||||
// and the data will be returned to the bus.
|
||||
|
||||
// Pull in standard exit routine
|
||||
#include "boot2_helpers/exit_from_boot2.S"
|
||||
|
||||
.global literals
|
||||
literals:
|
||||
.ltorg
|
||||
|
||||
.end
|
||||
264
lib/main/pico-sdk/rp2040/boot_stage2/boot2_is25lp080.S
Normal file
264
lib/main/pico-sdk/rp2040/boot_stage2/boot2_is25lp080.S
Normal file
|
|
@ -0,0 +1,264 @@
|
|||
// ----------------------------------------------------------------------------
|
||||
// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
//
|
||||
// Device: ISSI IS25LP080D
|
||||
// Based on W25Q080 code: main difference is the QE bit being in
|
||||
// SR1 instead of SR2.
|
||||
//
|
||||
// Description: Configures IS25LP080D to run in Quad I/O continuous read XIP mode
|
||||
//
|
||||
// Details: * Check status register to determine if QSPI mode is enabled,
|
||||
// and perform an SR programming cycle if necessary.
|
||||
// * Use SSI to perform a dummy 0xEB read command, with the mode
|
||||
// continuation bits set, so that the flash will not require
|
||||
// 0xEB instruction prefix on subsequent reads.
|
||||
// * Configure SSI to write address, mode bits, but no instruction.
|
||||
// SSI + flash are now jointly in a state where continuous reads
|
||||
// can take place.
|
||||
// * Set VTOR = 0x10000100 (user vector table immediately after
|
||||
// this boot2 image).
|
||||
// * Read stack pointer (MSP) and reset vector from the flash
|
||||
// vector table; set SP and jump, as though the processor had
|
||||
// booted directly from flash.
|
||||
//
|
||||
// Building: * This code must be linked to run at 0x20027f00
|
||||
// * The code will be padded to a size of 256 bytes, including a
|
||||
// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include "pico/asm_helper.S"
|
||||
#include "hardware/regs/addressmap.h"
|
||||
#include "hardware/regs/ssi.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Config section
|
||||
// ----------------------------------------------------------------------------
|
||||
// It should be possible to support most flash devices by modifying this section
|
||||
|
||||
// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
|
||||
// This must be a positive, even integer.
|
||||
// The bootrom is very conservative with SPI frequency, but here we should be
|
||||
// as aggressive as possible.
|
||||
#ifndef PICO_FLASH_SPI_CLKDIV
|
||||
#define PICO_FLASH_SPI_CLKDIV 4
|
||||
#endif
|
||||
|
||||
|
||||
// Define interface width: single/dual/quad IO
|
||||
#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
|
||||
|
||||
// For W25Q080 this is the "Read data fast quad IO" instruction:
|
||||
#define CMD_READ 0xeb
|
||||
|
||||
// "Mode bits" are 8 special bits sent immediately after
|
||||
// the address bits in a "Read Data Fast Quad I/O" command sequence.
|
||||
// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
|
||||
// next read does not require the 0xeb instruction prefix.
|
||||
#define MODE_CONTINUOUS_READ 0xa0
|
||||
|
||||
// The number of address + mode bits, divided by 4 (always 4, not function of
|
||||
// interface width).
|
||||
#define ADDR_L 8
|
||||
|
||||
// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
|
||||
// are required.
|
||||
#define WAIT_CYCLES 4
|
||||
|
||||
// If defined, we will read status reg, compare to SREG_DATA, and overwrite
|
||||
// with our value if the SR doesn't match.
|
||||
// This isn't great because it will remove block protections.
|
||||
// A better solution is to use a volatile SR write if your device supports it.
|
||||
#define PROGRAM_STATUS_REG
|
||||
|
||||
#define CMD_WRITE_ENABLE 0x06
|
||||
#define CMD_READ_STATUS 0x05
|
||||
#define CMD_WRITE_STATUS 0x01
|
||||
#define SREG_DATA 0x40 // Enable quad-SPI mode
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Start of 2nd Stage Boot Code
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
pico_default_asm_setup
|
||||
|
||||
.section .text
|
||||
// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected
|
||||
// to continue into the binary via the vector table at 0x10000100.
|
||||
//
|
||||
// lr will be non-zero on entry if this code has been copied into RAM by user code and called
|
||||
// from there, and the boot_stage2 should just return normally.
|
||||
//
|
||||
// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used.
|
||||
regular_func _stage2_boot
|
||||
push {lr}
|
||||
|
||||
ldr r3, =XIP_SSI_BASE // Use as base address where possible
|
||||
|
||||
// Disable SSI to allow further config
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
// Set baud rate
|
||||
movs r1, #PICO_FLASH_SPI_CLKDIV
|
||||
str r1, [r3, #SSI_BAUDR_OFFSET]
|
||||
|
||||
// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
|
||||
// (i.e. turn WPn and HOLDn into IO2/IO3)
|
||||
#ifdef PROGRAM_STATUS_REG
|
||||
program_sregs:
|
||||
#define CTRL0_SPI_TXRX \
|
||||
(7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
|
||||
(SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
|
||||
|
||||
ldr r1, =(CTRL0_SPI_TXRX)
|
||||
str r1, [r3, #SSI_CTRLR0_OFFSET]
|
||||
|
||||
// Enable SSI and select slave 0
|
||||
movs r1, #1
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
// Check whether SR needs updating
|
||||
ldr r0, =CMD_READ_STATUS
|
||||
bl read_flash_sreg
|
||||
ldr r2, =SREG_DATA
|
||||
cmp r0, r2
|
||||
beq skip_sreg_programming
|
||||
|
||||
// Send write enable command
|
||||
movs r1, #CMD_WRITE_ENABLE
|
||||
str r1, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
// Poll for completion and discard RX
|
||||
bl wait_ssi_ready
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
// Send status write command followed by data bytes
|
||||
movs r1, #CMD_WRITE_STATUS
|
||||
str r1, [r3, #SSI_DR0_OFFSET]
|
||||
movs r0, #0
|
||||
str r2, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
bl wait_ssi_ready
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
// Poll status register for write completion
|
||||
1:
|
||||
ldr r0, =CMD_READ_STATUS
|
||||
bl read_flash_sreg
|
||||
movs r1, #1
|
||||
tst r0, r1
|
||||
bne 1b
|
||||
|
||||
skip_sreg_programming:
|
||||
|
||||
// Send a 0xA3 high-performance-mode instruction
|
||||
// ldr r1, =0xa3
|
||||
// str r1, [r3, #SSI_DR0_OFFSET]
|
||||
// bl wait_ssi_ready
|
||||
|
||||
// Disable SSI again so that it can be reconfigured
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
#endif
|
||||
|
||||
|
||||
// First we need to send the initial command to get us in to Fast Read Quad I/O
|
||||
// mode. As this transaction requires a command, we can't send it in XIP mode.
|
||||
// To enter Continuous Read mode as well we need to append 4'b0010 to the address
|
||||
// bits and then add a further 4 don't care bits. We will construct this by
|
||||
// specifying a 28-bit address, with the least significant bits being 4'b0010.
|
||||
// This is just a dummy transaction so we'll perform a read from address zero
|
||||
// and then discard what comes back. All we really care about is that at the
|
||||
// end of the transaction, the flash device is in Continuous Read mode
|
||||
// and from then on will only expect to receive addresses.
|
||||
dummy_read:
|
||||
#define CTRLR0_ENTER_XIP \
|
||||
(FRAME_FORMAT /* Quad I/O mode */ \
|
||||
<< SSI_CTRLR0_SPI_FRF_LSB) | \
|
||||
(31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \
|
||||
(SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \
|
||||
<< SSI_CTRLR0_TMOD_LSB)
|
||||
|
||||
ldr r1, =(CTRLR0_ENTER_XIP)
|
||||
str r1, [r3, #SSI_CTRLR0_OFFSET]
|
||||
|
||||
movs r1, #0x0 // NDF=0 (single 32b read)
|
||||
str r1, [r3, #SSI_CTRLR1_OFFSET]
|
||||
|
||||
#define SPI_CTRLR0_ENTER_XIP \
|
||||
(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \
|
||||
(WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
|
||||
(SSI_SPI_CTRLR0_INST_L_VALUE_8B \
|
||||
<< SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \
|
||||
(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \
|
||||
<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
|
||||
|
||||
ldr r1, =(SPI_CTRLR0_ENTER_XIP)
|
||||
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
|
||||
str r1, [r0]
|
||||
|
||||
movs r1, #1 // Re-enable SSI
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
movs r1, #CMD_READ
|
||||
str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
|
||||
movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
|
||||
str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
|
||||
|
||||
// Poll for completion
|
||||
bl wait_ssi_ready
|
||||
|
||||
// At this point CN# will be deasserted and the SPI clock will not be running.
|
||||
// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and
|
||||
// only expecting address bits after the next CN# assertion. So long as we
|
||||
// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address
|
||||
// then the Winbond device will remain in continuous read mode. This is the
|
||||
// ideal mode for Execute-In-Place.
|
||||
// (If we want to exit continuous read mode then we will need to switch back
|
||||
// to APM mode and generate a 28-bit address phase with the extra nibble set
|
||||
// to 4'b0000).
|
||||
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
|
||||
|
||||
// Note that the INST_L field is used to select what XIP data gets pushed into
|
||||
// the TX FIFO:
|
||||
// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD
|
||||
// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD
|
||||
configure_ssi:
|
||||
#define SPI_CTRLR0_XIP \
|
||||
(MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \
|
||||
<< SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
|
||||
(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \
|
||||
(WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
|
||||
(SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
|
||||
<< SSI_SPI_CTRLR0_INST_L_LSB) | \
|
||||
(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
|
||||
<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
|
||||
|
||||
ldr r1, =(SPI_CTRLR0_XIP)
|
||||
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
|
||||
str r1, [r0]
|
||||
|
||||
movs r1, #1
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI
|
||||
|
||||
// We are now in XIP mode, with all transactions using Dual I/O and only
|
||||
// needing to send 24-bit addresses (plus mode bits) for each read transaction.
|
||||
|
||||
// Pull in standard exit routine
|
||||
#include "boot2_helpers/exit_from_boot2.S"
|
||||
|
||||
// Common functions
|
||||
#include "boot2_helpers/wait_ssi_ready.S"
|
||||
#ifdef PROGRAM_STATUS_REG
|
||||
#include "boot2_helpers/read_flash_sreg.S"
|
||||
#endif
|
||||
|
||||
.global literals
|
||||
literals:
|
||||
.ltorg
|
||||
|
||||
.end
|
||||
50
lib/main/pico-sdk/rp2040/boot_stage2/boot2_usb_blinky.S
Normal file
50
lib/main/pico-sdk/rp2040/boot_stage2/boot2_usb_blinky.S
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "pico/asm_helper.S"
|
||||
|
||||
// Stub second stage which calls into USB bootcode, with parameters.
|
||||
// USB boot takes two parameters:
|
||||
// - A GPIO mask for activity LED -- if mask is 0, don't touch GPIOs at all
|
||||
// - A mask of interfaces to disable. Bit 0 disables MSC, bit 1 disables PICOBoot
|
||||
// The bootrom passes 0 for both of these parameters, but user code (or this
|
||||
// second stage) can pass anything.
|
||||
|
||||
#define USB_BOOT_MSD_AND_PICOBOOT 0x0
|
||||
#define USB_BOOT_MSD_ONLY 0x2
|
||||
#define USB_BOOT_PICOBOOT_ONLY 0x1
|
||||
|
||||
// Config
|
||||
#define ACTIVITY_LED 0
|
||||
#define BOOT_MODE USB_BOOT_MSD_AND_PICOBOOT
|
||||
|
||||
pico_default_asm_setup
|
||||
|
||||
.section .text
|
||||
|
||||
regular_func _stage2_boot
|
||||
movs r7, #0x14 // Pointer to _well_known pointer table in ROM
|
||||
ldrh r0, [r7, #0] // Offset 0 is 16 bit pointer to function table
|
||||
ldrh r7, [r7, #4] // Offset 4 is 16 bit pointer to table lookup routine
|
||||
ldr r1, =('U' | ('B' << 8)) // Symbol for USB Boot
|
||||
blx r7
|
||||
cmp r0, #0
|
||||
beq dead
|
||||
|
||||
mov r7, r0
|
||||
ldr r0, =(1u << ACTIVITY_LED) // Mask of which GPIO (or GPIOs) to use
|
||||
movs r1, #BOOT_MODE
|
||||
blx r7
|
||||
|
||||
dead:
|
||||
wfi
|
||||
b dead
|
||||
|
||||
.global literals
|
||||
literals:
|
||||
.ltorg
|
||||
|
||||
.end
|
||||
284
lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25q080.S
Normal file
284
lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25q080.S
Normal file
|
|
@ -0,0 +1,284 @@
|
|||
// ----------------------------------------------------------------------------
|
||||
// Second stage boot code
|
||||
// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
//
|
||||
// Device: Winbond W25Q080
|
||||
// Also supports W25Q16JV (which has some different SR instructions)
|
||||
// Also supports AT25SF081
|
||||
// Also supports S25FL132K0
|
||||
//
|
||||
// Description: Configures W25Q080 to run in Quad I/O continuous read XIP mode
|
||||
//
|
||||
// Details: * Check status register 2 to determine if QSPI mode is enabled,
|
||||
// and perform an SR2 programming cycle if necessary.
|
||||
// * Use SSI to perform a dummy 0xEB read command, with the mode
|
||||
// continuation bits set, so that the flash will not require
|
||||
// 0xEB instruction prefix on subsequent reads.
|
||||
// * Configure SSI to write address, mode bits, but no instruction.
|
||||
// SSI + flash are now jointly in a state where continuous reads
|
||||
// can take place.
|
||||
// * Jump to exit pointer passed in via lr. Bootrom passes null,
|
||||
// in which case this code uses a default 256 byte flash offset
|
||||
//
|
||||
// Building: * This code must be position-independent, and use stack only
|
||||
// * The code will be padded to a size of 256 bytes, including a
|
||||
// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include "pico/asm_helper.S"
|
||||
#include "hardware/regs/addressmap.h"
|
||||
#include "hardware/regs/ssi.h"
|
||||
#include "hardware/regs/pads_qspi.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Config section
|
||||
// ----------------------------------------------------------------------------
|
||||
// It should be possible to support most flash devices by modifying this section
|
||||
|
||||
// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
|
||||
// This must be a positive, even integer.
|
||||
// The bootrom is very conservative with SPI frequency, but here we should be
|
||||
// as aggressive as possible.
|
||||
|
||||
#ifndef PICO_FLASH_SPI_CLKDIV
|
||||
#define PICO_FLASH_SPI_CLKDIV 4
|
||||
#endif
|
||||
#if PICO_FLASH_SPI_CLKDIV & 1
|
||||
#error PICO_FLASH_SPI_CLKDIV must be even
|
||||
#endif
|
||||
|
||||
// Define interface width: single/dual/quad IO
|
||||
#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
|
||||
|
||||
// For W25Q080 this is the "Read data fast quad IO" instruction:
|
||||
#define CMD_READ 0xeb
|
||||
|
||||
// "Mode bits" are 8 special bits sent immediately after
|
||||
// the address bits in a "Read Data Fast Quad I/O" command sequence.
|
||||
// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
|
||||
// next read does not require the 0xeb instruction prefix.
|
||||
#define MODE_CONTINUOUS_READ 0xa0
|
||||
|
||||
// The number of address + mode bits, divided by 4 (always 4, not function of
|
||||
// interface width).
|
||||
#define ADDR_L 8
|
||||
|
||||
// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
|
||||
// are required.
|
||||
#define WAIT_CYCLES 4
|
||||
|
||||
// If defined, we will read status reg, compare to SREG_DATA, and overwrite
|
||||
// with our value if the SR doesn't match.
|
||||
// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to
|
||||
// SR2 (31h cmd) as the latter command isn't supported by WX25Q080.
|
||||
// This isn't great because it will remove block protections.
|
||||
// A better solution is to use a volatile SR write if your device supports it.
|
||||
#define PROGRAM_STATUS_REG
|
||||
|
||||
#define CMD_WRITE_ENABLE 0x06
|
||||
#define CMD_READ_STATUS 0x05
|
||||
#define CMD_READ_STATUS2 0x35
|
||||
#define CMD_WRITE_STATUS 0x01
|
||||
#define SREG_DATA 0x02 // Enable quad-SPI mode
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Start of 2nd Stage Boot Code
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
pico_default_asm_setup
|
||||
|
||||
.section .text
|
||||
|
||||
// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected
|
||||
// to continue into the binary via the vector table at 0x10000100.
|
||||
//
|
||||
// lr will be non-zero on entry if this code has been copied into RAM by user code and called
|
||||
// from there, and the boot_stage2 should just return normally.
|
||||
//
|
||||
// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used.
|
||||
regular_func _stage2_boot
|
||||
push {lr}
|
||||
|
||||
// Set pad configuration:
|
||||
// - SCLK 8mA drive, no slew limiting
|
||||
// - SDx disable input Schmitt to reduce delay
|
||||
|
||||
ldr r3, =PADS_QSPI_BASE
|
||||
movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS)
|
||||
str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
|
||||
ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
|
||||
movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS
|
||||
bics r0, r1
|
||||
str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
|
||||
str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
|
||||
str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
|
||||
str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
|
||||
|
||||
ldr r3, =XIP_SSI_BASE
|
||||
|
||||
// Disable SSI to allow further config
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
// Set baud rate
|
||||
movs r1, #PICO_FLASH_SPI_CLKDIV
|
||||
str r1, [r3, #SSI_BAUDR_OFFSET]
|
||||
|
||||
// Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
|
||||
// if the flash launches data on SCLK posedge, we capture it at the time that
|
||||
// the next SCLK posedge is launched. This is shortly before that posedge
|
||||
// arrives at the flash, so data hold time should be ok. For
|
||||
// PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
|
||||
|
||||
movs r1, #1
|
||||
movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance
|
||||
str r1, [r3, r2]
|
||||
|
||||
|
||||
// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
|
||||
// (i.e. turn WPn and HOLDn into IO2/IO3)
|
||||
#ifdef PROGRAM_STATUS_REG
|
||||
program_sregs:
|
||||
#define CTRL0_SPI_TXRX \
|
||||
(7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
|
||||
(SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
|
||||
|
||||
ldr r1, =(CTRL0_SPI_TXRX)
|
||||
str r1, [r3, #SSI_CTRLR0_OFFSET]
|
||||
|
||||
// Enable SSI and select slave 0
|
||||
movs r1, #1
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
// Check whether SR needs updating
|
||||
movs r0, #CMD_READ_STATUS2
|
||||
bl read_flash_sreg
|
||||
movs r2, #SREG_DATA
|
||||
cmp r0, r2
|
||||
beq skip_sreg_programming
|
||||
|
||||
// Send write enable command
|
||||
movs r1, #CMD_WRITE_ENABLE
|
||||
str r1, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
// Poll for completion and discard RX
|
||||
bl wait_ssi_ready
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
// Send status write command followed by data bytes
|
||||
movs r1, #CMD_WRITE_STATUS
|
||||
str r1, [r3, #SSI_DR0_OFFSET]
|
||||
movs r0, #0
|
||||
str r0, [r3, #SSI_DR0_OFFSET]
|
||||
str r2, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
bl wait_ssi_ready
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
// Poll status register for write completion
|
||||
1:
|
||||
movs r0, #CMD_READ_STATUS
|
||||
bl read_flash_sreg
|
||||
movs r1, #1
|
||||
tst r0, r1
|
||||
bne 1b
|
||||
|
||||
skip_sreg_programming:
|
||||
|
||||
// Disable SSI again so that it can be reconfigured
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
#endif
|
||||
|
||||
// Currently the flash expects an 8 bit serial command prefix on every
|
||||
// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O
|
||||
// command, with mode bits set such that the flash will not expect a serial
|
||||
// command prefix on *subsequent* transfers. We don't care about the results
|
||||
// of the read, the important part is the mode bits.
|
||||
|
||||
dummy_read:
|
||||
#define CTRLR0_ENTER_XIP \
|
||||
(FRAME_FORMAT /* Quad I/O mode */ \
|
||||
<< SSI_CTRLR0_SPI_FRF_LSB) | \
|
||||
(31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \
|
||||
(SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \
|
||||
<< SSI_CTRLR0_TMOD_LSB)
|
||||
|
||||
ldr r1, =(CTRLR0_ENTER_XIP)
|
||||
str r1, [r3, #SSI_CTRLR0_OFFSET]
|
||||
|
||||
movs r1, #0x0 // NDF=0 (single 32b read)
|
||||
str r1, [r3, #SSI_CTRLR1_OFFSET]
|
||||
|
||||
#define SPI_CTRLR0_ENTER_XIP \
|
||||
(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \
|
||||
(WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
|
||||
(SSI_SPI_CTRLR0_INST_L_VALUE_8B \
|
||||
<< SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \
|
||||
(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \
|
||||
<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
|
||||
|
||||
ldr r1, =(SPI_CTRLR0_ENTER_XIP)
|
||||
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
|
||||
str r1, [r0]
|
||||
|
||||
movs r1, #1 // Re-enable SSI
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
movs r1, #CMD_READ
|
||||
str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
|
||||
movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
|
||||
str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
|
||||
|
||||
// Poll for completion
|
||||
bl wait_ssi_ready
|
||||
|
||||
// The flash is in a state where we can blast addresses in parallel, and get
|
||||
// parallel data back. Now configure the SSI to translate XIP bus accesses
|
||||
// into QSPI transfers of this form.
|
||||
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
|
||||
|
||||
// Note that the INST_L field is used to select what XIP data gets pushed into
|
||||
// the TX FIFO:
|
||||
// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD
|
||||
// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD
|
||||
configure_ssi:
|
||||
#define SPI_CTRLR0_XIP \
|
||||
(MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \
|
||||
<< SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
|
||||
(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \
|
||||
(WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
|
||||
(SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
|
||||
<< SSI_SPI_CTRLR0_INST_L_LSB) | \
|
||||
(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
|
||||
<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
|
||||
|
||||
ldr r1, =(SPI_CTRLR0_XIP)
|
||||
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
|
||||
str r1, [r0]
|
||||
|
||||
movs r1, #1
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI
|
||||
|
||||
// Bus accesses to the XIP window will now be transparently serviced by the
|
||||
// external flash on cache miss. We are ready to run code from flash.
|
||||
|
||||
// Pull in standard exit routine
|
||||
#include "boot2_helpers/exit_from_boot2.S"
|
||||
|
||||
// Common functions
|
||||
#include "boot2_helpers/wait_ssi_ready.S"
|
||||
#ifdef PROGRAM_STATUS_REG
|
||||
#include "boot2_helpers/read_flash_sreg.S"
|
||||
#endif
|
||||
|
||||
.global literals
|
||||
literals:
|
||||
.ltorg
|
||||
|
||||
.end
|
||||
197
lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25x10cl.S
Normal file
197
lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25x10cl.S
Normal file
|
|
@ -0,0 +1,197 @@
|
|||
// ----------------------------------------------------------------------------
|
||||
// Second stage boot code
|
||||
// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
//
|
||||
// Device: Winbond W25X10CL
|
||||
//
|
||||
// Description: Configures W25X10CL to run in Dual I/O continuous read XIP mode
|
||||
//
|
||||
// Details: * Disable SSI
|
||||
// * Configure SSI to generate 8b command + 28b address + 2 wait,
|
||||
// with address and data using dual SPI mode
|
||||
// * Enable SSI
|
||||
// * Generate dummy read with command = 0xBB, top 24b of address
|
||||
// of 0x000000 followed by M[7:0]=0010zzzz (with the HiZ being
|
||||
// generated by 2 wait cycles). This leaves the W25X10CL in
|
||||
// continuous read mode
|
||||
// * Disable SSI
|
||||
// * Configure SSI to generate 0b command + 28b address + 2 wait,
|
||||
// with the extra 4 bits of address LSB being 0x2 to keep the
|
||||
// W25X10CL in continuous read mode forever
|
||||
// * Enable SSI
|
||||
// * Set VTOR = 0x10000100
|
||||
// * Read MSP reset vector from 0x10000100 and write to MSP (this
|
||||
// will also enable XIP mode in the SSI wrapper)
|
||||
// * Read PC reset vector from 0x10000104 and jump to it
|
||||
//
|
||||
// Building: * This code must be linked to run at 0x20000000
|
||||
// * The code will be padded to a size of 256 bytes, including a
|
||||
// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include "pico/asm_helper.S"
|
||||
#include "hardware/regs/addressmap.h"
|
||||
#include "hardware/regs/ssi.h"
|
||||
|
||||
// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
|
||||
// This must be an even number.
|
||||
#ifndef PICO_FLASH_SPI_CLKDIV
|
||||
#define PICO_FLASH_SPI_CLKDIV 4
|
||||
#endif
|
||||
|
||||
pico_default_asm_setup
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// The "System Control Block" is a set of internal Cortex-M0+ control registers
|
||||
// that are memory mapped and accessed like any other H/W register. They have
|
||||
// fixed addresses in the address map of every Cortex-M0+ system.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
.equ SCB_VTOR, 0xE000ED08 // RW Vector Table Offset Register
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Winbond W25X10CL Supported Commands
|
||||
// Taken from "w25x10cl_reg_021714.pdf"
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
.equ W25X10CL_CMD_READ_DATA_FAST_DUAL_IO, 0xbb
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Winbond W25X10CL "Mode bits" are 8 special bits sent immediately after
|
||||
// the address bits in a "Read Data Fast Dual I/O" command sequence.
|
||||
// Of M[7:4], they say M[7:6] are reserved (set to zero), and bits M[3:0]
|
||||
// are don't care (we HiZ). Only M[5:4] are used, and they must be set
|
||||
// to M[5:4] = 2'b10 to enable continuous read mode.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
.equ W25X10CL_MODE_CONTINUOUS_READ, 0x20
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Start of 2nd Stage Boot Code
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
.org 0
|
||||
|
||||
.section .text
|
||||
|
||||
// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected
|
||||
// to continue into the binary via the vector table at 0x10000100.
|
||||
//
|
||||
// lr will be non-zero on entry if this code has been copied into RAM by user code and called
|
||||
// from there, and the boot_stage2 should just return normally.
|
||||
//
|
||||
// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used.
|
||||
regular_func _stage2_boot
|
||||
push {lr}
|
||||
ldr r3, =XIP_SSI_BASE // Use as base address where possible
|
||||
|
||||
// We are primarily interested in setting up Flash for DSPI XIP w/ continuous read
|
||||
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config
|
||||
|
||||
// The Boot ROM sets a very conservative SPI clock frequency to be sure it can
|
||||
// read the initial 256 bytes from any device. Here we can be more aggressive.
|
||||
|
||||
movs r1, #PICO_FLASH_SPI_CLKDIV
|
||||
str r1, [r3, #SSI_BAUDR_OFFSET] // Set SSI Clock
|
||||
|
||||
// First we need to send the initial command to get us in to Fast Read Dual I/O
|
||||
// mode. As this transaction requires a command, we can't send it in XIP mode.
|
||||
// To enter Continuous Read mode as well we need to append 4'b0010 to the address
|
||||
// bits and then add a further 4 don't care bits. We will construct this by
|
||||
// specifying a 28-bit address, with the least significant bits being 4'b0010.
|
||||
// This is just a dummy transaction so we'll perform a read from address zero
|
||||
// and then discard what comes back. All we really care about is that at the
|
||||
// end of the transaction, the Winbond W25X10CL device is in Continuous Read mode
|
||||
// and from then on will only expect to receive addresses.
|
||||
|
||||
#define CTRLR0_ENTER_XIP \
|
||||
(SSI_CTRLR0_SPI_FRF_VALUE_DUAL /* Dual I/O mode */ \
|
||||
<< SSI_CTRLR0_SPI_FRF_LSB) | \
|
||||
(31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \
|
||||
(SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \
|
||||
<< SSI_CTRLR0_TMOD_LSB)
|
||||
|
||||
ldr r1, =(CTRLR0_ENTER_XIP)
|
||||
str r1, [r3, #SSI_CTRLR0_OFFSET]
|
||||
|
||||
movs r1, #0x0 // NDF=0 (single 32b read)
|
||||
str r1, [r3, #SSI_CTRLR1_OFFSET]
|
||||
|
||||
#define SPI_CTRLR0_ENTER_XIP \
|
||||
(7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \
|
||||
(2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \
|
||||
(SSI_SPI_CTRLR0_INST_L_VALUE_8B \
|
||||
<< SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \
|
||||
(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Dual I/O mode */ \
|
||||
<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
|
||||
|
||||
ldr r1, =(SPI_CTRLR0_ENTER_XIP)
|
||||
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
|
||||
str r1, [r0]
|
||||
|
||||
movs r1, #1 // Re-enable SSI
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
movs r1, #W25X10CL_CMD_READ_DATA_FAST_DUAL_IO // 8b command = 0xBB
|
||||
str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
|
||||
movs r1, #0x0000002 // 28-bit Address for dummy read = 0x000000 + 0x2 Mode bits to set M[5:4]=10
|
||||
str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
|
||||
|
||||
// Now we wait for the read transaction to complete by monitoring the SSI
|
||||
// status register and checking for the "RX FIFO Not Empty" flag to assert.
|
||||
|
||||
movs r1, #SSI_SR_RFNE_BITS
|
||||
00:
|
||||
ldr r0, [r3, #SSI_SR_OFFSET] // Read status register
|
||||
tst r0, r1 // RFNE status flag set?
|
||||
beq 00b // If not then wait
|
||||
|
||||
// At this point CN# will be deasserted and the SPI clock will not be running.
|
||||
// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and
|
||||
// only expecting address bits after the next CN# assertion. So long as we
|
||||
// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address
|
||||
// then the Winbond device will remain in continuous read mode. This is the
|
||||
// ideal mode for Execute-In-Place.
|
||||
// (If we want to exit continuous read mode then we will need to switch back
|
||||
// to APM mode and generate a 28-bit address phase with the extra nibble set
|
||||
// to 4'b0000).
|
||||
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
|
||||
|
||||
// Note that the INST_L field is used to select what XIP data gets pushed into
|
||||
// the TX FIFO:
|
||||
// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD
|
||||
// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD
|
||||
|
||||
#define SPI_CTRLR0_XIP \
|
||||
(W25X10CL_MODE_CONTINUOUS_READ /* Mode bits to keep Winbond in continuous read mode */ \
|
||||
<< SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
|
||||
(7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \
|
||||
(2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \
|
||||
(SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
|
||||
<< SSI_SPI_CTRLR0_INST_L_LSB) | \
|
||||
(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Dual I/O mode (and Command but that is zero bits long) */ \
|
||||
<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
|
||||
|
||||
ldr r1, =(SPI_CTRLR0_XIP)
|
||||
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
|
||||
str r1, [r0]
|
||||
|
||||
movs r1, #1
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI
|
||||
|
||||
// We are now in XIP mode, with all transactions using Dual I/O and only
|
||||
// needing to send 24-bit addresses (plus mode bits) for each read transaction.
|
||||
|
||||
// Pull in standard exit routine
|
||||
#include "boot2_helpers/exit_from_boot2.S"
|
||||
|
||||
.global literals
|
||||
literals:
|
||||
.ltorg
|
||||
|
||||
.end
|
||||
13
lib/main/pico-sdk/rp2040/boot_stage2/boot_stage2.ld
Normal file
13
lib/main/pico-sdk/rp2040/boot_stage2/boot_stage2.ld
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
MEMORY {
|
||||
/* We are loaded to the top 256 bytes of SRAM, which is above the bootrom
|
||||
stack. Note 4 bytes occupied by checksum. */
|
||||
SRAM(rx) : ORIGIN = 0x20041f00, LENGTH = 252
|
||||
}
|
||||
|
||||
SECTIONS {
|
||||
. = ORIGIN(SRAM);
|
||||
.text : {
|
||||
*(.entry)
|
||||
*(.text)
|
||||
} >SRAM
|
||||
}
|
||||
19
lib/main/pico-sdk/rp2040/boot_stage2/compile_time_choice.S
Normal file
19
lib/main/pico-sdk/rp2040/boot_stage2/compile_time_choice.S
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
// ----------------------------------------------------------------------------
|
||||
// Second stage boot code
|
||||
// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// ----------------------------------------------------------------------------
|
||||
//
|
||||
// This implementation uses the PICO_BOOT_STAGE2_CHOOSE_ preprocessor defines to pick
|
||||
// amongst a menu of known boot stage 2 implementations, allowing the board
|
||||
// configuration header to be able to specify the boot stage 2
|
||||
|
||||
#include "boot_stage2/config.h"
|
||||
|
||||
#ifdef PICO_BUILD_BOOT_STAGE2_NAME
|
||||
// boot stage 2 is configured by cmake, so use the name specified there
|
||||
#error PICO_BUILD_BOOT_STAGE2_NAME should not be defined for compile_time_choice builds
|
||||
#else
|
||||
// boot stage 2 is selected by board config header, and PICO_BOOT_STAGE2_ASM is set in boot_stage2/config.h
|
||||
#include PICO_BOOT_STAGE2_ASM
|
||||
#endif
|
||||
4
lib/main/pico-sdk/rp2040/boot_stage2/doc.h
Normal file
4
lib/main/pico-sdk/rp2040/boot_stage2/doc.h
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
/**
|
||||
* \defgroup boot_stage2 boot_stage2
|
||||
* \brief Second stage boot loaders responsible for setting up external flash
|
||||
*/
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _BOOT_STAGE2_CONFIG_H
|
||||
#define _BOOT_STAGE2_CONFIG_H
|
||||
|
||||
// NOTE THIS HEADER IS INCLUDED FROM ASSEMBLY
|
||||
|
||||
#include "pico.h"
|
||||
|
||||
// PICO_CONFIG: PICO_BUILD_BOOT_STAGE2_NAME, Name of the boot stage 2 if selected in the build system, group=boot_stage2
|
||||
#ifdef PICO_BUILD_BOOT_STAGE2_NAME
|
||||
#define _BOOT_STAGE2_SELECTED
|
||||
#else
|
||||
// check that multiple boot stage 2 options haven't been set...
|
||||
|
||||
// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_IS25LP080, Select boot2_is25lp080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2
|
||||
#ifndef PICO_BOOT_STAGE2_CHOOSE_IS25LP080
|
||||
#define PICO_BOOT_STAGE2_CHOOSE_IS25LP080 0
|
||||
#elif PICO_BOOT_STAGE2_CHOOSE_IS25LP080
|
||||
#ifdef _BOOT_STAGE2_SELECTED
|
||||
#error multiple boot stage 2 options chosen
|
||||
#endif
|
||||
#define _BOOT_STAGE2_SELECTED
|
||||
#endif
|
||||
// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25Q080, Select boot2_w25q080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2
|
||||
#ifndef PICO_BOOT_STAGE2_CHOOSE_W25Q080
|
||||
#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 0
|
||||
#elif PICO_BOOT_STAGE2_CHOOSE_W25Q080
|
||||
#ifdef _BOOT_STAGE2_SELECTED
|
||||
#error multiple boot stage 2 options chosen
|
||||
#endif
|
||||
#define _BOOT_STAGE2_SELECTED
|
||||
#endif
|
||||
// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25X10CL, Select boot2_w25x10cl as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2
|
||||
#ifndef PICO_BOOT_STAGE2_CHOOSE_W25X10CL
|
||||
#define PICO_BOOT_STAGE2_CHOOSE_W25X10CL 0
|
||||
#elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL
|
||||
#ifdef _BOOT_STAGE2_SELECTED
|
||||
#error multiple boot stage 2 options chosen
|
||||
#endif
|
||||
#define _BOOT_STAGE2_SELECTED
|
||||
#endif
|
||||
// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_AT25SF128A, Select boot2_at25sf128a as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2
|
||||
#ifndef PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
|
||||
#define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 0
|
||||
#elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
|
||||
#ifdef _BOOT_STAGE2_SELECTED
|
||||
#error multiple boot stage 2 options chosen
|
||||
#endif
|
||||
#define _BOOT_STAGE2_SELECTED
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H, Select boot2_generic_03h as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=1, group=boot_stage2
|
||||
#if defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) && PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
|
||||
#ifdef _BOOT_STAGE2_SELECTED
|
||||
#error multiple boot stage 2 options chosen
|
||||
#endif
|
||||
#define _BOOT_STAGE2_SELECTED
|
||||
#endif
|
||||
|
||||
#endif // PICO_BUILD_BOOT_STAGE2_NAME
|
||||
|
||||
#ifdef PICO_BUILD_BOOT_STAGE2_NAME
|
||||
// boot stage 2 is configured by cmake, so use the name specified there
|
||||
#define PICO_BOOT_STAGE2_NAME PICO_BUILD_BOOT_STAGE2_NAME
|
||||
#else
|
||||
// boot stage 2 is selected by board config header, so we have to do some work
|
||||
#if PICO_BOOT_STAGE2_CHOOSE_IS25LP080
|
||||
#define _BOOT_STAGE2 boot2_is25lp080
|
||||
#elif PICO_BOOT_STAGE2_CHOOSE_W25Q080
|
||||
#define _BOOT_STAGE2 boot2_w25q080
|
||||
#elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL
|
||||
#define _BOOT_STAGE2 boot2_w25x10cl
|
||||
#elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
|
||||
#define _BOOT_STAGE2 boot2_at25sf128a
|
||||
#elif !defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) || PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
|
||||
#undef PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
|
||||
#define PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H 1
|
||||
#define _BOOT_STAGE2 boot2_generic_03h
|
||||
#else
|
||||
#error no boot stage 2 is defined by PICO_BOOT_STAGE2_CHOOSE_ macro
|
||||
#endif
|
||||
// we can't include cdefs in assembly, so define our own, but avoid conflict with real ones for c inclusion
|
||||
#define PICO_BOOT_STAGE2_NAME __PICO_XSTRING(_BOOT_STAGE2)
|
||||
#define PICO_BOOT_STAGE2_ASM __PICO_XSTRING(__PICO_CONCAT1(_BOOT_STAGE2,.S))
|
||||
#endif
|
||||
#endif
|
||||
55
lib/main/pico-sdk/rp2040/boot_stage2/pad_checksum
Normal file
55
lib/main/pico-sdk/rp2040/boot_stage2/pad_checksum
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import argparse
|
||||
import binascii
|
||||
import struct
|
||||
import sys
|
||||
|
||||
|
||||
def any_int(x):
|
||||
try:
|
||||
return int(x, 0)
|
||||
except:
|
||||
raise argparse.ArgumentTypeError("expected an integer, not '{!r}'".format(x))
|
||||
|
||||
|
||||
def bitrev(x, width):
|
||||
return int("{:0{w}b}".format(x, w=width)[::-1], 2)
|
||||
|
||||
|
||||
parser = argparse.ArgumentParser()
|
||||
parser.add_argument("ifile", help="Input file (binary)")
|
||||
parser.add_argument("ofile", help="Output file (assembly)")
|
||||
parser.add_argument("-p", "--pad", help="Padded size (bytes), including 4-byte checksum, default 256",
|
||||
type=any_int, default=256)
|
||||
parser.add_argument("-s", "--seed", help="Checksum seed value, default 0",
|
||||
type=any_int, default=0)
|
||||
args = parser.parse_args()
|
||||
|
||||
try:
|
||||
idata = open(args.ifile, "rb").read()
|
||||
except:
|
||||
sys.exit("Could not open input file '{}'".format(args.ifile))
|
||||
|
||||
if len(idata) > args.pad - 4:
|
||||
sys.exit("Input file size ({} bytes) too large for final size ({} bytes)".format(len(idata), args.pad))
|
||||
|
||||
idata_padded = idata + bytes(args.pad - 4 - len(idata))
|
||||
|
||||
# Our bootrom CRC32 is slightly bass-ackward but it's best to work around for now (FIXME)
|
||||
# 100% worth it to save two Thumb instructions
|
||||
checksum = bitrev(
|
||||
(binascii.crc32(bytes(bitrev(b, 8) for b in idata_padded), args.seed ^ 0xffffffff) ^ 0xffffffff) & 0xffffffff, 32)
|
||||
odata = idata_padded + struct.pack("<L", checksum)
|
||||
|
||||
try:
|
||||
with open(args.ofile, "w") as ofile:
|
||||
ofile.write("// Padded and checksummed version of: {}\n\n".format(args.ifile))
|
||||
ofile.write(".cpu cortex-m0plus\n")
|
||||
ofile.write(".thumb\n\n")
|
||||
ofile.write(".section .boot2, \"ax\"\n\n")
|
||||
for offs in range(0, len(odata), 16):
|
||||
chunk = odata[offs:min(offs + 16, len(odata))]
|
||||
ofile.write(".byte {}\n".format(", ".join("0x{:02x}".format(b) for b in chunk)))
|
||||
except:
|
||||
sys.exit("Could not open output file '{}'".format(args.ofile))
|
||||
51025
lib/main/pico-sdk/rp2040/hardware_regs/RP2040.svd
Normal file
51025
lib/main/pico-sdk/rp2040/hardware_regs/RP2040.svd
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _HARDWARE_PLATFORM_DEFS_H
|
||||
#define _HARDWARE_PLATFORM_DEFS_H
|
||||
|
||||
// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__
|
||||
|
||||
#ifndef _u
|
||||
#ifdef __ASSEMBLER__
|
||||
#define _u(x) x
|
||||
#else
|
||||
#define _u(x) x ## u
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define NUM_CORES _u(2)
|
||||
#define NUM_DMA_CHANNELS _u(12)
|
||||
#define NUM_DMA_TIMERS _u(4)
|
||||
#define NUM_DMA_IRQS _u(2)
|
||||
#define NUM_IRQS _u(32)
|
||||
#define NUM_USER_IRQS _u(6)
|
||||
#define NUM_PIOS _u(2)
|
||||
#define NUM_PIO_STATE_MACHINES _u(4)
|
||||
#define NUM_PIO_IRQS _u(2)
|
||||
#define NUM_PWM_SLICES _u(8)
|
||||
#define NUM_PWM_IRQS _u(1)
|
||||
#define NUM_SPIN_LOCKS _u(32)
|
||||
#define NUM_UARTS _u(2)
|
||||
#define NUM_I2CS _u(2)
|
||||
#define NUM_SPIS _u(2)
|
||||
#define NUM_GENERIC_TIMERS _u(1)
|
||||
#define NUM_ALARMS _u(4)
|
||||
#define ADC_BASE_PIN _u(26)
|
||||
#define NUM_ADC_CHANNELS _u(5)
|
||||
#define NUM_RESETS _u(24)
|
||||
#define NUM_BANK0_GPIOS _u(30)
|
||||
#define NUM_QSPI_GPIOS _u(6)
|
||||
|
||||
#define PIO_INSTRUCTION_COUNT _u(32)
|
||||
|
||||
#define USBCTRL_DPRAM_SIZE _u(4096)
|
||||
|
||||
#define HAS_SIO_DIVIDER 1
|
||||
#define HAS_RP2040_RTC 1
|
||||
// PICO_CONFIG: XOSC_HZ, Crystal oscillator frequency in Hz, type=int, default=12000000, advanced=true, group=hardware_base
|
||||
// NOTE: The system and USB clocks are generated from the frequency using two PLLs.
|
||||
// If you override this define, or SYS_CLK_HZ/USB_CLK_HZ below, you will *also* need to add your own adjusted PLL set-up defines to
|
||||
// override the defaults which live in src/rp2_common/hardware_clocks/include/hardware/clocks.h
|
||||
// Please see the comments there about calculating the new PLL setting values.
|
||||
#ifndef XOSC_HZ
|
||||
#ifdef XOSC_KHZ
|
||||
#define XOSC_HZ ((XOSC_KHZ) * _u(1000))
|
||||
#elif defined(XOSC_MHZ)
|
||||
#define XOSC_HZ ((XOSC_MHZ) * _u(1000000))
|
||||
#else
|
||||
#define XOSC_HZ _u(12000000)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: SYS_CLK_HZ, System operating frequency in Hz, type=int, default=125000000, advanced=true, group=hardware_base
|
||||
#ifndef SYS_CLK_HZ
|
||||
#ifdef SYS_CLK_KHZ
|
||||
#define SYS_CLK_HZ ((SYS_CLK_KHZ) * _u(1000))
|
||||
#elif defined(SYS_CLK_MHZ)
|
||||
#define SYS_CLK_HZ ((SYS_CLK_MHZ) * _u(1000000))
|
||||
#else
|
||||
#define SYS_CLK_HZ _u(125000000)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: USB_CLK_HZ, USB clock frequency. Must be 48MHz for the USB interface to operate correctly, type=int, default=48000000, advanced=true, group=hardware_base
|
||||
#ifndef USB_CLK_HZ
|
||||
#ifdef USB_CLK_KHZ
|
||||
#define USB_CLK_HZ ((USB_CLK_KHZ) * _u(1000))
|
||||
#elif defined(USB_CLK_MHZ)
|
||||
#define USB_CLK_HZ ((USB_CLK_MHZ) * _u(1000000))
|
||||
#else
|
||||
#define USB_CLK_HZ _u(48000000)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// For backwards compatibility define XOSC_KHZ if the frequency is indeed an integer number of Khz.
|
||||
#if defined(XOSC_HZ) && !defined(XOSC_KHZ) && (XOSC_HZ % 1000 == 0)
|
||||
#define XOSC_KHZ (XOSC_HZ / 1000)
|
||||
#endif
|
||||
|
||||
// For backwards compatibility define XOSC_MHZ if the frequency is indeed an integer number of Mhz.
|
||||
#if defined(XOSC_KHZ) && !defined(XOSC_MHZ) && (XOSC_KHZ % 1000 == 0)
|
||||
#define XOSC_MHZ (XOSC_KHZ / 1000)
|
||||
#endif
|
||||
|
||||
// For backwards compatibility define SYS_CLK_KHZ if the frequency is indeed an integer number of Khz.
|
||||
#if defined(SYS_CLK_HZ) && !defined(SYS_CLK_KHZ) && (SYS_CLK_HZ % 1000 == 0)
|
||||
#define SYS_CLK_KHZ (SYS_CLK_HZ / 1000)
|
||||
#endif
|
||||
|
||||
// For backwards compatibility define SYS_CLK_MHZ if the frequency is indeed an integer number of Mhz.
|
||||
#if defined(SYS_CLK_KHZ) && !defined(SYS_CLK_MHZ) && (SYS_CLK_KHZ % 1000 == 0)
|
||||
#define SYS_CLK_MHZ (SYS_CLK_KHZ / 1000)
|
||||
#endif
|
||||
|
||||
// For backwards compatibility define USB_CLK_KHZ if the frequency is indeed an integer number of Khz.
|
||||
#if defined(USB_CLK_HZ) && !defined(USB_CLK_KHZ) && (USB_CLK_HZ % 1000 == 0)
|
||||
#define USB_CLK_KHZ (USB_CLK_HZ / 1000)
|
||||
#endif
|
||||
|
||||
// For backwards compatibility define USB_CLK_MHZ if the frequency is indeed an integer number of Mhz.
|
||||
#if defined(USB_CLK_KHZ) && !defined(USB_CLK_MHZ) && (USB_CLK_KHZ % 1000 == 0)
|
||||
#define USB_CLK_MHZ (USB_CLK_KHZ / 1000)
|
||||
#endif
|
||||
|
||||
#define FIRST_USER_IRQ (NUM_IRQS - NUM_USER_IRQS)
|
||||
#define VTABLE_FIRST_IRQ 16
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,314 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : ADC
|
||||
// Version : 2
|
||||
// Bus type : apb
|
||||
// Description : Control and data interface to SAR ADC
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_ADC_H
|
||||
#define _HARDWARE_REGS_ADC_H
|
||||
// =============================================================================
|
||||
// Register : ADC_CS
|
||||
// Description : ADC Control and Status
|
||||
#define ADC_CS_OFFSET _u(0x00000000)
|
||||
#define ADC_CS_BITS _u(0x001f770f)
|
||||
#define ADC_CS_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_CS_RROBIN
|
||||
// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to
|
||||
// disable.
|
||||
// Otherwise, the ADC will cycle through each enabled channel in a
|
||||
// round-robin fashion.
|
||||
// The first channel to be sampled will be the one currently
|
||||
// indicated by AINSEL.
|
||||
// AINSEL will be updated after each conversion with the newly-
|
||||
// selected channel.
|
||||
#define ADC_CS_RROBIN_RESET _u(0x00)
|
||||
#define ADC_CS_RROBIN_BITS _u(0x001f0000)
|
||||
#define ADC_CS_RROBIN_MSB _u(20)
|
||||
#define ADC_CS_RROBIN_LSB _u(16)
|
||||
#define ADC_CS_RROBIN_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_CS_AINSEL
|
||||
// Description : Select analog mux input. Updated automatically in round-robin
|
||||
// mode.
|
||||
#define ADC_CS_AINSEL_RESET _u(0x0)
|
||||
#define ADC_CS_AINSEL_BITS _u(0x00007000)
|
||||
#define ADC_CS_AINSEL_MSB _u(14)
|
||||
#define ADC_CS_AINSEL_LSB _u(12)
|
||||
#define ADC_CS_AINSEL_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_CS_ERR_STICKY
|
||||
// Description : Some past ADC conversion encountered an error. Write 1 to
|
||||
// clear.
|
||||
#define ADC_CS_ERR_STICKY_RESET _u(0x0)
|
||||
#define ADC_CS_ERR_STICKY_BITS _u(0x00000400)
|
||||
#define ADC_CS_ERR_STICKY_MSB _u(10)
|
||||
#define ADC_CS_ERR_STICKY_LSB _u(10)
|
||||
#define ADC_CS_ERR_STICKY_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_CS_ERR
|
||||
// Description : The most recent ADC conversion encountered an error; result is
|
||||
// undefined or noisy.
|
||||
#define ADC_CS_ERR_RESET _u(0x0)
|
||||
#define ADC_CS_ERR_BITS _u(0x00000200)
|
||||
#define ADC_CS_ERR_MSB _u(9)
|
||||
#define ADC_CS_ERR_LSB _u(9)
|
||||
#define ADC_CS_ERR_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_CS_READY
|
||||
// Description : 1 if the ADC is ready to start a new conversion. Implies any
|
||||
// previous conversion has completed.
|
||||
// 0 whilst conversion in progress.
|
||||
#define ADC_CS_READY_RESET _u(0x0)
|
||||
#define ADC_CS_READY_BITS _u(0x00000100)
|
||||
#define ADC_CS_READY_MSB _u(8)
|
||||
#define ADC_CS_READY_LSB _u(8)
|
||||
#define ADC_CS_READY_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_CS_START_MANY
|
||||
// Description : Continuously perform conversions whilst this bit is 1. A new
|
||||
// conversion will start immediately after the previous finishes.
|
||||
#define ADC_CS_START_MANY_RESET _u(0x0)
|
||||
#define ADC_CS_START_MANY_BITS _u(0x00000008)
|
||||
#define ADC_CS_START_MANY_MSB _u(3)
|
||||
#define ADC_CS_START_MANY_LSB _u(3)
|
||||
#define ADC_CS_START_MANY_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_CS_START_ONCE
|
||||
// Description : Start a single conversion. Self-clearing. Ignored if start_many
|
||||
// is asserted.
|
||||
#define ADC_CS_START_ONCE_RESET _u(0x0)
|
||||
#define ADC_CS_START_ONCE_BITS _u(0x00000004)
|
||||
#define ADC_CS_START_ONCE_MSB _u(2)
|
||||
#define ADC_CS_START_ONCE_LSB _u(2)
|
||||
#define ADC_CS_START_ONCE_ACCESS "SC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_CS_TS_EN
|
||||
// Description : Power on temperature sensor. 1 - enabled. 0 - disabled.
|
||||
#define ADC_CS_TS_EN_RESET _u(0x0)
|
||||
#define ADC_CS_TS_EN_BITS _u(0x00000002)
|
||||
#define ADC_CS_TS_EN_MSB _u(1)
|
||||
#define ADC_CS_TS_EN_LSB _u(1)
|
||||
#define ADC_CS_TS_EN_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_CS_EN
|
||||
// Description : Power on ADC and enable its clock.
|
||||
// 1 - enabled. 0 - disabled.
|
||||
#define ADC_CS_EN_RESET _u(0x0)
|
||||
#define ADC_CS_EN_BITS _u(0x00000001)
|
||||
#define ADC_CS_EN_MSB _u(0)
|
||||
#define ADC_CS_EN_LSB _u(0)
|
||||
#define ADC_CS_EN_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : ADC_RESULT
|
||||
// Description : Result of most recent ADC conversion
|
||||
#define ADC_RESULT_OFFSET _u(0x00000004)
|
||||
#define ADC_RESULT_BITS _u(0x00000fff)
|
||||
#define ADC_RESULT_RESET _u(0x00000000)
|
||||
#define ADC_RESULT_MSB _u(11)
|
||||
#define ADC_RESULT_LSB _u(0)
|
||||
#define ADC_RESULT_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : ADC_FCS
|
||||
// Description : FIFO control and status
|
||||
#define ADC_FCS_OFFSET _u(0x00000008)
|
||||
#define ADC_FCS_BITS _u(0x0f0f0f0f)
|
||||
#define ADC_FCS_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FCS_THRESH
|
||||
// Description : DREQ/IRQ asserted when level >= threshold
|
||||
#define ADC_FCS_THRESH_RESET _u(0x0)
|
||||
#define ADC_FCS_THRESH_BITS _u(0x0f000000)
|
||||
#define ADC_FCS_THRESH_MSB _u(27)
|
||||
#define ADC_FCS_THRESH_LSB _u(24)
|
||||
#define ADC_FCS_THRESH_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FCS_LEVEL
|
||||
// Description : The number of conversion results currently waiting in the FIFO
|
||||
#define ADC_FCS_LEVEL_RESET _u(0x0)
|
||||
#define ADC_FCS_LEVEL_BITS _u(0x000f0000)
|
||||
#define ADC_FCS_LEVEL_MSB _u(19)
|
||||
#define ADC_FCS_LEVEL_LSB _u(16)
|
||||
#define ADC_FCS_LEVEL_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FCS_OVER
|
||||
// Description : 1 if the FIFO has been overflowed. Write 1 to clear.
|
||||
#define ADC_FCS_OVER_RESET _u(0x0)
|
||||
#define ADC_FCS_OVER_BITS _u(0x00000800)
|
||||
#define ADC_FCS_OVER_MSB _u(11)
|
||||
#define ADC_FCS_OVER_LSB _u(11)
|
||||
#define ADC_FCS_OVER_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FCS_UNDER
|
||||
// Description : 1 if the FIFO has been underflowed. Write 1 to clear.
|
||||
#define ADC_FCS_UNDER_RESET _u(0x0)
|
||||
#define ADC_FCS_UNDER_BITS _u(0x00000400)
|
||||
#define ADC_FCS_UNDER_MSB _u(10)
|
||||
#define ADC_FCS_UNDER_LSB _u(10)
|
||||
#define ADC_FCS_UNDER_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FCS_FULL
|
||||
#define ADC_FCS_FULL_RESET _u(0x0)
|
||||
#define ADC_FCS_FULL_BITS _u(0x00000200)
|
||||
#define ADC_FCS_FULL_MSB _u(9)
|
||||
#define ADC_FCS_FULL_LSB _u(9)
|
||||
#define ADC_FCS_FULL_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FCS_EMPTY
|
||||
#define ADC_FCS_EMPTY_RESET _u(0x0)
|
||||
#define ADC_FCS_EMPTY_BITS _u(0x00000100)
|
||||
#define ADC_FCS_EMPTY_MSB _u(8)
|
||||
#define ADC_FCS_EMPTY_LSB _u(8)
|
||||
#define ADC_FCS_EMPTY_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FCS_DREQ_EN
|
||||
// Description : If 1: assert DMA requests when FIFO contains data
|
||||
#define ADC_FCS_DREQ_EN_RESET _u(0x0)
|
||||
#define ADC_FCS_DREQ_EN_BITS _u(0x00000008)
|
||||
#define ADC_FCS_DREQ_EN_MSB _u(3)
|
||||
#define ADC_FCS_DREQ_EN_LSB _u(3)
|
||||
#define ADC_FCS_DREQ_EN_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FCS_ERR
|
||||
// Description : If 1: conversion error bit appears in the FIFO alongside the
|
||||
// result
|
||||
#define ADC_FCS_ERR_RESET _u(0x0)
|
||||
#define ADC_FCS_ERR_BITS _u(0x00000004)
|
||||
#define ADC_FCS_ERR_MSB _u(2)
|
||||
#define ADC_FCS_ERR_LSB _u(2)
|
||||
#define ADC_FCS_ERR_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FCS_SHIFT
|
||||
// Description : If 1: FIFO results are right-shifted to be one byte in size.
|
||||
// Enables DMA to byte buffers.
|
||||
#define ADC_FCS_SHIFT_RESET _u(0x0)
|
||||
#define ADC_FCS_SHIFT_BITS _u(0x00000002)
|
||||
#define ADC_FCS_SHIFT_MSB _u(1)
|
||||
#define ADC_FCS_SHIFT_LSB _u(1)
|
||||
#define ADC_FCS_SHIFT_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FCS_EN
|
||||
// Description : If 1: write result to the FIFO after each conversion.
|
||||
#define ADC_FCS_EN_RESET _u(0x0)
|
||||
#define ADC_FCS_EN_BITS _u(0x00000001)
|
||||
#define ADC_FCS_EN_MSB _u(0)
|
||||
#define ADC_FCS_EN_LSB _u(0)
|
||||
#define ADC_FCS_EN_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : ADC_FIFO
|
||||
// Description : Conversion result FIFO
|
||||
#define ADC_FIFO_OFFSET _u(0x0000000c)
|
||||
#define ADC_FIFO_BITS _u(0x00008fff)
|
||||
#define ADC_FIFO_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FIFO_ERR
|
||||
// Description : 1 if this particular sample experienced a conversion error.
|
||||
// Remains in the same location if the sample is shifted.
|
||||
#define ADC_FIFO_ERR_RESET "-"
|
||||
#define ADC_FIFO_ERR_BITS _u(0x00008000)
|
||||
#define ADC_FIFO_ERR_MSB _u(15)
|
||||
#define ADC_FIFO_ERR_LSB _u(15)
|
||||
#define ADC_FIFO_ERR_ACCESS "RF"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_FIFO_VAL
|
||||
#define ADC_FIFO_VAL_RESET "-"
|
||||
#define ADC_FIFO_VAL_BITS _u(0x00000fff)
|
||||
#define ADC_FIFO_VAL_MSB _u(11)
|
||||
#define ADC_FIFO_VAL_LSB _u(0)
|
||||
#define ADC_FIFO_VAL_ACCESS "RF"
|
||||
// =============================================================================
|
||||
// Register : ADC_DIV
|
||||
// Description : Clock divider. If non-zero, CS_START_MANY will start
|
||||
// conversions
|
||||
// at regular intervals rather than back-to-back.
|
||||
// The divider is reset when either of these fields are written.
|
||||
// Total period is 1 + INT + FRAC / 256
|
||||
#define ADC_DIV_OFFSET _u(0x00000010)
|
||||
#define ADC_DIV_BITS _u(0x00ffffff)
|
||||
#define ADC_DIV_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_DIV_INT
|
||||
// Description : Integer part of clock divisor.
|
||||
#define ADC_DIV_INT_RESET _u(0x0000)
|
||||
#define ADC_DIV_INT_BITS _u(0x00ffff00)
|
||||
#define ADC_DIV_INT_MSB _u(23)
|
||||
#define ADC_DIV_INT_LSB _u(8)
|
||||
#define ADC_DIV_INT_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_DIV_FRAC
|
||||
// Description : Fractional part of clock divisor. First-order delta-sigma.
|
||||
#define ADC_DIV_FRAC_RESET _u(0x00)
|
||||
#define ADC_DIV_FRAC_BITS _u(0x000000ff)
|
||||
#define ADC_DIV_FRAC_MSB _u(7)
|
||||
#define ADC_DIV_FRAC_LSB _u(0)
|
||||
#define ADC_DIV_FRAC_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : ADC_INTR
|
||||
// Description : Raw Interrupts
|
||||
#define ADC_INTR_OFFSET _u(0x00000014)
|
||||
#define ADC_INTR_BITS _u(0x00000001)
|
||||
#define ADC_INTR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_INTR_FIFO
|
||||
// Description : Triggered when the sample FIFO reaches a certain level.
|
||||
// This level can be programmed via the FCS_THRESH field.
|
||||
#define ADC_INTR_FIFO_RESET _u(0x0)
|
||||
#define ADC_INTR_FIFO_BITS _u(0x00000001)
|
||||
#define ADC_INTR_FIFO_MSB _u(0)
|
||||
#define ADC_INTR_FIFO_LSB _u(0)
|
||||
#define ADC_INTR_FIFO_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : ADC_INTE
|
||||
// Description : Interrupt Enable
|
||||
#define ADC_INTE_OFFSET _u(0x00000018)
|
||||
#define ADC_INTE_BITS _u(0x00000001)
|
||||
#define ADC_INTE_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_INTE_FIFO
|
||||
// Description : Triggered when the sample FIFO reaches a certain level.
|
||||
// This level can be programmed via the FCS_THRESH field.
|
||||
#define ADC_INTE_FIFO_RESET _u(0x0)
|
||||
#define ADC_INTE_FIFO_BITS _u(0x00000001)
|
||||
#define ADC_INTE_FIFO_MSB _u(0)
|
||||
#define ADC_INTE_FIFO_LSB _u(0)
|
||||
#define ADC_INTE_FIFO_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : ADC_INTF
|
||||
// Description : Interrupt Force
|
||||
#define ADC_INTF_OFFSET _u(0x0000001c)
|
||||
#define ADC_INTF_BITS _u(0x00000001)
|
||||
#define ADC_INTF_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_INTF_FIFO
|
||||
// Description : Triggered when the sample FIFO reaches a certain level.
|
||||
// This level can be programmed via the FCS_THRESH field.
|
||||
#define ADC_INTF_FIFO_RESET _u(0x0)
|
||||
#define ADC_INTF_FIFO_BITS _u(0x00000001)
|
||||
#define ADC_INTF_FIFO_MSB _u(0)
|
||||
#define ADC_INTF_FIFO_LSB _u(0)
|
||||
#define ADC_INTF_FIFO_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : ADC_INTS
|
||||
// Description : Interrupt status after masking & forcing
|
||||
#define ADC_INTS_OFFSET _u(0x00000020)
|
||||
#define ADC_INTS_BITS _u(0x00000001)
|
||||
#define ADC_INTS_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ADC_INTS_FIFO
|
||||
// Description : Triggered when the sample FIFO reaches a certain level.
|
||||
// This level can be programmed via the FCS_THRESH field.
|
||||
#define ADC_INTS_FIFO_RESET _u(0x0)
|
||||
#define ADC_INTS_FIFO_BITS _u(0x00000001)
|
||||
#define ADC_INTS_FIFO_MSB _u(0)
|
||||
#define ADC_INTS_FIFO_LSB _u(0)
|
||||
#define ADC_INTS_FIFO_ACCESS "RO"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_ADC_H
|
||||
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _ADDRESSMAP_H
|
||||
#define _ADDRESSMAP_H
|
||||
|
||||
/**
|
||||
* \file rp2040/addressmap.h
|
||||
*/
|
||||
|
||||
#include "hardware/platform_defs.h"
|
||||
|
||||
// Register address offsets for atomic RMW aliases
|
||||
#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12))
|
||||
#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12))
|
||||
#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12))
|
||||
#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12))
|
||||
|
||||
#define ROM_BASE _u(0x00000000)
|
||||
#define XIP_BASE _u(0x10000000)
|
||||
#define XIP_MAIN_BASE _u(0x10000000)
|
||||
#define XIP_NOALLOC_BASE _u(0x11000000)
|
||||
#define XIP_NOCACHE_BASE _u(0x12000000)
|
||||
#define XIP_NOCACHE_NOALLOC_BASE _u(0x13000000)
|
||||
#define XIP_CTRL_BASE _u(0x14000000)
|
||||
#define XIP_SRAM_BASE _u(0x15000000)
|
||||
#define XIP_SRAM_END _u(0x15004000)
|
||||
#define XIP_SSI_BASE _u(0x18000000)
|
||||
#define SRAM_BASE _u(0x20000000)
|
||||
#define SRAM_STRIPED_BASE _u(0x20000000)
|
||||
#define SRAM_STRIPED_END _u(0x20040000)
|
||||
#define SRAM4_BASE _u(0x20040000)
|
||||
#define SRAM5_BASE _u(0x20041000)
|
||||
#define SRAM_END _u(0x20042000)
|
||||
#define SRAM0_BASE _u(0x21000000)
|
||||
#define SRAM1_BASE _u(0x21010000)
|
||||
#define SRAM2_BASE _u(0x21020000)
|
||||
#define SRAM3_BASE _u(0x21030000)
|
||||
#define SYSINFO_BASE _u(0x40000000)
|
||||
#define SYSCFG_BASE _u(0x40004000)
|
||||
#define CLOCKS_BASE _u(0x40008000)
|
||||
#define RESETS_BASE _u(0x4000c000)
|
||||
#define PSM_BASE _u(0x40010000)
|
||||
#define IO_BANK0_BASE _u(0x40014000)
|
||||
#define IO_QSPI_BASE _u(0x40018000)
|
||||
#define PADS_BANK0_BASE _u(0x4001c000)
|
||||
#define PADS_QSPI_BASE _u(0x40020000)
|
||||
#define XOSC_BASE _u(0x40024000)
|
||||
#define PLL_SYS_BASE _u(0x40028000)
|
||||
#define PLL_USB_BASE _u(0x4002c000)
|
||||
#define BUSCTRL_BASE _u(0x40030000)
|
||||
#define UART0_BASE _u(0x40034000)
|
||||
#define UART1_BASE _u(0x40038000)
|
||||
#define SPI0_BASE _u(0x4003c000)
|
||||
#define SPI1_BASE _u(0x40040000)
|
||||
#define I2C0_BASE _u(0x40044000)
|
||||
#define I2C1_BASE _u(0x40048000)
|
||||
#define ADC_BASE _u(0x4004c000)
|
||||
#define PWM_BASE _u(0x40050000)
|
||||
#define TIMER_BASE _u(0x40054000)
|
||||
#define WATCHDOG_BASE _u(0x40058000)
|
||||
#define RTC_BASE _u(0x4005c000)
|
||||
#define ROSC_BASE _u(0x40060000)
|
||||
#define VREG_AND_CHIP_RESET_BASE _u(0x40064000)
|
||||
#define TBMAN_BASE _u(0x4006c000)
|
||||
#define DMA_BASE _u(0x50000000)
|
||||
#define USBCTRL_DPRAM_BASE _u(0x50100000)
|
||||
#define USBCTRL_BASE _u(0x50100000)
|
||||
#define USBCTRL_REGS_BASE _u(0x50110000)
|
||||
#define PIO0_BASE _u(0x50200000)
|
||||
#define PIO1_BASE _u(0x50300000)
|
||||
#define XIP_AUX_BASE _u(0x50400000)
|
||||
#define SIO_BASE _u(0xd0000000)
|
||||
#define PPB_BASE _u(0xe0000000)
|
||||
|
||||
#endif // _ADDRESSMAP_H
|
||||
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : BUSCTRL
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// Description : Register block for busfabric control signals and performance
|
||||
// counters
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_BUSCTRL_H
|
||||
#define _HARDWARE_REGS_BUSCTRL_H
|
||||
// =============================================================================
|
||||
// Register : BUSCTRL_BUS_PRIORITY
|
||||
// Description : Set the priority of each master for bus arbitration.
|
||||
#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000)
|
||||
#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111)
|
||||
#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : BUSCTRL_BUS_PRIORITY_DMA_W
|
||||
// Description : 0 - low priority, 1 - high priority
|
||||
#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0)
|
||||
#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000)
|
||||
#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12)
|
||||
#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12)
|
||||
#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : BUSCTRL_BUS_PRIORITY_DMA_R
|
||||
// Description : 0 - low priority, 1 - high priority
|
||||
#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0)
|
||||
#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100)
|
||||
#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8)
|
||||
#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8)
|
||||
#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : BUSCTRL_BUS_PRIORITY_PROC1
|
||||
// Description : 0 - low priority, 1 - high priority
|
||||
#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0)
|
||||
#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010)
|
||||
#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4)
|
||||
#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4)
|
||||
#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : BUSCTRL_BUS_PRIORITY_PROC0
|
||||
// Description : 0 - low priority, 1 - high priority
|
||||
#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0)
|
||||
#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001)
|
||||
#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0)
|
||||
#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0)
|
||||
#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : BUSCTRL_BUS_PRIORITY_ACK
|
||||
// Description : Bus priority acknowledge
|
||||
// Goes to 1 once all arbiters have registered the new global
|
||||
// priority levels.
|
||||
// Arbiters update their local priority when servicing a new
|
||||
// nonsequential access.
|
||||
// In normal circumstances this will happen almost immediately.
|
||||
#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004)
|
||||
#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001)
|
||||
#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000)
|
||||
#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0)
|
||||
#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0)
|
||||
#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : BUSCTRL_PERFCTR0
|
||||
// Description : Bus fabric performance counter 0
|
||||
// Busfabric saturating performance counter 0
|
||||
// Count some event signal from the busfabric arbiters.
|
||||
// Write any value to clear. Select an event to count using
|
||||
// PERFSEL0
|
||||
#define BUSCTRL_PERFCTR0_OFFSET _u(0x00000008)
|
||||
#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff)
|
||||
#define BUSCTRL_PERFCTR0_RESET _u(0x00000000)
|
||||
#define BUSCTRL_PERFCTR0_MSB _u(23)
|
||||
#define BUSCTRL_PERFCTR0_LSB _u(0)
|
||||
#define BUSCTRL_PERFCTR0_ACCESS "WC"
|
||||
// =============================================================================
|
||||
// Register : BUSCTRL_PERFSEL0
|
||||
// Description : Bus fabric performance event select for PERFCTR0
|
||||
// Select an event for PERFCTR0. Count either contested accesses,
|
||||
// or all accesses, on a downstream port of the main crossbar.
|
||||
// 0x00 -> apb_contested
|
||||
// 0x01 -> apb
|
||||
// 0x02 -> fastperi_contested
|
||||
// 0x03 -> fastperi
|
||||
// 0x04 -> sram5_contested
|
||||
// 0x05 -> sram5
|
||||
// 0x06 -> sram4_contested
|
||||
// 0x07 -> sram4
|
||||
// 0x08 -> sram3_contested
|
||||
// 0x09 -> sram3
|
||||
// 0x0a -> sram2_contested
|
||||
// 0x0b -> sram2
|
||||
// 0x0c -> sram1_contested
|
||||
// 0x0d -> sram1
|
||||
// 0x0e -> sram0_contested
|
||||
// 0x0f -> sram0
|
||||
// 0x10 -> xip_main_contested
|
||||
// 0x11 -> xip_main
|
||||
// 0x12 -> rom_contested
|
||||
// 0x13 -> rom
|
||||
#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c)
|
||||
#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f)
|
||||
#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f)
|
||||
#define BUSCTRL_PERFSEL0_MSB _u(4)
|
||||
#define BUSCTRL_PERFSEL0_LSB _u(0)
|
||||
#define BUSCTRL_PERFSEL0_ACCESS "RW"
|
||||
#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _u(0x02)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _u(0x10)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12)
|
||||
#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13)
|
||||
// =============================================================================
|
||||
// Register : BUSCTRL_PERFCTR1
|
||||
// Description : Bus fabric performance counter 1
|
||||
// Busfabric saturating performance counter 1
|
||||
// Count some event signal from the busfabric arbiters.
|
||||
// Write any value to clear. Select an event to count using
|
||||
// PERFSEL1
|
||||
#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000010)
|
||||
#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff)
|
||||
#define BUSCTRL_PERFCTR1_RESET _u(0x00000000)
|
||||
#define BUSCTRL_PERFCTR1_MSB _u(23)
|
||||
#define BUSCTRL_PERFCTR1_LSB _u(0)
|
||||
#define BUSCTRL_PERFCTR1_ACCESS "WC"
|
||||
// =============================================================================
|
||||
// Register : BUSCTRL_PERFSEL1
|
||||
// Description : Bus fabric performance event select for PERFCTR1
|
||||
// Select an event for PERFCTR1. Count either contested accesses,
|
||||
// or all accesses, on a downstream port of the main crossbar.
|
||||
// 0x00 -> apb_contested
|
||||
// 0x01 -> apb
|
||||
// 0x02 -> fastperi_contested
|
||||
// 0x03 -> fastperi
|
||||
// 0x04 -> sram5_contested
|
||||
// 0x05 -> sram5
|
||||
// 0x06 -> sram4_contested
|
||||
// 0x07 -> sram4
|
||||
// 0x08 -> sram3_contested
|
||||
// 0x09 -> sram3
|
||||
// 0x0a -> sram2_contested
|
||||
// 0x0b -> sram2
|
||||
// 0x0c -> sram1_contested
|
||||
// 0x0d -> sram1
|
||||
// 0x0e -> sram0_contested
|
||||
// 0x0f -> sram0
|
||||
// 0x10 -> xip_main_contested
|
||||
// 0x11 -> xip_main
|
||||
// 0x12 -> rom_contested
|
||||
// 0x13 -> rom
|
||||
#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014)
|
||||
#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f)
|
||||
#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f)
|
||||
#define BUSCTRL_PERFSEL1_MSB _u(4)
|
||||
#define BUSCTRL_PERFSEL1_LSB _u(0)
|
||||
#define BUSCTRL_PERFSEL1_ACCESS "RW"
|
||||
#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _u(0x02)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _u(0x10)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12)
|
||||
#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13)
|
||||
// =============================================================================
|
||||
// Register : BUSCTRL_PERFCTR2
|
||||
// Description : Bus fabric performance counter 2
|
||||
// Busfabric saturating performance counter 2
|
||||
// Count some event signal from the busfabric arbiters.
|
||||
// Write any value to clear. Select an event to count using
|
||||
// PERFSEL2
|
||||
#define BUSCTRL_PERFCTR2_OFFSET _u(0x00000018)
|
||||
#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff)
|
||||
#define BUSCTRL_PERFCTR2_RESET _u(0x00000000)
|
||||
#define BUSCTRL_PERFCTR2_MSB _u(23)
|
||||
#define BUSCTRL_PERFCTR2_LSB _u(0)
|
||||
#define BUSCTRL_PERFCTR2_ACCESS "WC"
|
||||
// =============================================================================
|
||||
// Register : BUSCTRL_PERFSEL2
|
||||
// Description : Bus fabric performance event select for PERFCTR2
|
||||
// Select an event for PERFCTR2. Count either contested accesses,
|
||||
// or all accesses, on a downstream port of the main crossbar.
|
||||
// 0x00 -> apb_contested
|
||||
// 0x01 -> apb
|
||||
// 0x02 -> fastperi_contested
|
||||
// 0x03 -> fastperi
|
||||
// 0x04 -> sram5_contested
|
||||
// 0x05 -> sram5
|
||||
// 0x06 -> sram4_contested
|
||||
// 0x07 -> sram4
|
||||
// 0x08 -> sram3_contested
|
||||
// 0x09 -> sram3
|
||||
// 0x0a -> sram2_contested
|
||||
// 0x0b -> sram2
|
||||
// 0x0c -> sram1_contested
|
||||
// 0x0d -> sram1
|
||||
// 0x0e -> sram0_contested
|
||||
// 0x0f -> sram0
|
||||
// 0x10 -> xip_main_contested
|
||||
// 0x11 -> xip_main
|
||||
// 0x12 -> rom_contested
|
||||
// 0x13 -> rom
|
||||
#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c)
|
||||
#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f)
|
||||
#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f)
|
||||
#define BUSCTRL_PERFSEL2_MSB _u(4)
|
||||
#define BUSCTRL_PERFSEL2_LSB _u(0)
|
||||
#define BUSCTRL_PERFSEL2_ACCESS "RW"
|
||||
#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _u(0x02)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _u(0x10)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12)
|
||||
#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13)
|
||||
// =============================================================================
|
||||
// Register : BUSCTRL_PERFCTR3
|
||||
// Description : Bus fabric performance counter 3
|
||||
// Busfabric saturating performance counter 3
|
||||
// Count some event signal from the busfabric arbiters.
|
||||
// Write any value to clear. Select an event to count using
|
||||
// PERFSEL3
|
||||
#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000020)
|
||||
#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff)
|
||||
#define BUSCTRL_PERFCTR3_RESET _u(0x00000000)
|
||||
#define BUSCTRL_PERFCTR3_MSB _u(23)
|
||||
#define BUSCTRL_PERFCTR3_LSB _u(0)
|
||||
#define BUSCTRL_PERFCTR3_ACCESS "WC"
|
||||
// =============================================================================
|
||||
// Register : BUSCTRL_PERFSEL3
|
||||
// Description : Bus fabric performance event select for PERFCTR3
|
||||
// Select an event for PERFCTR3. Count either contested accesses,
|
||||
// or all accesses, on a downstream port of the main crossbar.
|
||||
// 0x00 -> apb_contested
|
||||
// 0x01 -> apb
|
||||
// 0x02 -> fastperi_contested
|
||||
// 0x03 -> fastperi
|
||||
// 0x04 -> sram5_contested
|
||||
// 0x05 -> sram5
|
||||
// 0x06 -> sram4_contested
|
||||
// 0x07 -> sram4
|
||||
// 0x08 -> sram3_contested
|
||||
// 0x09 -> sram3
|
||||
// 0x0a -> sram2_contested
|
||||
// 0x0b -> sram2
|
||||
// 0x0c -> sram1_contested
|
||||
// 0x0d -> sram1
|
||||
// 0x0e -> sram0_contested
|
||||
// 0x0f -> sram0
|
||||
// 0x10 -> xip_main_contested
|
||||
// 0x11 -> xip_main
|
||||
// 0x12 -> rom_contested
|
||||
// 0x13 -> rom
|
||||
#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024)
|
||||
#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f)
|
||||
#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f)
|
||||
#define BUSCTRL_PERFSEL3_MSB _u(4)
|
||||
#define BUSCTRL_PERFSEL3_LSB _u(0)
|
||||
#define BUSCTRL_PERFSEL3_ACCESS "RW"
|
||||
#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _u(0x02)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _u(0x10)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12)
|
||||
#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13)
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_BUSCTRL_H
|
||||
|
||||
File diff suppressed because it is too large
Load diff
5301
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h
Normal file
5301
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,117 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _DREQ_H
|
||||
#define _DREQ_H
|
||||
|
||||
/**
|
||||
* \file rp2040/dreq.h
|
||||
*/
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
#define DREQ_PIO0_TX0 0
|
||||
#define DREQ_PIO0_TX1 1
|
||||
#define DREQ_PIO0_TX2 2
|
||||
#define DREQ_PIO0_TX3 3
|
||||
#define DREQ_PIO0_RX0 4
|
||||
#define DREQ_PIO0_RX1 5
|
||||
#define DREQ_PIO0_RX2 6
|
||||
#define DREQ_PIO0_RX3 7
|
||||
#define DREQ_PIO1_TX0 8
|
||||
#define DREQ_PIO1_TX1 9
|
||||
#define DREQ_PIO1_TX2 10
|
||||
#define DREQ_PIO1_TX3 11
|
||||
#define DREQ_PIO1_RX0 12
|
||||
#define DREQ_PIO1_RX1 13
|
||||
#define DREQ_PIO1_RX2 14
|
||||
#define DREQ_PIO1_RX3 15
|
||||
#define DREQ_SPI0_TX 16
|
||||
#define DREQ_SPI0_RX 17
|
||||
#define DREQ_SPI1_TX 18
|
||||
#define DREQ_SPI1_RX 19
|
||||
#define DREQ_UART0_TX 20
|
||||
#define DREQ_UART0_RX 21
|
||||
#define DREQ_UART1_TX 22
|
||||
#define DREQ_UART1_RX 23
|
||||
#define DREQ_PWM_WRAP0 24
|
||||
#define DREQ_PWM_WRAP1 25
|
||||
#define DREQ_PWM_WRAP2 26
|
||||
#define DREQ_PWM_WRAP3 27
|
||||
#define DREQ_PWM_WRAP4 28
|
||||
#define DREQ_PWM_WRAP5 29
|
||||
#define DREQ_PWM_WRAP6 30
|
||||
#define DREQ_PWM_WRAP7 31
|
||||
#define DREQ_I2C0_TX 32
|
||||
#define DREQ_I2C0_RX 33
|
||||
#define DREQ_I2C1_TX 34
|
||||
#define DREQ_I2C1_RX 35
|
||||
#define DREQ_ADC 36
|
||||
#define DREQ_XIP_STREAM 37
|
||||
#define DREQ_XIP_SSITX 38
|
||||
#define DREQ_XIP_SSIRX 39
|
||||
#define DREQ_DMA_TIMER0 59
|
||||
#define DREQ_DMA_TIMER1 60
|
||||
#define DREQ_DMA_TIMER2 61
|
||||
#define DREQ_DMA_TIMER3 62
|
||||
#define DREQ_FORCE 63
|
||||
#else
|
||||
/**
|
||||
* \brief DREQ numbers for DMA pacing on RP2040 (used as typedef \ref dreq_num_t)
|
||||
* \ingroup hardware_dma
|
||||
*/
|
||||
typedef enum dreq_num_rp2040 {
|
||||
DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ
|
||||
DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ
|
||||
DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ
|
||||
DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ
|
||||
DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ
|
||||
DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ
|
||||
DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ
|
||||
DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ
|
||||
DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ
|
||||
DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ
|
||||
DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ
|
||||
DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ
|
||||
DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ
|
||||
DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ
|
||||
DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ
|
||||
DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ
|
||||
DREQ_SPI0_TX = 16, ///< Select SPI0's TX FIFO as DREQ
|
||||
DREQ_SPI0_RX = 17, ///< Select SPI0's RX FIFO as DREQ
|
||||
DREQ_SPI1_TX = 18, ///< Select SPI1's TX FIFO as DREQ
|
||||
DREQ_SPI1_RX = 19, ///< Select SPI1's RX FIFO as DREQ
|
||||
DREQ_UART0_TX = 20, ///< Select UART0's TX FIFO as DREQ
|
||||
DREQ_UART0_RX = 21, ///< Select UART0's RX FIFO as DREQ
|
||||
DREQ_UART1_TX = 22, ///< Select UART1's TX FIFO as DREQ
|
||||
DREQ_UART1_RX = 23, ///< Select UART1's RX FIFO as DREQ
|
||||
DREQ_PWM_WRAP0 = 24, ///< Select PWM Counter 0's Wrap Value as DREQ
|
||||
DREQ_PWM_WRAP1 = 25, ///< Select PWM Counter 1's Wrap Value as DREQ
|
||||
DREQ_PWM_WRAP2 = 26, ///< Select PWM Counter 2's Wrap Value as DREQ
|
||||
DREQ_PWM_WRAP3 = 27, ///< Select PWM Counter 3's Wrap Value as DREQ
|
||||
DREQ_PWM_WRAP4 = 28, ///< Select PWM Counter 4's Wrap Value as DREQ
|
||||
DREQ_PWM_WRAP5 = 29, ///< Select PWM Counter 5's Wrap Value as DREQ
|
||||
DREQ_PWM_WRAP6 = 30, ///< Select PWM Counter 6's Wrap Value as DREQ
|
||||
DREQ_PWM_WRAP7 = 31, ///< Select PWM Counter 7's Wrap Value as DREQ
|
||||
DREQ_I2C0_TX = 32, ///< Select I2C0's TX FIFO as DREQ
|
||||
DREQ_I2C0_RX = 33, ///< Select I2C0's RX FIFO as DREQ
|
||||
DREQ_I2C1_TX = 34, ///< Select I2C1's TX FIFO as DREQ
|
||||
DREQ_I2C1_RX = 35, ///< Select I2C1's RX FIFO as DREQ
|
||||
DREQ_ADC = 36, ///< Select the ADC as DREQ
|
||||
DREQ_XIP_STREAM = 37, ///< Select the XIP Streaming FIFO as DREQ
|
||||
DREQ_XIP_SSITX = 38, ///< Select the XIP SSI TX FIFO as DREQ
|
||||
DREQ_XIP_SSIRX = 39, ///< Select the XIP SSI RX FIFO as DREQ
|
||||
DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ
|
||||
DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ
|
||||
DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ
|
||||
DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ
|
||||
DREQ_FORCE = 63, ///< Select FORCE as DREQ
|
||||
DREQ_COUNT
|
||||
} dreq_num_t;
|
||||
#endif
|
||||
|
||||
#endif // _DREQ_H
|
||||
|
||||
2700
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h
Normal file
2700
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,106 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _INTCTRL_H
|
||||
#define _INTCTRL_H
|
||||
|
||||
/**
|
||||
* \file rp2040/intctrl.h
|
||||
*/
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
#define TIMER_IRQ_0 0
|
||||
#define TIMER_IRQ_1 1
|
||||
#define TIMER_IRQ_2 2
|
||||
#define TIMER_IRQ_3 3
|
||||
#define PWM_IRQ_WRAP 4
|
||||
#define USBCTRL_IRQ 5
|
||||
#define XIP_IRQ 6
|
||||
#define PIO0_IRQ_0 7
|
||||
#define PIO0_IRQ_1 8
|
||||
#define PIO1_IRQ_0 9
|
||||
#define PIO1_IRQ_1 10
|
||||
#define DMA_IRQ_0 11
|
||||
#define DMA_IRQ_1 12
|
||||
#define IO_IRQ_BANK0 13
|
||||
#define IO_IRQ_QSPI 14
|
||||
#define SIO_IRQ_PROC0 15
|
||||
#define SIO_IRQ_PROC1 16
|
||||
#define CLOCKS_IRQ 17
|
||||
#define SPI0_IRQ 18
|
||||
#define SPI1_IRQ 19
|
||||
#define UART0_IRQ 20
|
||||
#define UART1_IRQ 21
|
||||
#define ADC_IRQ_FIFO 22
|
||||
#define I2C0_IRQ 23
|
||||
#define I2C1_IRQ 24
|
||||
#define RTC_IRQ 25
|
||||
#else
|
||||
/**
|
||||
* \brief Interrupt numbers on RP2040 (used as typedef \ref irq_num_t)
|
||||
* \ingroup hardware_irq
|
||||
*/
|
||||
typedef enum irq_num_rp2040 {
|
||||
TIMER_IRQ_0 = 0, ///< Select TIMER's IRQ 0 output
|
||||
TIMER_IRQ_1 = 1, ///< Select TIMER's IRQ 1 output
|
||||
TIMER_IRQ_2 = 2, ///< Select TIMER's IRQ 2 output
|
||||
TIMER_IRQ_3 = 3, ///< Select TIMER's IRQ 3 output
|
||||
PWM_IRQ_WRAP = 4, ///< Select PWM's IRQ_WRAP output
|
||||
USBCTRL_IRQ = 5, ///< Select USBCTRL's IRQ output
|
||||
XIP_IRQ = 6, ///< Select XIP's IRQ output
|
||||
PIO0_IRQ_0 = 7, ///< Select PIO0's IRQ 0 output
|
||||
PIO0_IRQ_1 = 8, ///< Select PIO0's IRQ 1 output
|
||||
PIO1_IRQ_0 = 9, ///< Select PIO1's IRQ 0 output
|
||||
PIO1_IRQ_1 = 10, ///< Select PIO1's IRQ 1 output
|
||||
DMA_IRQ_0 = 11, ///< Select DMA's IRQ 0 output
|
||||
DMA_IRQ_1 = 12, ///< Select DMA's IRQ 1 output
|
||||
IO_IRQ_BANK0 = 13, ///< Select IO_BANK0's IRQ output
|
||||
IO_IRQ_QSPI = 14, ///< Select IO_QSPI's IRQ output
|
||||
SIO_IRQ_PROC0 = 15, ///< Select SIO_PROC0's IRQ output
|
||||
SIO_IRQ_PROC1 = 16, ///< Select SIO_PROC1's IRQ output
|
||||
CLOCKS_IRQ = 17, ///< Select CLOCKS's IRQ output
|
||||
SPI0_IRQ = 18, ///< Select SPI0's IRQ output
|
||||
SPI1_IRQ = 19, ///< Select SPI1's IRQ output
|
||||
UART0_IRQ = 20, ///< Select UART0's IRQ output
|
||||
UART1_IRQ = 21, ///< Select UART1's IRQ output
|
||||
ADC_IRQ_FIFO = 22, ///< Select ADC's IRQ_FIFO output
|
||||
I2C0_IRQ = 23, ///< Select I2C0's IRQ output
|
||||
I2C1_IRQ = 24, ///< Select I2C1's IRQ output
|
||||
RTC_IRQ = 25, ///< Select RTC's IRQ output
|
||||
IRQ_COUNT
|
||||
} irq_num_t;
|
||||
#endif
|
||||
|
||||
#define isr_timer_0 isr_irq0
|
||||
#define isr_timer_1 isr_irq1
|
||||
#define isr_timer_2 isr_irq2
|
||||
#define isr_timer_3 isr_irq3
|
||||
#define isr_pwm_wrap isr_irq4
|
||||
#define isr_usbctrl isr_irq5
|
||||
#define isr_xip isr_irq6
|
||||
#define isr_pio0_0 isr_irq7
|
||||
#define isr_pio0_1 isr_irq8
|
||||
#define isr_pio1_0 isr_irq9
|
||||
#define isr_pio1_1 isr_irq10
|
||||
#define isr_dma_0 isr_irq11
|
||||
#define isr_dma_1 isr_irq12
|
||||
#define isr_io_bank0 isr_irq13
|
||||
#define isr_io_qspi isr_irq14
|
||||
#define isr_sio_proc0 isr_irq15
|
||||
#define isr_sio_proc1 isr_irq16
|
||||
#define isr_clocks isr_irq17
|
||||
#define isr_spi0 isr_irq18
|
||||
#define isr_spi1 isr_irq19
|
||||
#define isr_uart0 isr_irq20
|
||||
#define isr_uart1 isr_irq21
|
||||
#define isr_adc_fifo isr_irq22
|
||||
#define isr_i2c0 isr_irq23
|
||||
#define isr_i2c1 isr_irq24
|
||||
#define isr_rtc isr_irq25
|
||||
|
||||
#endif // _INTCTRL_H
|
||||
|
||||
13649
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h
Normal file
13649
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,456 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : PADS_QSPI
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_PADS_QSPI_H
|
||||
#define _HARDWARE_REGS_PADS_QSPI_H
|
||||
// =============================================================================
|
||||
// Register : PADS_QSPI_VOLTAGE_SELECT
|
||||
// Description : Voltage select. Per bank control
|
||||
// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
|
||||
// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
|
||||
#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000)
|
||||
#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001)
|
||||
#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000)
|
||||
#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0)
|
||||
#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0)
|
||||
#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW"
|
||||
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
|
||||
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
|
||||
// =============================================================================
|
||||
// Register : PADS_QSPI_GPIO_QSPI_SCLK
|
||||
// Description : Pad control register
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000000ff)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000056)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD
|
||||
// Description : Output disable. Has priority over output enable from
|
||||
// peripherals
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE
|
||||
// Description : Input enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
|
||||
// Description : Drive strength.
|
||||
// 0x0 -> 2mA
|
||||
// 0x1 -> 4mA
|
||||
// 0x2 -> 8mA
|
||||
// 0x3 -> 12mA
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW"
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE
|
||||
// Description : Pull up enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE
|
||||
// Description : Pull down enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
|
||||
// Description : Enable schmitt trigger
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
|
||||
// Description : Slew rate control. 1 = Fast, 0 = Slow
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : PADS_QSPI_GPIO_QSPI_SD0
|
||||
// Description : Pad control register
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000000ff)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000052)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD0_OD
|
||||
// Description : Output disable. Has priority over output enable from
|
||||
// peripherals
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD0_IE
|
||||
// Description : Input enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
|
||||
// Description : Drive strength.
|
||||
// 0x0 -> 2mA
|
||||
// 0x1 -> 4mA
|
||||
// 0x2 -> 8mA
|
||||
// 0x3 -> 12mA
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW"
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE
|
||||
// Description : Pull up enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE
|
||||
// Description : Pull down enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
|
||||
// Description : Enable schmitt trigger
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
|
||||
// Description : Slew rate control. 1 = Fast, 0 = Slow
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : PADS_QSPI_GPIO_QSPI_SD1
|
||||
// Description : Pad control register
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000000ff)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000052)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD1_OD
|
||||
// Description : Output disable. Has priority over output enable from
|
||||
// peripherals
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD1_IE
|
||||
// Description : Input enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
|
||||
// Description : Drive strength.
|
||||
// 0x0 -> 2mA
|
||||
// 0x1 -> 4mA
|
||||
// 0x2 -> 8mA
|
||||
// 0x3 -> 12mA
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW"
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE
|
||||
// Description : Pull up enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE
|
||||
// Description : Pull down enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
|
||||
// Description : Enable schmitt trigger
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
|
||||
// Description : Slew rate control. 1 = Fast, 0 = Slow
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : PADS_QSPI_GPIO_QSPI_SD2
|
||||
// Description : Pad control register
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000000ff)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x00000052)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD2_OD
|
||||
// Description : Output disable. Has priority over output enable from
|
||||
// peripherals
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD2_IE
|
||||
// Description : Input enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
|
||||
// Description : Drive strength.
|
||||
// 0x0 -> 2mA
|
||||
// 0x1 -> 4mA
|
||||
// 0x2 -> 8mA
|
||||
// 0x3 -> 12mA
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW"
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE
|
||||
// Description : Pull up enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE
|
||||
// Description : Pull down enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
|
||||
// Description : Enable schmitt trigger
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
|
||||
// Description : Slew rate control. 1 = Fast, 0 = Slow
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : PADS_QSPI_GPIO_QSPI_SD3
|
||||
// Description : Pad control register
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000000ff)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x00000052)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD3_OD
|
||||
// Description : Output disable. Has priority over output enable from
|
||||
// peripherals
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD3_IE
|
||||
// Description : Input enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
|
||||
// Description : Drive strength.
|
||||
// 0x0 -> 2mA
|
||||
// 0x1 -> 4mA
|
||||
// 0x2 -> 8mA
|
||||
// 0x3 -> 12mA
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW"
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE
|
||||
// Description : Pull up enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE
|
||||
// Description : Pull down enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
|
||||
// Description : Enable schmitt trigger
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
|
||||
// Description : Slew rate control. 1 = Fast, 0 = Slow
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : PADS_QSPI_GPIO_QSPI_SS
|
||||
// Description : Pad control register
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000000ff)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000005a)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SS_OD
|
||||
// Description : Output disable. Has priority over output enable from
|
||||
// peripherals
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SS_IE
|
||||
// Description : Input enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE
|
||||
// Description : Drive strength.
|
||||
// 0x0 -> 2mA
|
||||
// 0x1 -> 4mA
|
||||
// 0x2 -> 8mA
|
||||
// 0x3 -> 12mA
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW"
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SS_PUE
|
||||
// Description : Pull up enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SS_PDE
|
||||
// Description : Pull down enable
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
|
||||
// Description : Enable schmitt trigger
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
|
||||
// Description : Slew rate control. 1 = Fast, 0 = Slow
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0)
|
||||
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_PADS_QSPI_H
|
||||
|
||||
2678
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h
Normal file
2678
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,137 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : PLL
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_PLL_H
|
||||
#define _HARDWARE_REGS_PLL_H
|
||||
// =============================================================================
|
||||
// Register : PLL_CS
|
||||
// Description : Control and Status
|
||||
// GENERAL CONSTRAINTS:
|
||||
// Reference clock frequency min=5MHz, max=800MHz
|
||||
// Feedback divider min=16, max=320
|
||||
// VCO frequency min=750MHz, max=1600MHz
|
||||
#define PLL_CS_OFFSET _u(0x00000000)
|
||||
#define PLL_CS_BITS _u(0x8000013f)
|
||||
#define PLL_CS_RESET _u(0x00000001)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PLL_CS_LOCK
|
||||
// Description : PLL is locked
|
||||
#define PLL_CS_LOCK_RESET _u(0x0)
|
||||
#define PLL_CS_LOCK_BITS _u(0x80000000)
|
||||
#define PLL_CS_LOCK_MSB _u(31)
|
||||
#define PLL_CS_LOCK_LSB _u(31)
|
||||
#define PLL_CS_LOCK_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PLL_CS_BYPASS
|
||||
// Description : Passes the reference clock to the output instead of the divided
|
||||
// VCO. The VCO continues to run so the user can switch between
|
||||
// the reference clock and the divided VCO but the output will
|
||||
// glitch when doing so.
|
||||
#define PLL_CS_BYPASS_RESET _u(0x0)
|
||||
#define PLL_CS_BYPASS_BITS _u(0x00000100)
|
||||
#define PLL_CS_BYPASS_MSB _u(8)
|
||||
#define PLL_CS_BYPASS_LSB _u(8)
|
||||
#define PLL_CS_BYPASS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PLL_CS_REFDIV
|
||||
// Description : Divides the PLL input reference clock.
|
||||
// Behaviour is undefined for div=0.
|
||||
// PLL output will be unpredictable during refdiv changes, wait
|
||||
// for lock=1 before using it.
|
||||
#define PLL_CS_REFDIV_RESET _u(0x01)
|
||||
#define PLL_CS_REFDIV_BITS _u(0x0000003f)
|
||||
#define PLL_CS_REFDIV_MSB _u(5)
|
||||
#define PLL_CS_REFDIV_LSB _u(0)
|
||||
#define PLL_CS_REFDIV_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : PLL_PWR
|
||||
// Description : Controls the PLL power modes.
|
||||
#define PLL_PWR_OFFSET _u(0x00000004)
|
||||
#define PLL_PWR_BITS _u(0x0000002d)
|
||||
#define PLL_PWR_RESET _u(0x0000002d)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PLL_PWR_VCOPD
|
||||
// Description : PLL VCO powerdown
|
||||
// To save power set high when PLL output not required or
|
||||
// bypass=1.
|
||||
#define PLL_PWR_VCOPD_RESET _u(0x1)
|
||||
#define PLL_PWR_VCOPD_BITS _u(0x00000020)
|
||||
#define PLL_PWR_VCOPD_MSB _u(5)
|
||||
#define PLL_PWR_VCOPD_LSB _u(5)
|
||||
#define PLL_PWR_VCOPD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PLL_PWR_POSTDIVPD
|
||||
// Description : PLL post divider powerdown
|
||||
// To save power set high when PLL output not required or
|
||||
// bypass=1.
|
||||
#define PLL_PWR_POSTDIVPD_RESET _u(0x1)
|
||||
#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008)
|
||||
#define PLL_PWR_POSTDIVPD_MSB _u(3)
|
||||
#define PLL_PWR_POSTDIVPD_LSB _u(3)
|
||||
#define PLL_PWR_POSTDIVPD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PLL_PWR_DSMPD
|
||||
// Description : PLL DSM powerdown
|
||||
// Nothing is achieved by setting this low.
|
||||
#define PLL_PWR_DSMPD_RESET _u(0x1)
|
||||
#define PLL_PWR_DSMPD_BITS _u(0x00000004)
|
||||
#define PLL_PWR_DSMPD_MSB _u(2)
|
||||
#define PLL_PWR_DSMPD_LSB _u(2)
|
||||
#define PLL_PWR_DSMPD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PLL_PWR_PD
|
||||
// Description : PLL powerdown
|
||||
// To save power set high when PLL output not required.
|
||||
#define PLL_PWR_PD_RESET _u(0x1)
|
||||
#define PLL_PWR_PD_BITS _u(0x00000001)
|
||||
#define PLL_PWR_PD_MSB _u(0)
|
||||
#define PLL_PWR_PD_LSB _u(0)
|
||||
#define PLL_PWR_PD_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : PLL_FBDIV_INT
|
||||
// Description : Feedback divisor
|
||||
// (note: this PLL does not support fractional division)
|
||||
// see ctrl reg description for constraints
|
||||
#define PLL_FBDIV_INT_OFFSET _u(0x00000008)
|
||||
#define PLL_FBDIV_INT_BITS _u(0x00000fff)
|
||||
#define PLL_FBDIV_INT_RESET _u(0x00000000)
|
||||
#define PLL_FBDIV_INT_MSB _u(11)
|
||||
#define PLL_FBDIV_INT_LSB _u(0)
|
||||
#define PLL_FBDIV_INT_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : PLL_PRIM
|
||||
// Description : Controls the PLL post dividers for the primary output
|
||||
// (note: this PLL does not have a secondary output)
|
||||
// the primary output is driven from VCO divided by
|
||||
// postdiv1*postdiv2
|
||||
#define PLL_PRIM_OFFSET _u(0x0000000c)
|
||||
#define PLL_PRIM_BITS _u(0x00077000)
|
||||
#define PLL_PRIM_RESET _u(0x00077000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PLL_PRIM_POSTDIV1
|
||||
// Description : divide by 1-7
|
||||
#define PLL_PRIM_POSTDIV1_RESET _u(0x7)
|
||||
#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000)
|
||||
#define PLL_PRIM_POSTDIV1_MSB _u(18)
|
||||
#define PLL_PRIM_POSTDIV1_LSB _u(16)
|
||||
#define PLL_PRIM_POSTDIV1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PLL_PRIM_POSTDIV2
|
||||
// Description : divide by 1-7
|
||||
#define PLL_PRIM_POSTDIV2_RESET _u(0x7)
|
||||
#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000)
|
||||
#define PLL_PRIM_POSTDIV2_MSB _u(14)
|
||||
#define PLL_PRIM_POSTDIV2_LSB _u(12)
|
||||
#define PLL_PRIM_POSTDIV2_ACCESS "RW"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_PLL_H
|
||||
|
||||
|
|
@ -0,0 +1,518 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : PSM
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_PSM_H
|
||||
#define _HARDWARE_REGS_PSM_H
|
||||
// =============================================================================
|
||||
// Register : PSM_FRCE_ON
|
||||
// Description : Force block out of reset (i.e. power it on)
|
||||
#define PSM_FRCE_ON_OFFSET _u(0x00000000)
|
||||
#define PSM_FRCE_ON_BITS _u(0x0001ffff)
|
||||
#define PSM_FRCE_ON_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_PROC1
|
||||
#define PSM_FRCE_ON_PROC1_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_PROC1_BITS _u(0x00010000)
|
||||
#define PSM_FRCE_ON_PROC1_MSB _u(16)
|
||||
#define PSM_FRCE_ON_PROC1_LSB _u(16)
|
||||
#define PSM_FRCE_ON_PROC1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_PROC0
|
||||
#define PSM_FRCE_ON_PROC0_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_PROC0_BITS _u(0x00008000)
|
||||
#define PSM_FRCE_ON_PROC0_MSB _u(15)
|
||||
#define PSM_FRCE_ON_PROC0_LSB _u(15)
|
||||
#define PSM_FRCE_ON_PROC0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_SIO
|
||||
#define PSM_FRCE_ON_SIO_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_SIO_BITS _u(0x00004000)
|
||||
#define PSM_FRCE_ON_SIO_MSB _u(14)
|
||||
#define PSM_FRCE_ON_SIO_LSB _u(14)
|
||||
#define PSM_FRCE_ON_SIO_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET
|
||||
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
|
||||
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13)
|
||||
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB _u(13)
|
||||
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_XIP
|
||||
#define PSM_FRCE_ON_XIP_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_XIP_BITS _u(0x00001000)
|
||||
#define PSM_FRCE_ON_XIP_MSB _u(12)
|
||||
#define PSM_FRCE_ON_XIP_LSB _u(12)
|
||||
#define PSM_FRCE_ON_XIP_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_SRAM5
|
||||
#define PSM_FRCE_ON_SRAM5_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800)
|
||||
#define PSM_FRCE_ON_SRAM5_MSB _u(11)
|
||||
#define PSM_FRCE_ON_SRAM5_LSB _u(11)
|
||||
#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_SRAM4
|
||||
#define PSM_FRCE_ON_SRAM4_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400)
|
||||
#define PSM_FRCE_ON_SRAM4_MSB _u(10)
|
||||
#define PSM_FRCE_ON_SRAM4_LSB _u(10)
|
||||
#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_SRAM3
|
||||
#define PSM_FRCE_ON_SRAM3_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200)
|
||||
#define PSM_FRCE_ON_SRAM3_MSB _u(9)
|
||||
#define PSM_FRCE_ON_SRAM3_LSB _u(9)
|
||||
#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_SRAM2
|
||||
#define PSM_FRCE_ON_SRAM2_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100)
|
||||
#define PSM_FRCE_ON_SRAM2_MSB _u(8)
|
||||
#define PSM_FRCE_ON_SRAM2_LSB _u(8)
|
||||
#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_SRAM1
|
||||
#define PSM_FRCE_ON_SRAM1_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080)
|
||||
#define PSM_FRCE_ON_SRAM1_MSB _u(7)
|
||||
#define PSM_FRCE_ON_SRAM1_LSB _u(7)
|
||||
#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_SRAM0
|
||||
#define PSM_FRCE_ON_SRAM0_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040)
|
||||
#define PSM_FRCE_ON_SRAM0_MSB _u(6)
|
||||
#define PSM_FRCE_ON_SRAM0_LSB _u(6)
|
||||
#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_ROM
|
||||
#define PSM_FRCE_ON_ROM_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_ROM_BITS _u(0x00000020)
|
||||
#define PSM_FRCE_ON_ROM_MSB _u(5)
|
||||
#define PSM_FRCE_ON_ROM_LSB _u(5)
|
||||
#define PSM_FRCE_ON_ROM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_BUSFABRIC
|
||||
#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010)
|
||||
#define PSM_FRCE_ON_BUSFABRIC_MSB _u(4)
|
||||
#define PSM_FRCE_ON_BUSFABRIC_LSB _u(4)
|
||||
#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_RESETS
|
||||
#define PSM_FRCE_ON_RESETS_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_RESETS_BITS _u(0x00000008)
|
||||
#define PSM_FRCE_ON_RESETS_MSB _u(3)
|
||||
#define PSM_FRCE_ON_RESETS_LSB _u(3)
|
||||
#define PSM_FRCE_ON_RESETS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_CLOCKS
|
||||
#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004)
|
||||
#define PSM_FRCE_ON_CLOCKS_MSB _u(2)
|
||||
#define PSM_FRCE_ON_CLOCKS_LSB _u(2)
|
||||
#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_XOSC
|
||||
#define PSM_FRCE_ON_XOSC_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_XOSC_BITS _u(0x00000002)
|
||||
#define PSM_FRCE_ON_XOSC_MSB _u(1)
|
||||
#define PSM_FRCE_ON_XOSC_LSB _u(1)
|
||||
#define PSM_FRCE_ON_XOSC_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_ON_ROSC
|
||||
#define PSM_FRCE_ON_ROSC_RESET _u(0x0)
|
||||
#define PSM_FRCE_ON_ROSC_BITS _u(0x00000001)
|
||||
#define PSM_FRCE_ON_ROSC_MSB _u(0)
|
||||
#define PSM_FRCE_ON_ROSC_LSB _u(0)
|
||||
#define PSM_FRCE_ON_ROSC_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : PSM_FRCE_OFF
|
||||
// Description : Force into reset (i.e. power it off)
|
||||
#define PSM_FRCE_OFF_OFFSET _u(0x00000004)
|
||||
#define PSM_FRCE_OFF_BITS _u(0x0001ffff)
|
||||
#define PSM_FRCE_OFF_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_PROC1
|
||||
#define PSM_FRCE_OFF_PROC1_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000)
|
||||
#define PSM_FRCE_OFF_PROC1_MSB _u(16)
|
||||
#define PSM_FRCE_OFF_PROC1_LSB _u(16)
|
||||
#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_PROC0
|
||||
#define PSM_FRCE_OFF_PROC0_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000)
|
||||
#define PSM_FRCE_OFF_PROC0_MSB _u(15)
|
||||
#define PSM_FRCE_OFF_PROC0_LSB _u(15)
|
||||
#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_SIO
|
||||
#define PSM_FRCE_OFF_SIO_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_SIO_BITS _u(0x00004000)
|
||||
#define PSM_FRCE_OFF_SIO_MSB _u(14)
|
||||
#define PSM_FRCE_OFF_SIO_LSB _u(14)
|
||||
#define PSM_FRCE_OFF_SIO_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET
|
||||
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
|
||||
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13)
|
||||
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB _u(13)
|
||||
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_XIP
|
||||
#define PSM_FRCE_OFF_XIP_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_XIP_BITS _u(0x00001000)
|
||||
#define PSM_FRCE_OFF_XIP_MSB _u(12)
|
||||
#define PSM_FRCE_OFF_XIP_LSB _u(12)
|
||||
#define PSM_FRCE_OFF_XIP_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_SRAM5
|
||||
#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800)
|
||||
#define PSM_FRCE_OFF_SRAM5_MSB _u(11)
|
||||
#define PSM_FRCE_OFF_SRAM5_LSB _u(11)
|
||||
#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_SRAM4
|
||||
#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400)
|
||||
#define PSM_FRCE_OFF_SRAM4_MSB _u(10)
|
||||
#define PSM_FRCE_OFF_SRAM4_LSB _u(10)
|
||||
#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_SRAM3
|
||||
#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200)
|
||||
#define PSM_FRCE_OFF_SRAM3_MSB _u(9)
|
||||
#define PSM_FRCE_OFF_SRAM3_LSB _u(9)
|
||||
#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_SRAM2
|
||||
#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100)
|
||||
#define PSM_FRCE_OFF_SRAM2_MSB _u(8)
|
||||
#define PSM_FRCE_OFF_SRAM2_LSB _u(8)
|
||||
#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_SRAM1
|
||||
#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080)
|
||||
#define PSM_FRCE_OFF_SRAM1_MSB _u(7)
|
||||
#define PSM_FRCE_OFF_SRAM1_LSB _u(7)
|
||||
#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_SRAM0
|
||||
#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040)
|
||||
#define PSM_FRCE_OFF_SRAM0_MSB _u(6)
|
||||
#define PSM_FRCE_OFF_SRAM0_LSB _u(6)
|
||||
#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_ROM
|
||||
#define PSM_FRCE_OFF_ROM_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_ROM_BITS _u(0x00000020)
|
||||
#define PSM_FRCE_OFF_ROM_MSB _u(5)
|
||||
#define PSM_FRCE_OFF_ROM_LSB _u(5)
|
||||
#define PSM_FRCE_OFF_ROM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_BUSFABRIC
|
||||
#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010)
|
||||
#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4)
|
||||
#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(4)
|
||||
#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_RESETS
|
||||
#define PSM_FRCE_OFF_RESETS_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008)
|
||||
#define PSM_FRCE_OFF_RESETS_MSB _u(3)
|
||||
#define PSM_FRCE_OFF_RESETS_LSB _u(3)
|
||||
#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_CLOCKS
|
||||
#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004)
|
||||
#define PSM_FRCE_OFF_CLOCKS_MSB _u(2)
|
||||
#define PSM_FRCE_OFF_CLOCKS_LSB _u(2)
|
||||
#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_XOSC
|
||||
#define PSM_FRCE_OFF_XOSC_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002)
|
||||
#define PSM_FRCE_OFF_XOSC_MSB _u(1)
|
||||
#define PSM_FRCE_OFF_XOSC_LSB _u(1)
|
||||
#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_FRCE_OFF_ROSC
|
||||
#define PSM_FRCE_OFF_ROSC_RESET _u(0x0)
|
||||
#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001)
|
||||
#define PSM_FRCE_OFF_ROSC_MSB _u(0)
|
||||
#define PSM_FRCE_OFF_ROSC_LSB _u(0)
|
||||
#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : PSM_WDSEL
|
||||
// Description : Set to 1 if this peripheral should be reset when the watchdog
|
||||
// fires.
|
||||
#define PSM_WDSEL_OFFSET _u(0x00000008)
|
||||
#define PSM_WDSEL_BITS _u(0x0001ffff)
|
||||
#define PSM_WDSEL_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_PROC1
|
||||
#define PSM_WDSEL_PROC1_RESET _u(0x0)
|
||||
#define PSM_WDSEL_PROC1_BITS _u(0x00010000)
|
||||
#define PSM_WDSEL_PROC1_MSB _u(16)
|
||||
#define PSM_WDSEL_PROC1_LSB _u(16)
|
||||
#define PSM_WDSEL_PROC1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_PROC0
|
||||
#define PSM_WDSEL_PROC0_RESET _u(0x0)
|
||||
#define PSM_WDSEL_PROC0_BITS _u(0x00008000)
|
||||
#define PSM_WDSEL_PROC0_MSB _u(15)
|
||||
#define PSM_WDSEL_PROC0_LSB _u(15)
|
||||
#define PSM_WDSEL_PROC0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_SIO
|
||||
#define PSM_WDSEL_SIO_RESET _u(0x0)
|
||||
#define PSM_WDSEL_SIO_BITS _u(0x00004000)
|
||||
#define PSM_WDSEL_SIO_MSB _u(14)
|
||||
#define PSM_WDSEL_SIO_LSB _u(14)
|
||||
#define PSM_WDSEL_SIO_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_VREG_AND_CHIP_RESET
|
||||
#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0)
|
||||
#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
|
||||
#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13)
|
||||
#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB _u(13)
|
||||
#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_XIP
|
||||
#define PSM_WDSEL_XIP_RESET _u(0x0)
|
||||
#define PSM_WDSEL_XIP_BITS _u(0x00001000)
|
||||
#define PSM_WDSEL_XIP_MSB _u(12)
|
||||
#define PSM_WDSEL_XIP_LSB _u(12)
|
||||
#define PSM_WDSEL_XIP_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_SRAM5
|
||||
#define PSM_WDSEL_SRAM5_RESET _u(0x0)
|
||||
#define PSM_WDSEL_SRAM5_BITS _u(0x00000800)
|
||||
#define PSM_WDSEL_SRAM5_MSB _u(11)
|
||||
#define PSM_WDSEL_SRAM5_LSB _u(11)
|
||||
#define PSM_WDSEL_SRAM5_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_SRAM4
|
||||
#define PSM_WDSEL_SRAM4_RESET _u(0x0)
|
||||
#define PSM_WDSEL_SRAM4_BITS _u(0x00000400)
|
||||
#define PSM_WDSEL_SRAM4_MSB _u(10)
|
||||
#define PSM_WDSEL_SRAM4_LSB _u(10)
|
||||
#define PSM_WDSEL_SRAM4_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_SRAM3
|
||||
#define PSM_WDSEL_SRAM3_RESET _u(0x0)
|
||||
#define PSM_WDSEL_SRAM3_BITS _u(0x00000200)
|
||||
#define PSM_WDSEL_SRAM3_MSB _u(9)
|
||||
#define PSM_WDSEL_SRAM3_LSB _u(9)
|
||||
#define PSM_WDSEL_SRAM3_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_SRAM2
|
||||
#define PSM_WDSEL_SRAM2_RESET _u(0x0)
|
||||
#define PSM_WDSEL_SRAM2_BITS _u(0x00000100)
|
||||
#define PSM_WDSEL_SRAM2_MSB _u(8)
|
||||
#define PSM_WDSEL_SRAM2_LSB _u(8)
|
||||
#define PSM_WDSEL_SRAM2_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_SRAM1
|
||||
#define PSM_WDSEL_SRAM1_RESET _u(0x0)
|
||||
#define PSM_WDSEL_SRAM1_BITS _u(0x00000080)
|
||||
#define PSM_WDSEL_SRAM1_MSB _u(7)
|
||||
#define PSM_WDSEL_SRAM1_LSB _u(7)
|
||||
#define PSM_WDSEL_SRAM1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_SRAM0
|
||||
#define PSM_WDSEL_SRAM0_RESET _u(0x0)
|
||||
#define PSM_WDSEL_SRAM0_BITS _u(0x00000040)
|
||||
#define PSM_WDSEL_SRAM0_MSB _u(6)
|
||||
#define PSM_WDSEL_SRAM0_LSB _u(6)
|
||||
#define PSM_WDSEL_SRAM0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_ROM
|
||||
#define PSM_WDSEL_ROM_RESET _u(0x0)
|
||||
#define PSM_WDSEL_ROM_BITS _u(0x00000020)
|
||||
#define PSM_WDSEL_ROM_MSB _u(5)
|
||||
#define PSM_WDSEL_ROM_LSB _u(5)
|
||||
#define PSM_WDSEL_ROM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_BUSFABRIC
|
||||
#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0)
|
||||
#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010)
|
||||
#define PSM_WDSEL_BUSFABRIC_MSB _u(4)
|
||||
#define PSM_WDSEL_BUSFABRIC_LSB _u(4)
|
||||
#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_RESETS
|
||||
#define PSM_WDSEL_RESETS_RESET _u(0x0)
|
||||
#define PSM_WDSEL_RESETS_BITS _u(0x00000008)
|
||||
#define PSM_WDSEL_RESETS_MSB _u(3)
|
||||
#define PSM_WDSEL_RESETS_LSB _u(3)
|
||||
#define PSM_WDSEL_RESETS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_CLOCKS
|
||||
#define PSM_WDSEL_CLOCKS_RESET _u(0x0)
|
||||
#define PSM_WDSEL_CLOCKS_BITS _u(0x00000004)
|
||||
#define PSM_WDSEL_CLOCKS_MSB _u(2)
|
||||
#define PSM_WDSEL_CLOCKS_LSB _u(2)
|
||||
#define PSM_WDSEL_CLOCKS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_XOSC
|
||||
#define PSM_WDSEL_XOSC_RESET _u(0x0)
|
||||
#define PSM_WDSEL_XOSC_BITS _u(0x00000002)
|
||||
#define PSM_WDSEL_XOSC_MSB _u(1)
|
||||
#define PSM_WDSEL_XOSC_LSB _u(1)
|
||||
#define PSM_WDSEL_XOSC_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_WDSEL_ROSC
|
||||
#define PSM_WDSEL_ROSC_RESET _u(0x0)
|
||||
#define PSM_WDSEL_ROSC_BITS _u(0x00000001)
|
||||
#define PSM_WDSEL_ROSC_MSB _u(0)
|
||||
#define PSM_WDSEL_ROSC_LSB _u(0)
|
||||
#define PSM_WDSEL_ROSC_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : PSM_DONE
|
||||
// Description : Indicates the peripheral's registers are ready to access.
|
||||
#define PSM_DONE_OFFSET _u(0x0000000c)
|
||||
#define PSM_DONE_BITS _u(0x0001ffff)
|
||||
#define PSM_DONE_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_PROC1
|
||||
#define PSM_DONE_PROC1_RESET _u(0x0)
|
||||
#define PSM_DONE_PROC1_BITS _u(0x00010000)
|
||||
#define PSM_DONE_PROC1_MSB _u(16)
|
||||
#define PSM_DONE_PROC1_LSB _u(16)
|
||||
#define PSM_DONE_PROC1_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_PROC0
|
||||
#define PSM_DONE_PROC0_RESET _u(0x0)
|
||||
#define PSM_DONE_PROC0_BITS _u(0x00008000)
|
||||
#define PSM_DONE_PROC0_MSB _u(15)
|
||||
#define PSM_DONE_PROC0_LSB _u(15)
|
||||
#define PSM_DONE_PROC0_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_SIO
|
||||
#define PSM_DONE_SIO_RESET _u(0x0)
|
||||
#define PSM_DONE_SIO_BITS _u(0x00004000)
|
||||
#define PSM_DONE_SIO_MSB _u(14)
|
||||
#define PSM_DONE_SIO_LSB _u(14)
|
||||
#define PSM_DONE_SIO_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_VREG_AND_CHIP_RESET
|
||||
#define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0)
|
||||
#define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
|
||||
#define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13)
|
||||
#define PSM_DONE_VREG_AND_CHIP_RESET_LSB _u(13)
|
||||
#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_XIP
|
||||
#define PSM_DONE_XIP_RESET _u(0x0)
|
||||
#define PSM_DONE_XIP_BITS _u(0x00001000)
|
||||
#define PSM_DONE_XIP_MSB _u(12)
|
||||
#define PSM_DONE_XIP_LSB _u(12)
|
||||
#define PSM_DONE_XIP_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_SRAM5
|
||||
#define PSM_DONE_SRAM5_RESET _u(0x0)
|
||||
#define PSM_DONE_SRAM5_BITS _u(0x00000800)
|
||||
#define PSM_DONE_SRAM5_MSB _u(11)
|
||||
#define PSM_DONE_SRAM5_LSB _u(11)
|
||||
#define PSM_DONE_SRAM5_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_SRAM4
|
||||
#define PSM_DONE_SRAM4_RESET _u(0x0)
|
||||
#define PSM_DONE_SRAM4_BITS _u(0x00000400)
|
||||
#define PSM_DONE_SRAM4_MSB _u(10)
|
||||
#define PSM_DONE_SRAM4_LSB _u(10)
|
||||
#define PSM_DONE_SRAM4_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_SRAM3
|
||||
#define PSM_DONE_SRAM3_RESET _u(0x0)
|
||||
#define PSM_DONE_SRAM3_BITS _u(0x00000200)
|
||||
#define PSM_DONE_SRAM3_MSB _u(9)
|
||||
#define PSM_DONE_SRAM3_LSB _u(9)
|
||||
#define PSM_DONE_SRAM3_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_SRAM2
|
||||
#define PSM_DONE_SRAM2_RESET _u(0x0)
|
||||
#define PSM_DONE_SRAM2_BITS _u(0x00000100)
|
||||
#define PSM_DONE_SRAM2_MSB _u(8)
|
||||
#define PSM_DONE_SRAM2_LSB _u(8)
|
||||
#define PSM_DONE_SRAM2_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_SRAM1
|
||||
#define PSM_DONE_SRAM1_RESET _u(0x0)
|
||||
#define PSM_DONE_SRAM1_BITS _u(0x00000080)
|
||||
#define PSM_DONE_SRAM1_MSB _u(7)
|
||||
#define PSM_DONE_SRAM1_LSB _u(7)
|
||||
#define PSM_DONE_SRAM1_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_SRAM0
|
||||
#define PSM_DONE_SRAM0_RESET _u(0x0)
|
||||
#define PSM_DONE_SRAM0_BITS _u(0x00000040)
|
||||
#define PSM_DONE_SRAM0_MSB _u(6)
|
||||
#define PSM_DONE_SRAM0_LSB _u(6)
|
||||
#define PSM_DONE_SRAM0_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_ROM
|
||||
#define PSM_DONE_ROM_RESET _u(0x0)
|
||||
#define PSM_DONE_ROM_BITS _u(0x00000020)
|
||||
#define PSM_DONE_ROM_MSB _u(5)
|
||||
#define PSM_DONE_ROM_LSB _u(5)
|
||||
#define PSM_DONE_ROM_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_BUSFABRIC
|
||||
#define PSM_DONE_BUSFABRIC_RESET _u(0x0)
|
||||
#define PSM_DONE_BUSFABRIC_BITS _u(0x00000010)
|
||||
#define PSM_DONE_BUSFABRIC_MSB _u(4)
|
||||
#define PSM_DONE_BUSFABRIC_LSB _u(4)
|
||||
#define PSM_DONE_BUSFABRIC_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_RESETS
|
||||
#define PSM_DONE_RESETS_RESET _u(0x0)
|
||||
#define PSM_DONE_RESETS_BITS _u(0x00000008)
|
||||
#define PSM_DONE_RESETS_MSB _u(3)
|
||||
#define PSM_DONE_RESETS_LSB _u(3)
|
||||
#define PSM_DONE_RESETS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_CLOCKS
|
||||
#define PSM_DONE_CLOCKS_RESET _u(0x0)
|
||||
#define PSM_DONE_CLOCKS_BITS _u(0x00000004)
|
||||
#define PSM_DONE_CLOCKS_MSB _u(2)
|
||||
#define PSM_DONE_CLOCKS_LSB _u(2)
|
||||
#define PSM_DONE_CLOCKS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_XOSC
|
||||
#define PSM_DONE_XOSC_RESET _u(0x0)
|
||||
#define PSM_DONE_XOSC_BITS _u(0x00000002)
|
||||
#define PSM_DONE_XOSC_MSB _u(1)
|
||||
#define PSM_DONE_XOSC_LSB _u(1)
|
||||
#define PSM_DONE_XOSC_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : PSM_DONE_ROSC
|
||||
#define PSM_DONE_ROSC_RESET _u(0x0)
|
||||
#define PSM_DONE_ROSC_BITS _u(0x00000001)
|
||||
#define PSM_DONE_ROSC_MSB _u(0)
|
||||
#define PSM_DONE_ROSC_LSB _u(0)
|
||||
#define PSM_DONE_ROSC_ACCESS "RO"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_PSM_H
|
||||
|
||||
1420
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h
Normal file
1420
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,564 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : RESETS
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_RESETS_H
|
||||
#define _HARDWARE_REGS_RESETS_H
|
||||
// =============================================================================
|
||||
// Register : RESETS_RESET
|
||||
// Description : Reset control. If a bit is set it means the peripheral is in
|
||||
// reset. 0 means the peripheral's reset is deasserted.
|
||||
#define RESETS_RESET_OFFSET _u(0x00000000)
|
||||
#define RESETS_RESET_BITS _u(0x01ffffff)
|
||||
#define RESETS_RESET_RESET _u(0x01ffffff)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_USBCTRL
|
||||
#define RESETS_RESET_USBCTRL_RESET _u(0x1)
|
||||
#define RESETS_RESET_USBCTRL_BITS _u(0x01000000)
|
||||
#define RESETS_RESET_USBCTRL_MSB _u(24)
|
||||
#define RESETS_RESET_USBCTRL_LSB _u(24)
|
||||
#define RESETS_RESET_USBCTRL_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_UART1
|
||||
#define RESETS_RESET_UART1_RESET _u(0x1)
|
||||
#define RESETS_RESET_UART1_BITS _u(0x00800000)
|
||||
#define RESETS_RESET_UART1_MSB _u(23)
|
||||
#define RESETS_RESET_UART1_LSB _u(23)
|
||||
#define RESETS_RESET_UART1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_UART0
|
||||
#define RESETS_RESET_UART0_RESET _u(0x1)
|
||||
#define RESETS_RESET_UART0_BITS _u(0x00400000)
|
||||
#define RESETS_RESET_UART0_MSB _u(22)
|
||||
#define RESETS_RESET_UART0_LSB _u(22)
|
||||
#define RESETS_RESET_UART0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_TIMER
|
||||
#define RESETS_RESET_TIMER_RESET _u(0x1)
|
||||
#define RESETS_RESET_TIMER_BITS _u(0x00200000)
|
||||
#define RESETS_RESET_TIMER_MSB _u(21)
|
||||
#define RESETS_RESET_TIMER_LSB _u(21)
|
||||
#define RESETS_RESET_TIMER_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_TBMAN
|
||||
#define RESETS_RESET_TBMAN_RESET _u(0x1)
|
||||
#define RESETS_RESET_TBMAN_BITS _u(0x00100000)
|
||||
#define RESETS_RESET_TBMAN_MSB _u(20)
|
||||
#define RESETS_RESET_TBMAN_LSB _u(20)
|
||||
#define RESETS_RESET_TBMAN_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_SYSINFO
|
||||
#define RESETS_RESET_SYSINFO_RESET _u(0x1)
|
||||
#define RESETS_RESET_SYSINFO_BITS _u(0x00080000)
|
||||
#define RESETS_RESET_SYSINFO_MSB _u(19)
|
||||
#define RESETS_RESET_SYSINFO_LSB _u(19)
|
||||
#define RESETS_RESET_SYSINFO_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_SYSCFG
|
||||
#define RESETS_RESET_SYSCFG_RESET _u(0x1)
|
||||
#define RESETS_RESET_SYSCFG_BITS _u(0x00040000)
|
||||
#define RESETS_RESET_SYSCFG_MSB _u(18)
|
||||
#define RESETS_RESET_SYSCFG_LSB _u(18)
|
||||
#define RESETS_RESET_SYSCFG_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_SPI1
|
||||
#define RESETS_RESET_SPI1_RESET _u(0x1)
|
||||
#define RESETS_RESET_SPI1_BITS _u(0x00020000)
|
||||
#define RESETS_RESET_SPI1_MSB _u(17)
|
||||
#define RESETS_RESET_SPI1_LSB _u(17)
|
||||
#define RESETS_RESET_SPI1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_SPI0
|
||||
#define RESETS_RESET_SPI0_RESET _u(0x1)
|
||||
#define RESETS_RESET_SPI0_BITS _u(0x00010000)
|
||||
#define RESETS_RESET_SPI0_MSB _u(16)
|
||||
#define RESETS_RESET_SPI0_LSB _u(16)
|
||||
#define RESETS_RESET_SPI0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_RTC
|
||||
#define RESETS_RESET_RTC_RESET _u(0x1)
|
||||
#define RESETS_RESET_RTC_BITS _u(0x00008000)
|
||||
#define RESETS_RESET_RTC_MSB _u(15)
|
||||
#define RESETS_RESET_RTC_LSB _u(15)
|
||||
#define RESETS_RESET_RTC_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_PWM
|
||||
#define RESETS_RESET_PWM_RESET _u(0x1)
|
||||
#define RESETS_RESET_PWM_BITS _u(0x00004000)
|
||||
#define RESETS_RESET_PWM_MSB _u(14)
|
||||
#define RESETS_RESET_PWM_LSB _u(14)
|
||||
#define RESETS_RESET_PWM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_PLL_USB
|
||||
#define RESETS_RESET_PLL_USB_RESET _u(0x1)
|
||||
#define RESETS_RESET_PLL_USB_BITS _u(0x00002000)
|
||||
#define RESETS_RESET_PLL_USB_MSB _u(13)
|
||||
#define RESETS_RESET_PLL_USB_LSB _u(13)
|
||||
#define RESETS_RESET_PLL_USB_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_PLL_SYS
|
||||
#define RESETS_RESET_PLL_SYS_RESET _u(0x1)
|
||||
#define RESETS_RESET_PLL_SYS_BITS _u(0x00001000)
|
||||
#define RESETS_RESET_PLL_SYS_MSB _u(12)
|
||||
#define RESETS_RESET_PLL_SYS_LSB _u(12)
|
||||
#define RESETS_RESET_PLL_SYS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_PIO1
|
||||
#define RESETS_RESET_PIO1_RESET _u(0x1)
|
||||
#define RESETS_RESET_PIO1_BITS _u(0x00000800)
|
||||
#define RESETS_RESET_PIO1_MSB _u(11)
|
||||
#define RESETS_RESET_PIO1_LSB _u(11)
|
||||
#define RESETS_RESET_PIO1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_PIO0
|
||||
#define RESETS_RESET_PIO0_RESET _u(0x1)
|
||||
#define RESETS_RESET_PIO0_BITS _u(0x00000400)
|
||||
#define RESETS_RESET_PIO0_MSB _u(10)
|
||||
#define RESETS_RESET_PIO0_LSB _u(10)
|
||||
#define RESETS_RESET_PIO0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_PADS_QSPI
|
||||
#define RESETS_RESET_PADS_QSPI_RESET _u(0x1)
|
||||
#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200)
|
||||
#define RESETS_RESET_PADS_QSPI_MSB _u(9)
|
||||
#define RESETS_RESET_PADS_QSPI_LSB _u(9)
|
||||
#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_PADS_BANK0
|
||||
#define RESETS_RESET_PADS_BANK0_RESET _u(0x1)
|
||||
#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100)
|
||||
#define RESETS_RESET_PADS_BANK0_MSB _u(8)
|
||||
#define RESETS_RESET_PADS_BANK0_LSB _u(8)
|
||||
#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_JTAG
|
||||
#define RESETS_RESET_JTAG_RESET _u(0x1)
|
||||
#define RESETS_RESET_JTAG_BITS _u(0x00000080)
|
||||
#define RESETS_RESET_JTAG_MSB _u(7)
|
||||
#define RESETS_RESET_JTAG_LSB _u(7)
|
||||
#define RESETS_RESET_JTAG_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_IO_QSPI
|
||||
#define RESETS_RESET_IO_QSPI_RESET _u(0x1)
|
||||
#define RESETS_RESET_IO_QSPI_BITS _u(0x00000040)
|
||||
#define RESETS_RESET_IO_QSPI_MSB _u(6)
|
||||
#define RESETS_RESET_IO_QSPI_LSB _u(6)
|
||||
#define RESETS_RESET_IO_QSPI_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_IO_BANK0
|
||||
#define RESETS_RESET_IO_BANK0_RESET _u(0x1)
|
||||
#define RESETS_RESET_IO_BANK0_BITS _u(0x00000020)
|
||||
#define RESETS_RESET_IO_BANK0_MSB _u(5)
|
||||
#define RESETS_RESET_IO_BANK0_LSB _u(5)
|
||||
#define RESETS_RESET_IO_BANK0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_I2C1
|
||||
#define RESETS_RESET_I2C1_RESET _u(0x1)
|
||||
#define RESETS_RESET_I2C1_BITS _u(0x00000010)
|
||||
#define RESETS_RESET_I2C1_MSB _u(4)
|
||||
#define RESETS_RESET_I2C1_LSB _u(4)
|
||||
#define RESETS_RESET_I2C1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_I2C0
|
||||
#define RESETS_RESET_I2C0_RESET _u(0x1)
|
||||
#define RESETS_RESET_I2C0_BITS _u(0x00000008)
|
||||
#define RESETS_RESET_I2C0_MSB _u(3)
|
||||
#define RESETS_RESET_I2C0_LSB _u(3)
|
||||
#define RESETS_RESET_I2C0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DMA
|
||||
#define RESETS_RESET_DMA_RESET _u(0x1)
|
||||
#define RESETS_RESET_DMA_BITS _u(0x00000004)
|
||||
#define RESETS_RESET_DMA_MSB _u(2)
|
||||
#define RESETS_RESET_DMA_LSB _u(2)
|
||||
#define RESETS_RESET_DMA_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_BUSCTRL
|
||||
#define RESETS_RESET_BUSCTRL_RESET _u(0x1)
|
||||
#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002)
|
||||
#define RESETS_RESET_BUSCTRL_MSB _u(1)
|
||||
#define RESETS_RESET_BUSCTRL_LSB _u(1)
|
||||
#define RESETS_RESET_BUSCTRL_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_ADC
|
||||
#define RESETS_RESET_ADC_RESET _u(0x1)
|
||||
#define RESETS_RESET_ADC_BITS _u(0x00000001)
|
||||
#define RESETS_RESET_ADC_MSB _u(0)
|
||||
#define RESETS_RESET_ADC_LSB _u(0)
|
||||
#define RESETS_RESET_ADC_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : RESETS_WDSEL
|
||||
// Description : Watchdog select. If a bit is set then the watchdog will reset
|
||||
// this peripheral when the watchdog fires.
|
||||
#define RESETS_WDSEL_OFFSET _u(0x00000004)
|
||||
#define RESETS_WDSEL_BITS _u(0x01ffffff)
|
||||
#define RESETS_WDSEL_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_USBCTRL
|
||||
#define RESETS_WDSEL_USBCTRL_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000)
|
||||
#define RESETS_WDSEL_USBCTRL_MSB _u(24)
|
||||
#define RESETS_WDSEL_USBCTRL_LSB _u(24)
|
||||
#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_UART1
|
||||
#define RESETS_WDSEL_UART1_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_UART1_BITS _u(0x00800000)
|
||||
#define RESETS_WDSEL_UART1_MSB _u(23)
|
||||
#define RESETS_WDSEL_UART1_LSB _u(23)
|
||||
#define RESETS_WDSEL_UART1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_UART0
|
||||
#define RESETS_WDSEL_UART0_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_UART0_BITS _u(0x00400000)
|
||||
#define RESETS_WDSEL_UART0_MSB _u(22)
|
||||
#define RESETS_WDSEL_UART0_LSB _u(22)
|
||||
#define RESETS_WDSEL_UART0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_TIMER
|
||||
#define RESETS_WDSEL_TIMER_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_TIMER_BITS _u(0x00200000)
|
||||
#define RESETS_WDSEL_TIMER_MSB _u(21)
|
||||
#define RESETS_WDSEL_TIMER_LSB _u(21)
|
||||
#define RESETS_WDSEL_TIMER_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_TBMAN
|
||||
#define RESETS_WDSEL_TBMAN_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_TBMAN_BITS _u(0x00100000)
|
||||
#define RESETS_WDSEL_TBMAN_MSB _u(20)
|
||||
#define RESETS_WDSEL_TBMAN_LSB _u(20)
|
||||
#define RESETS_WDSEL_TBMAN_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_SYSINFO
|
||||
#define RESETS_WDSEL_SYSINFO_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000)
|
||||
#define RESETS_WDSEL_SYSINFO_MSB _u(19)
|
||||
#define RESETS_WDSEL_SYSINFO_LSB _u(19)
|
||||
#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_SYSCFG
|
||||
#define RESETS_WDSEL_SYSCFG_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000)
|
||||
#define RESETS_WDSEL_SYSCFG_MSB _u(18)
|
||||
#define RESETS_WDSEL_SYSCFG_LSB _u(18)
|
||||
#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_SPI1
|
||||
#define RESETS_WDSEL_SPI1_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_SPI1_BITS _u(0x00020000)
|
||||
#define RESETS_WDSEL_SPI1_MSB _u(17)
|
||||
#define RESETS_WDSEL_SPI1_LSB _u(17)
|
||||
#define RESETS_WDSEL_SPI1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_SPI0
|
||||
#define RESETS_WDSEL_SPI0_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_SPI0_BITS _u(0x00010000)
|
||||
#define RESETS_WDSEL_SPI0_MSB _u(16)
|
||||
#define RESETS_WDSEL_SPI0_LSB _u(16)
|
||||
#define RESETS_WDSEL_SPI0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_RTC
|
||||
#define RESETS_WDSEL_RTC_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_RTC_BITS _u(0x00008000)
|
||||
#define RESETS_WDSEL_RTC_MSB _u(15)
|
||||
#define RESETS_WDSEL_RTC_LSB _u(15)
|
||||
#define RESETS_WDSEL_RTC_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_PWM
|
||||
#define RESETS_WDSEL_PWM_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_PWM_BITS _u(0x00004000)
|
||||
#define RESETS_WDSEL_PWM_MSB _u(14)
|
||||
#define RESETS_WDSEL_PWM_LSB _u(14)
|
||||
#define RESETS_WDSEL_PWM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_PLL_USB
|
||||
#define RESETS_WDSEL_PLL_USB_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000)
|
||||
#define RESETS_WDSEL_PLL_USB_MSB _u(13)
|
||||
#define RESETS_WDSEL_PLL_USB_LSB _u(13)
|
||||
#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_PLL_SYS
|
||||
#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000)
|
||||
#define RESETS_WDSEL_PLL_SYS_MSB _u(12)
|
||||
#define RESETS_WDSEL_PLL_SYS_LSB _u(12)
|
||||
#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_PIO1
|
||||
#define RESETS_WDSEL_PIO1_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_PIO1_BITS _u(0x00000800)
|
||||
#define RESETS_WDSEL_PIO1_MSB _u(11)
|
||||
#define RESETS_WDSEL_PIO1_LSB _u(11)
|
||||
#define RESETS_WDSEL_PIO1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_PIO0
|
||||
#define RESETS_WDSEL_PIO0_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_PIO0_BITS _u(0x00000400)
|
||||
#define RESETS_WDSEL_PIO0_MSB _u(10)
|
||||
#define RESETS_WDSEL_PIO0_LSB _u(10)
|
||||
#define RESETS_WDSEL_PIO0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_PADS_QSPI
|
||||
#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200)
|
||||
#define RESETS_WDSEL_PADS_QSPI_MSB _u(9)
|
||||
#define RESETS_WDSEL_PADS_QSPI_LSB _u(9)
|
||||
#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_PADS_BANK0
|
||||
#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100)
|
||||
#define RESETS_WDSEL_PADS_BANK0_MSB _u(8)
|
||||
#define RESETS_WDSEL_PADS_BANK0_LSB _u(8)
|
||||
#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_JTAG
|
||||
#define RESETS_WDSEL_JTAG_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_JTAG_BITS _u(0x00000080)
|
||||
#define RESETS_WDSEL_JTAG_MSB _u(7)
|
||||
#define RESETS_WDSEL_JTAG_LSB _u(7)
|
||||
#define RESETS_WDSEL_JTAG_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_IO_QSPI
|
||||
#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040)
|
||||
#define RESETS_WDSEL_IO_QSPI_MSB _u(6)
|
||||
#define RESETS_WDSEL_IO_QSPI_LSB _u(6)
|
||||
#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_IO_BANK0
|
||||
#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020)
|
||||
#define RESETS_WDSEL_IO_BANK0_MSB _u(5)
|
||||
#define RESETS_WDSEL_IO_BANK0_LSB _u(5)
|
||||
#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_I2C1
|
||||
#define RESETS_WDSEL_I2C1_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_I2C1_BITS _u(0x00000010)
|
||||
#define RESETS_WDSEL_I2C1_MSB _u(4)
|
||||
#define RESETS_WDSEL_I2C1_LSB _u(4)
|
||||
#define RESETS_WDSEL_I2C1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_I2C0
|
||||
#define RESETS_WDSEL_I2C0_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_I2C0_BITS _u(0x00000008)
|
||||
#define RESETS_WDSEL_I2C0_MSB _u(3)
|
||||
#define RESETS_WDSEL_I2C0_LSB _u(3)
|
||||
#define RESETS_WDSEL_I2C0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_DMA
|
||||
#define RESETS_WDSEL_DMA_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_DMA_BITS _u(0x00000004)
|
||||
#define RESETS_WDSEL_DMA_MSB _u(2)
|
||||
#define RESETS_WDSEL_DMA_LSB _u(2)
|
||||
#define RESETS_WDSEL_DMA_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_BUSCTRL
|
||||
#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002)
|
||||
#define RESETS_WDSEL_BUSCTRL_MSB _u(1)
|
||||
#define RESETS_WDSEL_BUSCTRL_LSB _u(1)
|
||||
#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_WDSEL_ADC
|
||||
#define RESETS_WDSEL_ADC_RESET _u(0x0)
|
||||
#define RESETS_WDSEL_ADC_BITS _u(0x00000001)
|
||||
#define RESETS_WDSEL_ADC_MSB _u(0)
|
||||
#define RESETS_WDSEL_ADC_LSB _u(0)
|
||||
#define RESETS_WDSEL_ADC_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : RESETS_RESET_DONE
|
||||
// Description : Reset done. If a bit is set then a reset done signal has been
|
||||
// returned by the peripheral. This indicates that the
|
||||
// peripheral's registers are ready to be accessed.
|
||||
#define RESETS_RESET_DONE_OFFSET _u(0x00000008)
|
||||
#define RESETS_RESET_DONE_BITS _u(0x01ffffff)
|
||||
#define RESETS_RESET_DONE_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_USBCTRL
|
||||
#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000)
|
||||
#define RESETS_RESET_DONE_USBCTRL_MSB _u(24)
|
||||
#define RESETS_RESET_DONE_USBCTRL_LSB _u(24)
|
||||
#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_UART1
|
||||
#define RESETS_RESET_DONE_UART1_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_UART1_BITS _u(0x00800000)
|
||||
#define RESETS_RESET_DONE_UART1_MSB _u(23)
|
||||
#define RESETS_RESET_DONE_UART1_LSB _u(23)
|
||||
#define RESETS_RESET_DONE_UART1_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_UART0
|
||||
#define RESETS_RESET_DONE_UART0_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_UART0_BITS _u(0x00400000)
|
||||
#define RESETS_RESET_DONE_UART0_MSB _u(22)
|
||||
#define RESETS_RESET_DONE_UART0_LSB _u(22)
|
||||
#define RESETS_RESET_DONE_UART0_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_TIMER
|
||||
#define RESETS_RESET_DONE_TIMER_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000)
|
||||
#define RESETS_RESET_DONE_TIMER_MSB _u(21)
|
||||
#define RESETS_RESET_DONE_TIMER_LSB _u(21)
|
||||
#define RESETS_RESET_DONE_TIMER_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_TBMAN
|
||||
#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000)
|
||||
#define RESETS_RESET_DONE_TBMAN_MSB _u(20)
|
||||
#define RESETS_RESET_DONE_TBMAN_LSB _u(20)
|
||||
#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_SYSINFO
|
||||
#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000)
|
||||
#define RESETS_RESET_DONE_SYSINFO_MSB _u(19)
|
||||
#define RESETS_RESET_DONE_SYSINFO_LSB _u(19)
|
||||
#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_SYSCFG
|
||||
#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000)
|
||||
#define RESETS_RESET_DONE_SYSCFG_MSB _u(18)
|
||||
#define RESETS_RESET_DONE_SYSCFG_LSB _u(18)
|
||||
#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_SPI1
|
||||
#define RESETS_RESET_DONE_SPI1_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000)
|
||||
#define RESETS_RESET_DONE_SPI1_MSB _u(17)
|
||||
#define RESETS_RESET_DONE_SPI1_LSB _u(17)
|
||||
#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_SPI0
|
||||
#define RESETS_RESET_DONE_SPI0_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000)
|
||||
#define RESETS_RESET_DONE_SPI0_MSB _u(16)
|
||||
#define RESETS_RESET_DONE_SPI0_LSB _u(16)
|
||||
#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_RTC
|
||||
#define RESETS_RESET_DONE_RTC_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_RTC_BITS _u(0x00008000)
|
||||
#define RESETS_RESET_DONE_RTC_MSB _u(15)
|
||||
#define RESETS_RESET_DONE_RTC_LSB _u(15)
|
||||
#define RESETS_RESET_DONE_RTC_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_PWM
|
||||
#define RESETS_RESET_DONE_PWM_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_PWM_BITS _u(0x00004000)
|
||||
#define RESETS_RESET_DONE_PWM_MSB _u(14)
|
||||
#define RESETS_RESET_DONE_PWM_LSB _u(14)
|
||||
#define RESETS_RESET_DONE_PWM_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_PLL_USB
|
||||
#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000)
|
||||
#define RESETS_RESET_DONE_PLL_USB_MSB _u(13)
|
||||
#define RESETS_RESET_DONE_PLL_USB_LSB _u(13)
|
||||
#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_PLL_SYS
|
||||
#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000)
|
||||
#define RESETS_RESET_DONE_PLL_SYS_MSB _u(12)
|
||||
#define RESETS_RESET_DONE_PLL_SYS_LSB _u(12)
|
||||
#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_PIO1
|
||||
#define RESETS_RESET_DONE_PIO1_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800)
|
||||
#define RESETS_RESET_DONE_PIO1_MSB _u(11)
|
||||
#define RESETS_RESET_DONE_PIO1_LSB _u(11)
|
||||
#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_PIO0
|
||||
#define RESETS_RESET_DONE_PIO0_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400)
|
||||
#define RESETS_RESET_DONE_PIO0_MSB _u(10)
|
||||
#define RESETS_RESET_DONE_PIO0_LSB _u(10)
|
||||
#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_PADS_QSPI
|
||||
#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200)
|
||||
#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9)
|
||||
#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(9)
|
||||
#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_PADS_BANK0
|
||||
#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100)
|
||||
#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8)
|
||||
#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(8)
|
||||
#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_JTAG
|
||||
#define RESETS_RESET_DONE_JTAG_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080)
|
||||
#define RESETS_RESET_DONE_JTAG_MSB _u(7)
|
||||
#define RESETS_RESET_DONE_JTAG_LSB _u(7)
|
||||
#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_IO_QSPI
|
||||
#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040)
|
||||
#define RESETS_RESET_DONE_IO_QSPI_MSB _u(6)
|
||||
#define RESETS_RESET_DONE_IO_QSPI_LSB _u(6)
|
||||
#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_IO_BANK0
|
||||
#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020)
|
||||
#define RESETS_RESET_DONE_IO_BANK0_MSB _u(5)
|
||||
#define RESETS_RESET_DONE_IO_BANK0_LSB _u(5)
|
||||
#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_I2C1
|
||||
#define RESETS_RESET_DONE_I2C1_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010)
|
||||
#define RESETS_RESET_DONE_I2C1_MSB _u(4)
|
||||
#define RESETS_RESET_DONE_I2C1_LSB _u(4)
|
||||
#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_I2C0
|
||||
#define RESETS_RESET_DONE_I2C0_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008)
|
||||
#define RESETS_RESET_DONE_I2C0_MSB _u(3)
|
||||
#define RESETS_RESET_DONE_I2C0_LSB _u(3)
|
||||
#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_DMA
|
||||
#define RESETS_RESET_DONE_DMA_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004)
|
||||
#define RESETS_RESET_DONE_DMA_MSB _u(2)
|
||||
#define RESETS_RESET_DONE_DMA_LSB _u(2)
|
||||
#define RESETS_RESET_DONE_DMA_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_BUSCTRL
|
||||
#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002)
|
||||
#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1)
|
||||
#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1)
|
||||
#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RESETS_RESET_DONE_ADC
|
||||
#define RESETS_RESET_DONE_ADC_RESET _u(0x0)
|
||||
#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001)
|
||||
#define RESETS_RESET_DONE_ADC_MSB _u(0)
|
||||
#define RESETS_RESET_DONE_ADC_LSB _u(0)
|
||||
#define RESETS_RESET_DONE_ADC_ACCESS "RO"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_RESETS_H
|
||||
|
||||
|
|
@ -0,0 +1,314 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : ROSC
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_ROSC_H
|
||||
#define _HARDWARE_REGS_ROSC_H
|
||||
// =============================================================================
|
||||
// Register : ROSC_CTRL
|
||||
// Description : Ring Oscillator control
|
||||
#define ROSC_CTRL_OFFSET _u(0x00000000)
|
||||
#define ROSC_CTRL_BITS _u(0x00ffffff)
|
||||
#define ROSC_CTRL_RESET _u(0x00000aa0)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_CTRL_ENABLE
|
||||
// Description : On power-up this field is initialised to ENABLE
|
||||
// The system clock must be switched to another source before
|
||||
// setting this field to DISABLE otherwise the chip will lock up
|
||||
// The 12-bit code is intended to give some protection against
|
||||
// accidental writes. An invalid setting will enable the
|
||||
// oscillator.
|
||||
// 0xd1e -> DISABLE
|
||||
// 0xfab -> ENABLE
|
||||
#define ROSC_CTRL_ENABLE_RESET "-"
|
||||
#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000)
|
||||
#define ROSC_CTRL_ENABLE_MSB _u(23)
|
||||
#define ROSC_CTRL_ENABLE_LSB _u(12)
|
||||
#define ROSC_CTRL_ENABLE_ACCESS "RW"
|
||||
#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
|
||||
#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_CTRL_FREQ_RANGE
|
||||
// Description : Controls the number of delay stages in the ROSC ring
|
||||
// LOW uses stages 0 to 7
|
||||
// MEDIUM uses stages 2 to 7
|
||||
// HIGH uses stages 4 to 7
|
||||
// TOOHIGH uses stages 6 to 7 and should not be used because its
|
||||
// frequency exceeds design specifications
|
||||
// The clock output will not glitch when changing the range up one
|
||||
// step at a time
|
||||
// The clock output will glitch when changing the range down
|
||||
// Note: the values here are gray coded which is why HIGH comes
|
||||
// before TOOHIGH
|
||||
// 0xfa4 -> LOW
|
||||
// 0xfa5 -> MEDIUM
|
||||
// 0xfa7 -> HIGH
|
||||
// 0xfa6 -> TOOHIGH
|
||||
#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0)
|
||||
#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
|
||||
#define ROSC_CTRL_FREQ_RANGE_MSB _u(11)
|
||||
#define ROSC_CTRL_FREQ_RANGE_LSB _u(0)
|
||||
#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW"
|
||||
#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4)
|
||||
#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5)
|
||||
#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7)
|
||||
#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6)
|
||||
// =============================================================================
|
||||
// Register : ROSC_FREQA
|
||||
// Description : The FREQA & FREQB registers control the frequency by
|
||||
// controlling the drive strength of each stage
|
||||
// The drive strength has 4 levels determined by the number of
|
||||
// bits set
|
||||
// Increasing the number of bits set increases the drive strength
|
||||
// and increases the oscillation frequency
|
||||
// 0 bits set is the default drive strength
|
||||
// 1 bit set doubles the drive strength
|
||||
// 2 bits set triples drive strength
|
||||
// 3 bits set quadruples drive strength
|
||||
#define ROSC_FREQA_OFFSET _u(0x00000004)
|
||||
#define ROSC_FREQA_BITS _u(0xffff7777)
|
||||
#define ROSC_FREQA_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQA_PASSWD
|
||||
// Description : Set to 0x9696 to apply the settings
|
||||
// Any other value in this field will set all drive strengths to 0
|
||||
// 0x9696 -> PASS
|
||||
#define ROSC_FREQA_PASSWD_RESET _u(0x0000)
|
||||
#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000)
|
||||
#define ROSC_FREQA_PASSWD_MSB _u(31)
|
||||
#define ROSC_FREQA_PASSWD_LSB _u(16)
|
||||
#define ROSC_FREQA_PASSWD_ACCESS "RW"
|
||||
#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQA_DS3
|
||||
// Description : Stage 3 drive strength
|
||||
#define ROSC_FREQA_DS3_RESET _u(0x0)
|
||||
#define ROSC_FREQA_DS3_BITS _u(0x00007000)
|
||||
#define ROSC_FREQA_DS3_MSB _u(14)
|
||||
#define ROSC_FREQA_DS3_LSB _u(12)
|
||||
#define ROSC_FREQA_DS3_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQA_DS2
|
||||
// Description : Stage 2 drive strength
|
||||
#define ROSC_FREQA_DS2_RESET _u(0x0)
|
||||
#define ROSC_FREQA_DS2_BITS _u(0x00000700)
|
||||
#define ROSC_FREQA_DS2_MSB _u(10)
|
||||
#define ROSC_FREQA_DS2_LSB _u(8)
|
||||
#define ROSC_FREQA_DS2_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQA_DS1
|
||||
// Description : Stage 1 drive strength
|
||||
#define ROSC_FREQA_DS1_RESET _u(0x0)
|
||||
#define ROSC_FREQA_DS1_BITS _u(0x00000070)
|
||||
#define ROSC_FREQA_DS1_MSB _u(6)
|
||||
#define ROSC_FREQA_DS1_LSB _u(4)
|
||||
#define ROSC_FREQA_DS1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQA_DS0
|
||||
// Description : Stage 0 drive strength
|
||||
#define ROSC_FREQA_DS0_RESET _u(0x0)
|
||||
#define ROSC_FREQA_DS0_BITS _u(0x00000007)
|
||||
#define ROSC_FREQA_DS0_MSB _u(2)
|
||||
#define ROSC_FREQA_DS0_LSB _u(0)
|
||||
#define ROSC_FREQA_DS0_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : ROSC_FREQB
|
||||
// Description : For a detailed description see freqa register
|
||||
#define ROSC_FREQB_OFFSET _u(0x00000008)
|
||||
#define ROSC_FREQB_BITS _u(0xffff7777)
|
||||
#define ROSC_FREQB_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQB_PASSWD
|
||||
// Description : Set to 0x9696 to apply the settings
|
||||
// Any other value in this field will set all drive strengths to 0
|
||||
// 0x9696 -> PASS
|
||||
#define ROSC_FREQB_PASSWD_RESET _u(0x0000)
|
||||
#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000)
|
||||
#define ROSC_FREQB_PASSWD_MSB _u(31)
|
||||
#define ROSC_FREQB_PASSWD_LSB _u(16)
|
||||
#define ROSC_FREQB_PASSWD_ACCESS "RW"
|
||||
#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQB_DS7
|
||||
// Description : Stage 7 drive strength
|
||||
#define ROSC_FREQB_DS7_RESET _u(0x0)
|
||||
#define ROSC_FREQB_DS7_BITS _u(0x00007000)
|
||||
#define ROSC_FREQB_DS7_MSB _u(14)
|
||||
#define ROSC_FREQB_DS7_LSB _u(12)
|
||||
#define ROSC_FREQB_DS7_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQB_DS6
|
||||
// Description : Stage 6 drive strength
|
||||
#define ROSC_FREQB_DS6_RESET _u(0x0)
|
||||
#define ROSC_FREQB_DS6_BITS _u(0x00000700)
|
||||
#define ROSC_FREQB_DS6_MSB _u(10)
|
||||
#define ROSC_FREQB_DS6_LSB _u(8)
|
||||
#define ROSC_FREQB_DS6_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQB_DS5
|
||||
// Description : Stage 5 drive strength
|
||||
#define ROSC_FREQB_DS5_RESET _u(0x0)
|
||||
#define ROSC_FREQB_DS5_BITS _u(0x00000070)
|
||||
#define ROSC_FREQB_DS5_MSB _u(6)
|
||||
#define ROSC_FREQB_DS5_LSB _u(4)
|
||||
#define ROSC_FREQB_DS5_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQB_DS4
|
||||
// Description : Stage 4 drive strength
|
||||
#define ROSC_FREQB_DS4_RESET _u(0x0)
|
||||
#define ROSC_FREQB_DS4_BITS _u(0x00000007)
|
||||
#define ROSC_FREQB_DS4_MSB _u(2)
|
||||
#define ROSC_FREQB_DS4_LSB _u(0)
|
||||
#define ROSC_FREQB_DS4_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : ROSC_DORMANT
|
||||
// Description : Ring Oscillator pause control
|
||||
// This is used to save power by pausing the ROSC
|
||||
// On power-up this field is initialised to WAKE
|
||||
// An invalid write will also select WAKE
|
||||
// Warning: setup the irq before selecting dormant mode
|
||||
// 0x636f6d61 -> dormant
|
||||
// 0x77616b65 -> WAKE
|
||||
#define ROSC_DORMANT_OFFSET _u(0x0000000c)
|
||||
#define ROSC_DORMANT_BITS _u(0xffffffff)
|
||||
#define ROSC_DORMANT_RESET "-"
|
||||
#define ROSC_DORMANT_MSB _u(31)
|
||||
#define ROSC_DORMANT_LSB _u(0)
|
||||
#define ROSC_DORMANT_ACCESS "RW"
|
||||
#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
|
||||
#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65)
|
||||
// =============================================================================
|
||||
// Register : ROSC_DIV
|
||||
// Description : Controls the output divider
|
||||
// set to 0xaa0 + div where
|
||||
// div = 0 divides by 32
|
||||
// div = 1-31 divides by div
|
||||
// any other value sets div=31
|
||||
// this register resets to div=16
|
||||
// 0xaa0 -> PASS
|
||||
#define ROSC_DIV_OFFSET _u(0x00000010)
|
||||
#define ROSC_DIV_BITS _u(0x00000fff)
|
||||
#define ROSC_DIV_RESET "-"
|
||||
#define ROSC_DIV_MSB _u(11)
|
||||
#define ROSC_DIV_LSB _u(0)
|
||||
#define ROSC_DIV_ACCESS "RW"
|
||||
#define ROSC_DIV_VALUE_PASS _u(0xaa0)
|
||||
// =============================================================================
|
||||
// Register : ROSC_PHASE
|
||||
// Description : Controls the phase shifted output
|
||||
#define ROSC_PHASE_OFFSET _u(0x00000014)
|
||||
#define ROSC_PHASE_BITS _u(0x00000fff)
|
||||
#define ROSC_PHASE_RESET _u(0x00000008)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_PHASE_PASSWD
|
||||
// Description : set to 0xaa
|
||||
// any other value enables the output with shift=0
|
||||
#define ROSC_PHASE_PASSWD_RESET _u(0x00)
|
||||
#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
|
||||
#define ROSC_PHASE_PASSWD_MSB _u(11)
|
||||
#define ROSC_PHASE_PASSWD_LSB _u(4)
|
||||
#define ROSC_PHASE_PASSWD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_PHASE_ENABLE
|
||||
// Description : enable the phase-shifted output
|
||||
// this can be changed on-the-fly
|
||||
#define ROSC_PHASE_ENABLE_RESET _u(0x1)
|
||||
#define ROSC_PHASE_ENABLE_BITS _u(0x00000008)
|
||||
#define ROSC_PHASE_ENABLE_MSB _u(3)
|
||||
#define ROSC_PHASE_ENABLE_LSB _u(3)
|
||||
#define ROSC_PHASE_ENABLE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_PHASE_FLIP
|
||||
// Description : invert the phase-shifted output
|
||||
// this is ignored when div=1
|
||||
#define ROSC_PHASE_FLIP_RESET _u(0x0)
|
||||
#define ROSC_PHASE_FLIP_BITS _u(0x00000004)
|
||||
#define ROSC_PHASE_FLIP_MSB _u(2)
|
||||
#define ROSC_PHASE_FLIP_LSB _u(2)
|
||||
#define ROSC_PHASE_FLIP_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_PHASE_SHIFT
|
||||
// Description : phase shift the phase-shifted output by SHIFT input clocks
|
||||
// this can be changed on-the-fly
|
||||
// must be set to 0 before setting div=1
|
||||
#define ROSC_PHASE_SHIFT_RESET _u(0x0)
|
||||
#define ROSC_PHASE_SHIFT_BITS _u(0x00000003)
|
||||
#define ROSC_PHASE_SHIFT_MSB _u(1)
|
||||
#define ROSC_PHASE_SHIFT_LSB _u(0)
|
||||
#define ROSC_PHASE_SHIFT_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : ROSC_STATUS
|
||||
// Description : Ring Oscillator Status
|
||||
#define ROSC_STATUS_OFFSET _u(0x00000018)
|
||||
#define ROSC_STATUS_BITS _u(0x81011000)
|
||||
#define ROSC_STATUS_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_STATUS_STABLE
|
||||
// Description : Oscillator is running and stable
|
||||
#define ROSC_STATUS_STABLE_RESET _u(0x0)
|
||||
#define ROSC_STATUS_STABLE_BITS _u(0x80000000)
|
||||
#define ROSC_STATUS_STABLE_MSB _u(31)
|
||||
#define ROSC_STATUS_STABLE_LSB _u(31)
|
||||
#define ROSC_STATUS_STABLE_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_STATUS_BADWRITE
|
||||
// Description : An invalid value has been written to CTRL_ENABLE or
|
||||
// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
|
||||
#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
|
||||
#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
|
||||
#define ROSC_STATUS_BADWRITE_MSB _u(24)
|
||||
#define ROSC_STATUS_BADWRITE_LSB _u(24)
|
||||
#define ROSC_STATUS_BADWRITE_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_STATUS_DIV_RUNNING
|
||||
// Description : post-divider is running
|
||||
// this resets to 0 but transitions to 1 during chip startup
|
||||
#define ROSC_STATUS_DIV_RUNNING_RESET "-"
|
||||
#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000)
|
||||
#define ROSC_STATUS_DIV_RUNNING_MSB _u(16)
|
||||
#define ROSC_STATUS_DIV_RUNNING_LSB _u(16)
|
||||
#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_STATUS_ENABLED
|
||||
// Description : Oscillator is enabled but not necessarily running and stable
|
||||
// this resets to 0 but transitions to 1 during chip startup
|
||||
#define ROSC_STATUS_ENABLED_RESET "-"
|
||||
#define ROSC_STATUS_ENABLED_BITS _u(0x00001000)
|
||||
#define ROSC_STATUS_ENABLED_MSB _u(12)
|
||||
#define ROSC_STATUS_ENABLED_LSB _u(12)
|
||||
#define ROSC_STATUS_ENABLED_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : ROSC_RANDOMBIT
|
||||
// Description : This just reads the state of the oscillator output so
|
||||
// randomness is compromised if the ring oscillator is stopped or
|
||||
// run at a harmonic of the bus frequency
|
||||
#define ROSC_RANDOMBIT_OFFSET _u(0x0000001c)
|
||||
#define ROSC_RANDOMBIT_BITS _u(0x00000001)
|
||||
#define ROSC_RANDOMBIT_RESET _u(0x00000001)
|
||||
#define ROSC_RANDOMBIT_MSB _u(0)
|
||||
#define ROSC_RANDOMBIT_LSB _u(0)
|
||||
#define ROSC_RANDOMBIT_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : ROSC_COUNT
|
||||
// Description : A down counter running at the ROSC frequency which counts to
|
||||
// zero and stops.
|
||||
// To start the counter write a non-zero value.
|
||||
// Can be used for short software pauses when setting up time
|
||||
// sensitive hardware.
|
||||
#define ROSC_COUNT_OFFSET _u(0x00000020)
|
||||
#define ROSC_COUNT_BITS _u(0x000000ff)
|
||||
#define ROSC_COUNT_RESET _u(0x00000000)
|
||||
#define ROSC_COUNT_MSB _u(7)
|
||||
#define ROSC_COUNT_LSB _u(0)
|
||||
#define ROSC_COUNT_ACCESS "RW"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_ROSC_H
|
||||
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : RTC
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// Description : Register block to control RTC
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_RTC_H
|
||||
#define _HARDWARE_REGS_RTC_H
|
||||
// =============================================================================
|
||||
// Register : RTC_CLKDIV_M1
|
||||
// Description : Divider minus 1 for the 1 second counter. Safe to change the
|
||||
// value when RTC is not enabled.
|
||||
#define RTC_CLKDIV_M1_OFFSET _u(0x00000000)
|
||||
#define RTC_CLKDIV_M1_BITS _u(0x0000ffff)
|
||||
#define RTC_CLKDIV_M1_RESET _u(0x00000000)
|
||||
#define RTC_CLKDIV_M1_MSB _u(15)
|
||||
#define RTC_CLKDIV_M1_LSB _u(0)
|
||||
#define RTC_CLKDIV_M1_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : RTC_SETUP_0
|
||||
// Description : RTC setup register 0
|
||||
#define RTC_SETUP_0_OFFSET _u(0x00000004)
|
||||
#define RTC_SETUP_0_BITS _u(0x00ffff1f)
|
||||
#define RTC_SETUP_0_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_SETUP_0_YEAR
|
||||
// Description : Year
|
||||
#define RTC_SETUP_0_YEAR_RESET _u(0x000)
|
||||
#define RTC_SETUP_0_YEAR_BITS _u(0x00fff000)
|
||||
#define RTC_SETUP_0_YEAR_MSB _u(23)
|
||||
#define RTC_SETUP_0_YEAR_LSB _u(12)
|
||||
#define RTC_SETUP_0_YEAR_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_SETUP_0_MONTH
|
||||
// Description : Month (1..12)
|
||||
#define RTC_SETUP_0_MONTH_RESET _u(0x0)
|
||||
#define RTC_SETUP_0_MONTH_BITS _u(0x00000f00)
|
||||
#define RTC_SETUP_0_MONTH_MSB _u(11)
|
||||
#define RTC_SETUP_0_MONTH_LSB _u(8)
|
||||
#define RTC_SETUP_0_MONTH_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_SETUP_0_DAY
|
||||
// Description : Day of the month (1..31)
|
||||
#define RTC_SETUP_0_DAY_RESET _u(0x00)
|
||||
#define RTC_SETUP_0_DAY_BITS _u(0x0000001f)
|
||||
#define RTC_SETUP_0_DAY_MSB _u(4)
|
||||
#define RTC_SETUP_0_DAY_LSB _u(0)
|
||||
#define RTC_SETUP_0_DAY_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : RTC_SETUP_1
|
||||
// Description : RTC setup register 1
|
||||
#define RTC_SETUP_1_OFFSET _u(0x00000008)
|
||||
#define RTC_SETUP_1_BITS _u(0x071f3f3f)
|
||||
#define RTC_SETUP_1_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_SETUP_1_DOTW
|
||||
// Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
|
||||
#define RTC_SETUP_1_DOTW_RESET _u(0x0)
|
||||
#define RTC_SETUP_1_DOTW_BITS _u(0x07000000)
|
||||
#define RTC_SETUP_1_DOTW_MSB _u(26)
|
||||
#define RTC_SETUP_1_DOTW_LSB _u(24)
|
||||
#define RTC_SETUP_1_DOTW_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_SETUP_1_HOUR
|
||||
// Description : Hours
|
||||
#define RTC_SETUP_1_HOUR_RESET _u(0x00)
|
||||
#define RTC_SETUP_1_HOUR_BITS _u(0x001f0000)
|
||||
#define RTC_SETUP_1_HOUR_MSB _u(20)
|
||||
#define RTC_SETUP_1_HOUR_LSB _u(16)
|
||||
#define RTC_SETUP_1_HOUR_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_SETUP_1_MIN
|
||||
// Description : Minutes
|
||||
#define RTC_SETUP_1_MIN_RESET _u(0x00)
|
||||
#define RTC_SETUP_1_MIN_BITS _u(0x00003f00)
|
||||
#define RTC_SETUP_1_MIN_MSB _u(13)
|
||||
#define RTC_SETUP_1_MIN_LSB _u(8)
|
||||
#define RTC_SETUP_1_MIN_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_SETUP_1_SEC
|
||||
// Description : Seconds
|
||||
#define RTC_SETUP_1_SEC_RESET _u(0x00)
|
||||
#define RTC_SETUP_1_SEC_BITS _u(0x0000003f)
|
||||
#define RTC_SETUP_1_SEC_MSB _u(5)
|
||||
#define RTC_SETUP_1_SEC_LSB _u(0)
|
||||
#define RTC_SETUP_1_SEC_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : RTC_CTRL
|
||||
// Description : RTC Control and status
|
||||
#define RTC_CTRL_OFFSET _u(0x0000000c)
|
||||
#define RTC_CTRL_BITS _u(0x00000113)
|
||||
#define RTC_CTRL_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_CTRL_FORCE_NOTLEAPYEAR
|
||||
// Description : If set, leapyear is forced off.
|
||||
// Useful for years divisible by 100 but not by 400
|
||||
#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET _u(0x0)
|
||||
#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS _u(0x00000100)
|
||||
#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB _u(8)
|
||||
#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB _u(8)
|
||||
#define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_CTRL_LOAD
|
||||
// Description : Load RTC
|
||||
#define RTC_CTRL_LOAD_RESET _u(0x0)
|
||||
#define RTC_CTRL_LOAD_BITS _u(0x00000010)
|
||||
#define RTC_CTRL_LOAD_MSB _u(4)
|
||||
#define RTC_CTRL_LOAD_LSB _u(4)
|
||||
#define RTC_CTRL_LOAD_ACCESS "SC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_CTRL_RTC_ACTIVE
|
||||
// Description : RTC enabled (running)
|
||||
#define RTC_CTRL_RTC_ACTIVE_RESET "-"
|
||||
#define RTC_CTRL_RTC_ACTIVE_BITS _u(0x00000002)
|
||||
#define RTC_CTRL_RTC_ACTIVE_MSB _u(1)
|
||||
#define RTC_CTRL_RTC_ACTIVE_LSB _u(1)
|
||||
#define RTC_CTRL_RTC_ACTIVE_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_CTRL_RTC_ENABLE
|
||||
// Description : Enable RTC
|
||||
#define RTC_CTRL_RTC_ENABLE_RESET _u(0x0)
|
||||
#define RTC_CTRL_RTC_ENABLE_BITS _u(0x00000001)
|
||||
#define RTC_CTRL_RTC_ENABLE_MSB _u(0)
|
||||
#define RTC_CTRL_RTC_ENABLE_LSB _u(0)
|
||||
#define RTC_CTRL_RTC_ENABLE_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : RTC_IRQ_SETUP_0
|
||||
// Description : Interrupt setup register 0
|
||||
#define RTC_IRQ_SETUP_0_OFFSET _u(0x00000010)
|
||||
#define RTC_IRQ_SETUP_0_BITS _u(0x37ffff1f)
|
||||
#define RTC_IRQ_SETUP_0_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE
|
||||
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-"
|
||||
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000)
|
||||
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29)
|
||||
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB _u(29)
|
||||
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_0_MATCH_ENA
|
||||
// Description : Global match enable. Don't change any other value while this
|
||||
// one is enabled
|
||||
#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET _u(0x0)
|
||||
#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS _u(0x10000000)
|
||||
#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB _u(28)
|
||||
#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB _u(28)
|
||||
#define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_0_YEAR_ENA
|
||||
// Description : Enable year matching
|
||||
#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET _u(0x0)
|
||||
#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS _u(0x04000000)
|
||||
#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB _u(26)
|
||||
#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB _u(26)
|
||||
#define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_0_MONTH_ENA
|
||||
// Description : Enable month matching
|
||||
#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET _u(0x0)
|
||||
#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS _u(0x02000000)
|
||||
#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB _u(25)
|
||||
#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB _u(25)
|
||||
#define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_0_DAY_ENA
|
||||
// Description : Enable day matching
|
||||
#define RTC_IRQ_SETUP_0_DAY_ENA_RESET _u(0x0)
|
||||
#define RTC_IRQ_SETUP_0_DAY_ENA_BITS _u(0x01000000)
|
||||
#define RTC_IRQ_SETUP_0_DAY_ENA_MSB _u(24)
|
||||
#define RTC_IRQ_SETUP_0_DAY_ENA_LSB _u(24)
|
||||
#define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_0_YEAR
|
||||
// Description : Year
|
||||
#define RTC_IRQ_SETUP_0_YEAR_RESET _u(0x000)
|
||||
#define RTC_IRQ_SETUP_0_YEAR_BITS _u(0x00fff000)
|
||||
#define RTC_IRQ_SETUP_0_YEAR_MSB _u(23)
|
||||
#define RTC_IRQ_SETUP_0_YEAR_LSB _u(12)
|
||||
#define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_0_MONTH
|
||||
// Description : Month (1..12)
|
||||
#define RTC_IRQ_SETUP_0_MONTH_RESET _u(0x0)
|
||||
#define RTC_IRQ_SETUP_0_MONTH_BITS _u(0x00000f00)
|
||||
#define RTC_IRQ_SETUP_0_MONTH_MSB _u(11)
|
||||
#define RTC_IRQ_SETUP_0_MONTH_LSB _u(8)
|
||||
#define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_0_DAY
|
||||
// Description : Day of the month (1..31)
|
||||
#define RTC_IRQ_SETUP_0_DAY_RESET _u(0x00)
|
||||
#define RTC_IRQ_SETUP_0_DAY_BITS _u(0x0000001f)
|
||||
#define RTC_IRQ_SETUP_0_DAY_MSB _u(4)
|
||||
#define RTC_IRQ_SETUP_0_DAY_LSB _u(0)
|
||||
#define RTC_IRQ_SETUP_0_DAY_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : RTC_IRQ_SETUP_1
|
||||
// Description : Interrupt setup register 1
|
||||
#define RTC_IRQ_SETUP_1_OFFSET _u(0x00000014)
|
||||
#define RTC_IRQ_SETUP_1_BITS _u(0xf71f3f3f)
|
||||
#define RTC_IRQ_SETUP_1_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_1_DOTW_ENA
|
||||
// Description : Enable day of the week matching
|
||||
#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET _u(0x0)
|
||||
#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS _u(0x80000000)
|
||||
#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB _u(31)
|
||||
#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB _u(31)
|
||||
#define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_1_HOUR_ENA
|
||||
// Description : Enable hour matching
|
||||
#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET _u(0x0)
|
||||
#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS _u(0x40000000)
|
||||
#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB _u(30)
|
||||
#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB _u(30)
|
||||
#define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_1_MIN_ENA
|
||||
// Description : Enable minute matching
|
||||
#define RTC_IRQ_SETUP_1_MIN_ENA_RESET _u(0x0)
|
||||
#define RTC_IRQ_SETUP_1_MIN_ENA_BITS _u(0x20000000)
|
||||
#define RTC_IRQ_SETUP_1_MIN_ENA_MSB _u(29)
|
||||
#define RTC_IRQ_SETUP_1_MIN_ENA_LSB _u(29)
|
||||
#define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_1_SEC_ENA
|
||||
// Description : Enable second matching
|
||||
#define RTC_IRQ_SETUP_1_SEC_ENA_RESET _u(0x0)
|
||||
#define RTC_IRQ_SETUP_1_SEC_ENA_BITS _u(0x10000000)
|
||||
#define RTC_IRQ_SETUP_1_SEC_ENA_MSB _u(28)
|
||||
#define RTC_IRQ_SETUP_1_SEC_ENA_LSB _u(28)
|
||||
#define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_1_DOTW
|
||||
// Description : Day of the week
|
||||
#define RTC_IRQ_SETUP_1_DOTW_RESET _u(0x0)
|
||||
#define RTC_IRQ_SETUP_1_DOTW_BITS _u(0x07000000)
|
||||
#define RTC_IRQ_SETUP_1_DOTW_MSB _u(26)
|
||||
#define RTC_IRQ_SETUP_1_DOTW_LSB _u(24)
|
||||
#define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_1_HOUR
|
||||
// Description : Hours
|
||||
#define RTC_IRQ_SETUP_1_HOUR_RESET _u(0x00)
|
||||
#define RTC_IRQ_SETUP_1_HOUR_BITS _u(0x001f0000)
|
||||
#define RTC_IRQ_SETUP_1_HOUR_MSB _u(20)
|
||||
#define RTC_IRQ_SETUP_1_HOUR_LSB _u(16)
|
||||
#define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_1_MIN
|
||||
// Description : Minutes
|
||||
#define RTC_IRQ_SETUP_1_MIN_RESET _u(0x00)
|
||||
#define RTC_IRQ_SETUP_1_MIN_BITS _u(0x00003f00)
|
||||
#define RTC_IRQ_SETUP_1_MIN_MSB _u(13)
|
||||
#define RTC_IRQ_SETUP_1_MIN_LSB _u(8)
|
||||
#define RTC_IRQ_SETUP_1_MIN_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_IRQ_SETUP_1_SEC
|
||||
// Description : Seconds
|
||||
#define RTC_IRQ_SETUP_1_SEC_RESET _u(0x00)
|
||||
#define RTC_IRQ_SETUP_1_SEC_BITS _u(0x0000003f)
|
||||
#define RTC_IRQ_SETUP_1_SEC_MSB _u(5)
|
||||
#define RTC_IRQ_SETUP_1_SEC_LSB _u(0)
|
||||
#define RTC_IRQ_SETUP_1_SEC_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : RTC_RTC_1
|
||||
// Description : RTC register 1.
|
||||
#define RTC_RTC_1_OFFSET _u(0x00000018)
|
||||
#define RTC_RTC_1_BITS _u(0x00ffff1f)
|
||||
#define RTC_RTC_1_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_RTC_1_YEAR
|
||||
// Description : Year
|
||||
#define RTC_RTC_1_YEAR_RESET "-"
|
||||
#define RTC_RTC_1_YEAR_BITS _u(0x00fff000)
|
||||
#define RTC_RTC_1_YEAR_MSB _u(23)
|
||||
#define RTC_RTC_1_YEAR_LSB _u(12)
|
||||
#define RTC_RTC_1_YEAR_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_RTC_1_MONTH
|
||||
// Description : Month (1..12)
|
||||
#define RTC_RTC_1_MONTH_RESET "-"
|
||||
#define RTC_RTC_1_MONTH_BITS _u(0x00000f00)
|
||||
#define RTC_RTC_1_MONTH_MSB _u(11)
|
||||
#define RTC_RTC_1_MONTH_LSB _u(8)
|
||||
#define RTC_RTC_1_MONTH_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_RTC_1_DAY
|
||||
// Description : Day of the month (1..31)
|
||||
#define RTC_RTC_1_DAY_RESET "-"
|
||||
#define RTC_RTC_1_DAY_BITS _u(0x0000001f)
|
||||
#define RTC_RTC_1_DAY_MSB _u(4)
|
||||
#define RTC_RTC_1_DAY_LSB _u(0)
|
||||
#define RTC_RTC_1_DAY_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : RTC_RTC_0
|
||||
// Description : RTC register 0
|
||||
// Read this before RTC 1!
|
||||
#define RTC_RTC_0_OFFSET _u(0x0000001c)
|
||||
#define RTC_RTC_0_BITS _u(0x071f3f3f)
|
||||
#define RTC_RTC_0_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_RTC_0_DOTW
|
||||
// Description : Day of the week
|
||||
#define RTC_RTC_0_DOTW_RESET "-"
|
||||
#define RTC_RTC_0_DOTW_BITS _u(0x07000000)
|
||||
#define RTC_RTC_0_DOTW_MSB _u(26)
|
||||
#define RTC_RTC_0_DOTW_LSB _u(24)
|
||||
#define RTC_RTC_0_DOTW_ACCESS "RF"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_RTC_0_HOUR
|
||||
// Description : Hours
|
||||
#define RTC_RTC_0_HOUR_RESET "-"
|
||||
#define RTC_RTC_0_HOUR_BITS _u(0x001f0000)
|
||||
#define RTC_RTC_0_HOUR_MSB _u(20)
|
||||
#define RTC_RTC_0_HOUR_LSB _u(16)
|
||||
#define RTC_RTC_0_HOUR_ACCESS "RF"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_RTC_0_MIN
|
||||
// Description : Minutes
|
||||
#define RTC_RTC_0_MIN_RESET "-"
|
||||
#define RTC_RTC_0_MIN_BITS _u(0x00003f00)
|
||||
#define RTC_RTC_0_MIN_MSB _u(13)
|
||||
#define RTC_RTC_0_MIN_LSB _u(8)
|
||||
#define RTC_RTC_0_MIN_ACCESS "RF"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_RTC_0_SEC
|
||||
// Description : Seconds
|
||||
#define RTC_RTC_0_SEC_RESET "-"
|
||||
#define RTC_RTC_0_SEC_BITS _u(0x0000003f)
|
||||
#define RTC_RTC_0_SEC_MSB _u(5)
|
||||
#define RTC_RTC_0_SEC_LSB _u(0)
|
||||
#define RTC_RTC_0_SEC_ACCESS "RF"
|
||||
// =============================================================================
|
||||
// Register : RTC_INTR
|
||||
// Description : Raw Interrupts
|
||||
#define RTC_INTR_OFFSET _u(0x00000020)
|
||||
#define RTC_INTR_BITS _u(0x00000001)
|
||||
#define RTC_INTR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_INTR_RTC
|
||||
#define RTC_INTR_RTC_RESET _u(0x0)
|
||||
#define RTC_INTR_RTC_BITS _u(0x00000001)
|
||||
#define RTC_INTR_RTC_MSB _u(0)
|
||||
#define RTC_INTR_RTC_LSB _u(0)
|
||||
#define RTC_INTR_RTC_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : RTC_INTE
|
||||
// Description : Interrupt Enable
|
||||
#define RTC_INTE_OFFSET _u(0x00000024)
|
||||
#define RTC_INTE_BITS _u(0x00000001)
|
||||
#define RTC_INTE_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_INTE_RTC
|
||||
#define RTC_INTE_RTC_RESET _u(0x0)
|
||||
#define RTC_INTE_RTC_BITS _u(0x00000001)
|
||||
#define RTC_INTE_RTC_MSB _u(0)
|
||||
#define RTC_INTE_RTC_LSB _u(0)
|
||||
#define RTC_INTE_RTC_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : RTC_INTF
|
||||
// Description : Interrupt Force
|
||||
#define RTC_INTF_OFFSET _u(0x00000028)
|
||||
#define RTC_INTF_BITS _u(0x00000001)
|
||||
#define RTC_INTF_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_INTF_RTC
|
||||
#define RTC_INTF_RTC_RESET _u(0x0)
|
||||
#define RTC_INTF_RTC_BITS _u(0x00000001)
|
||||
#define RTC_INTF_RTC_MSB _u(0)
|
||||
#define RTC_INTF_RTC_LSB _u(0)
|
||||
#define RTC_INTF_RTC_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : RTC_INTS
|
||||
// Description : Interrupt status after masking & forcing
|
||||
#define RTC_INTS_OFFSET _u(0x0000002c)
|
||||
#define RTC_INTS_BITS _u(0x00000001)
|
||||
#define RTC_INTS_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RTC_INTS_RTC
|
||||
#define RTC_INTS_RTC_RESET _u(0x0)
|
||||
#define RTC_INTS_RTC_BITS _u(0x00000001)
|
||||
#define RTC_INTS_RTC_MSB _u(0)
|
||||
#define RTC_INTS_RTC_LSB _u(0)
|
||||
#define RTC_INTS_RTC_ACCESS "RO"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_RTC_H
|
||||
|
||||
1659
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h
Normal file
1659
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,523 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : SPI
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_SPI_H
|
||||
#define _HARDWARE_REGS_SPI_H
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPCR0
|
||||
// Description : Control register 0, SSPCR0 on page 3-4
|
||||
#define SPI_SSPCR0_OFFSET _u(0x00000000)
|
||||
#define SPI_SSPCR0_BITS _u(0x0000ffff)
|
||||
#define SPI_SSPCR0_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPCR0_SCR
|
||||
// Description : Serial clock rate. The value SCR is used to generate the
|
||||
// transmit and receive bit rate of the PrimeCell SSP. The bit
|
||||
// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even
|
||||
// value from 2-254, programmed through the SSPCPSR register and
|
||||
// SCR is a value from 0-255.
|
||||
#define SPI_SSPCR0_SCR_RESET _u(0x00)
|
||||
#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00)
|
||||
#define SPI_SSPCR0_SCR_MSB _u(15)
|
||||
#define SPI_SSPCR0_SCR_LSB _u(8)
|
||||
#define SPI_SSPCR0_SCR_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPCR0_SPH
|
||||
// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only.
|
||||
// See Motorola SPI frame format on page 2-10.
|
||||
#define SPI_SSPCR0_SPH_RESET _u(0x0)
|
||||
#define SPI_SSPCR0_SPH_BITS _u(0x00000080)
|
||||
#define SPI_SSPCR0_SPH_MSB _u(7)
|
||||
#define SPI_SSPCR0_SPH_LSB _u(7)
|
||||
#define SPI_SSPCR0_SPH_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPCR0_SPO
|
||||
// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format
|
||||
// only. See Motorola SPI frame format on page 2-10.
|
||||
#define SPI_SSPCR0_SPO_RESET _u(0x0)
|
||||
#define SPI_SSPCR0_SPO_BITS _u(0x00000040)
|
||||
#define SPI_SSPCR0_SPO_MSB _u(6)
|
||||
#define SPI_SSPCR0_SPO_LSB _u(6)
|
||||
#define SPI_SSPCR0_SPO_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPCR0_FRF
|
||||
// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous
|
||||
// serial frame format. 10 National Microwire frame format. 11
|
||||
// Reserved, undefined operation.
|
||||
#define SPI_SSPCR0_FRF_RESET _u(0x0)
|
||||
#define SPI_SSPCR0_FRF_BITS _u(0x00000030)
|
||||
#define SPI_SSPCR0_FRF_MSB _u(5)
|
||||
#define SPI_SSPCR0_FRF_LSB _u(4)
|
||||
#define SPI_SSPCR0_FRF_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPCR0_DSS
|
||||
// Description : Data Size Select: 0000 Reserved, undefined operation. 0001
|
||||
// Reserved, undefined operation. 0010 Reserved, undefined
|
||||
// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data.
|
||||
// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
|
||||
// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data.
|
||||
// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
|
||||
#define SPI_SSPCR0_DSS_RESET _u(0x0)
|
||||
#define SPI_SSPCR0_DSS_BITS _u(0x0000000f)
|
||||
#define SPI_SSPCR0_DSS_MSB _u(3)
|
||||
#define SPI_SSPCR0_DSS_LSB _u(0)
|
||||
#define SPI_SSPCR0_DSS_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPCR1
|
||||
// Description : Control register 1, SSPCR1 on page 3-5
|
||||
#define SPI_SSPCR1_OFFSET _u(0x00000004)
|
||||
#define SPI_SSPCR1_BITS _u(0x0000000f)
|
||||
#define SPI_SSPCR1_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPCR1_SOD
|
||||
// Description : Slave-mode output disable. This bit is relevant only in the
|
||||
// slave mode, MS=1. In multiple-slave systems, it is possible for
|
||||
// an PrimeCell SSP master to broadcast a message to all slaves in
|
||||
// the system while ensuring that only one slave drives data onto
|
||||
// its serial output line. In such systems the RXD lines from
|
||||
// multiple slaves could be tied together. To operate in such
|
||||
// systems, the SOD bit can be set if the PrimeCell SSP slave is
|
||||
// not supposed to drive the SSPTXD line: 0 SSP can drive the
|
||||
// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
|
||||
// output in slave mode.
|
||||
#define SPI_SSPCR1_SOD_RESET _u(0x0)
|
||||
#define SPI_SSPCR1_SOD_BITS _u(0x00000008)
|
||||
#define SPI_SSPCR1_SOD_MSB _u(3)
|
||||
#define SPI_SSPCR1_SOD_LSB _u(3)
|
||||
#define SPI_SSPCR1_SOD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPCR1_MS
|
||||
// Description : Master or slave mode select. This bit can be modified only when
|
||||
// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as
|
||||
// master, default. 1 Device configured as slave.
|
||||
#define SPI_SSPCR1_MS_RESET _u(0x0)
|
||||
#define SPI_SSPCR1_MS_BITS _u(0x00000004)
|
||||
#define SPI_SSPCR1_MS_MSB _u(2)
|
||||
#define SPI_SSPCR1_MS_LSB _u(2)
|
||||
#define SPI_SSPCR1_MS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPCR1_SSE
|
||||
// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP
|
||||
// operation enabled.
|
||||
#define SPI_SSPCR1_SSE_RESET _u(0x0)
|
||||
#define SPI_SSPCR1_SSE_BITS _u(0x00000002)
|
||||
#define SPI_SSPCR1_SSE_MSB _u(1)
|
||||
#define SPI_SSPCR1_SSE_LSB _u(1)
|
||||
#define SPI_SSPCR1_SSE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPCR1_LBM
|
||||
// Description : Loop back mode: 0 Normal serial port operation enabled. 1
|
||||
// Output of transmit serial shifter is connected to input of
|
||||
// receive serial shifter internally.
|
||||
#define SPI_SSPCR1_LBM_RESET _u(0x0)
|
||||
#define SPI_SSPCR1_LBM_BITS _u(0x00000001)
|
||||
#define SPI_SSPCR1_LBM_MSB _u(0)
|
||||
#define SPI_SSPCR1_LBM_LSB _u(0)
|
||||
#define SPI_SSPCR1_LBM_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPDR
|
||||
// Description : Data register, SSPDR on page 3-6
|
||||
#define SPI_SSPDR_OFFSET _u(0x00000008)
|
||||
#define SPI_SSPDR_BITS _u(0x0000ffff)
|
||||
#define SPI_SSPDR_RESET "-"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPDR_DATA
|
||||
// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO.
|
||||
// You must right-justify data when the PrimeCell SSP is
|
||||
// programmed for a data size that is less than 16 bits. Unused
|
||||
// bits at the top are ignored by transmit logic. The receive
|
||||
// logic automatically right-justifies.
|
||||
#define SPI_SSPDR_DATA_RESET "-"
|
||||
#define SPI_SSPDR_DATA_BITS _u(0x0000ffff)
|
||||
#define SPI_SSPDR_DATA_MSB _u(15)
|
||||
#define SPI_SSPDR_DATA_LSB _u(0)
|
||||
#define SPI_SSPDR_DATA_ACCESS "RWF"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPSR
|
||||
// Description : Status register, SSPSR on page 3-7
|
||||
#define SPI_SSPSR_OFFSET _u(0x0000000c)
|
||||
#define SPI_SSPSR_BITS _u(0x0000001f)
|
||||
#define SPI_SSPSR_RESET _u(0x00000003)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPSR_BSY
|
||||
// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently
|
||||
// transmitting and/or receiving a frame or the transmit FIFO is
|
||||
// not empty.
|
||||
#define SPI_SSPSR_BSY_RESET _u(0x0)
|
||||
#define SPI_SSPSR_BSY_BITS _u(0x00000010)
|
||||
#define SPI_SSPSR_BSY_MSB _u(4)
|
||||
#define SPI_SSPSR_BSY_LSB _u(4)
|
||||
#define SPI_SSPSR_BSY_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPSR_RFF
|
||||
// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
|
||||
// FIFO is full.
|
||||
#define SPI_SSPSR_RFF_RESET _u(0x0)
|
||||
#define SPI_SSPSR_RFF_BITS _u(0x00000008)
|
||||
#define SPI_SSPSR_RFF_MSB _u(3)
|
||||
#define SPI_SSPSR_RFF_LSB _u(3)
|
||||
#define SPI_SSPSR_RFF_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPSR_RNE
|
||||
// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive
|
||||
// FIFO is not empty.
|
||||
#define SPI_SSPSR_RNE_RESET _u(0x0)
|
||||
#define SPI_SSPSR_RNE_BITS _u(0x00000004)
|
||||
#define SPI_SSPSR_RNE_MSB _u(2)
|
||||
#define SPI_SSPSR_RNE_LSB _u(2)
|
||||
#define SPI_SSPSR_RNE_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPSR_TNF
|
||||
// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit
|
||||
// FIFO is not full.
|
||||
#define SPI_SSPSR_TNF_RESET _u(0x1)
|
||||
#define SPI_SSPSR_TNF_BITS _u(0x00000002)
|
||||
#define SPI_SSPSR_TNF_MSB _u(1)
|
||||
#define SPI_SSPSR_TNF_LSB _u(1)
|
||||
#define SPI_SSPSR_TNF_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPSR_TFE
|
||||
// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
|
||||
// Transmit FIFO is empty.
|
||||
#define SPI_SSPSR_TFE_RESET _u(0x1)
|
||||
#define SPI_SSPSR_TFE_BITS _u(0x00000001)
|
||||
#define SPI_SSPSR_TFE_MSB _u(0)
|
||||
#define SPI_SSPSR_TFE_LSB _u(0)
|
||||
#define SPI_SSPSR_TFE_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPCPSR
|
||||
// Description : Clock prescale register, SSPCPSR on page 3-8
|
||||
#define SPI_SSPCPSR_OFFSET _u(0x00000010)
|
||||
#define SPI_SSPCPSR_BITS _u(0x000000ff)
|
||||
#define SPI_SSPCPSR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPCPSR_CPSDVSR
|
||||
// Description : Clock prescale divisor. Must be an even number from 2-254,
|
||||
// depending on the frequency of SSPCLK. The least significant bit
|
||||
// always returns zero on reads.
|
||||
#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00)
|
||||
#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff)
|
||||
#define SPI_SSPCPSR_CPSDVSR_MSB _u(7)
|
||||
#define SPI_SSPCPSR_CPSDVSR_LSB _u(0)
|
||||
#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPIMSC
|
||||
// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9
|
||||
#define SPI_SSPIMSC_OFFSET _u(0x00000014)
|
||||
#define SPI_SSPIMSC_BITS _u(0x0000000f)
|
||||
#define SPI_SSPIMSC_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPIMSC_TXIM
|
||||
// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or
|
||||
// less condition interrupt is masked. 1 Transmit FIFO half empty
|
||||
// or less condition interrupt is not masked.
|
||||
#define SPI_SSPIMSC_TXIM_RESET _u(0x0)
|
||||
#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008)
|
||||
#define SPI_SSPIMSC_TXIM_MSB _u(3)
|
||||
#define SPI_SSPIMSC_TXIM_LSB _u(3)
|
||||
#define SPI_SSPIMSC_TXIM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPIMSC_RXIM
|
||||
// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less
|
||||
// condition interrupt is masked. 1 Receive FIFO half full or less
|
||||
// condition interrupt is not masked.
|
||||
#define SPI_SSPIMSC_RXIM_RESET _u(0x0)
|
||||
#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004)
|
||||
#define SPI_SSPIMSC_RXIM_MSB _u(2)
|
||||
#define SPI_SSPIMSC_RXIM_LSB _u(2)
|
||||
#define SPI_SSPIMSC_RXIM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPIMSC_RTIM
|
||||
// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no
|
||||
// read prior to timeout period interrupt is masked. 1 Receive
|
||||
// FIFO not empty and no read prior to timeout period interrupt is
|
||||
// not masked.
|
||||
#define SPI_SSPIMSC_RTIM_RESET _u(0x0)
|
||||
#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002)
|
||||
#define SPI_SSPIMSC_RTIM_MSB _u(1)
|
||||
#define SPI_SSPIMSC_RTIM_LSB _u(1)
|
||||
#define SPI_SSPIMSC_RTIM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPIMSC_RORIM
|
||||
// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while
|
||||
// full condition interrupt is masked. 1 Receive FIFO written to
|
||||
// while full condition interrupt is not masked.
|
||||
#define SPI_SSPIMSC_RORIM_RESET _u(0x0)
|
||||
#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001)
|
||||
#define SPI_SSPIMSC_RORIM_MSB _u(0)
|
||||
#define SPI_SSPIMSC_RORIM_LSB _u(0)
|
||||
#define SPI_SSPIMSC_RORIM_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPRIS
|
||||
// Description : Raw interrupt status register, SSPRIS on page 3-10
|
||||
#define SPI_SSPRIS_OFFSET _u(0x00000018)
|
||||
#define SPI_SSPRIS_BITS _u(0x0000000f)
|
||||
#define SPI_SSPRIS_RESET _u(0x00000008)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPRIS_TXRIS
|
||||
// Description : Gives the raw interrupt state, prior to masking, of the
|
||||
// SSPTXINTR interrupt
|
||||
#define SPI_SSPRIS_TXRIS_RESET _u(0x1)
|
||||
#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008)
|
||||
#define SPI_SSPRIS_TXRIS_MSB _u(3)
|
||||
#define SPI_SSPRIS_TXRIS_LSB _u(3)
|
||||
#define SPI_SSPRIS_TXRIS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPRIS_RXRIS
|
||||
// Description : Gives the raw interrupt state, prior to masking, of the
|
||||
// SSPRXINTR interrupt
|
||||
#define SPI_SSPRIS_RXRIS_RESET _u(0x0)
|
||||
#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004)
|
||||
#define SPI_SSPRIS_RXRIS_MSB _u(2)
|
||||
#define SPI_SSPRIS_RXRIS_LSB _u(2)
|
||||
#define SPI_SSPRIS_RXRIS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPRIS_RTRIS
|
||||
// Description : Gives the raw interrupt state, prior to masking, of the
|
||||
// SSPRTINTR interrupt
|
||||
#define SPI_SSPRIS_RTRIS_RESET _u(0x0)
|
||||
#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002)
|
||||
#define SPI_SSPRIS_RTRIS_MSB _u(1)
|
||||
#define SPI_SSPRIS_RTRIS_LSB _u(1)
|
||||
#define SPI_SSPRIS_RTRIS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPRIS_RORRIS
|
||||
// Description : Gives the raw interrupt state, prior to masking, of the
|
||||
// SSPRORINTR interrupt
|
||||
#define SPI_SSPRIS_RORRIS_RESET _u(0x0)
|
||||
#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001)
|
||||
#define SPI_SSPRIS_RORRIS_MSB _u(0)
|
||||
#define SPI_SSPRIS_RORRIS_LSB _u(0)
|
||||
#define SPI_SSPRIS_RORRIS_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPMIS
|
||||
// Description : Masked interrupt status register, SSPMIS on page 3-11
|
||||
#define SPI_SSPMIS_OFFSET _u(0x0000001c)
|
||||
#define SPI_SSPMIS_BITS _u(0x0000000f)
|
||||
#define SPI_SSPMIS_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPMIS_TXMIS
|
||||
// Description : Gives the transmit FIFO masked interrupt state, after masking,
|
||||
// of the SSPTXINTR interrupt
|
||||
#define SPI_SSPMIS_TXMIS_RESET _u(0x0)
|
||||
#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008)
|
||||
#define SPI_SSPMIS_TXMIS_MSB _u(3)
|
||||
#define SPI_SSPMIS_TXMIS_LSB _u(3)
|
||||
#define SPI_SSPMIS_TXMIS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPMIS_RXMIS
|
||||
// Description : Gives the receive FIFO masked interrupt state, after masking,
|
||||
// of the SSPRXINTR interrupt
|
||||
#define SPI_SSPMIS_RXMIS_RESET _u(0x0)
|
||||
#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004)
|
||||
#define SPI_SSPMIS_RXMIS_MSB _u(2)
|
||||
#define SPI_SSPMIS_RXMIS_LSB _u(2)
|
||||
#define SPI_SSPMIS_RXMIS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPMIS_RTMIS
|
||||
// Description : Gives the receive timeout masked interrupt state, after
|
||||
// masking, of the SSPRTINTR interrupt
|
||||
#define SPI_SSPMIS_RTMIS_RESET _u(0x0)
|
||||
#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002)
|
||||
#define SPI_SSPMIS_RTMIS_MSB _u(1)
|
||||
#define SPI_SSPMIS_RTMIS_LSB _u(1)
|
||||
#define SPI_SSPMIS_RTMIS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPMIS_RORMIS
|
||||
// Description : Gives the receive over run masked interrupt status, after
|
||||
// masking, of the SSPRORINTR interrupt
|
||||
#define SPI_SSPMIS_RORMIS_RESET _u(0x0)
|
||||
#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001)
|
||||
#define SPI_SSPMIS_RORMIS_MSB _u(0)
|
||||
#define SPI_SSPMIS_RORMIS_LSB _u(0)
|
||||
#define SPI_SSPMIS_RORMIS_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPICR
|
||||
// Description : Interrupt clear register, SSPICR on page 3-11
|
||||
#define SPI_SSPICR_OFFSET _u(0x00000020)
|
||||
#define SPI_SSPICR_BITS _u(0x00000003)
|
||||
#define SPI_SSPICR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPICR_RTIC
|
||||
// Description : Clears the SSPRTINTR interrupt
|
||||
#define SPI_SSPICR_RTIC_RESET _u(0x0)
|
||||
#define SPI_SSPICR_RTIC_BITS _u(0x00000002)
|
||||
#define SPI_SSPICR_RTIC_MSB _u(1)
|
||||
#define SPI_SSPICR_RTIC_LSB _u(1)
|
||||
#define SPI_SSPICR_RTIC_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPICR_RORIC
|
||||
// Description : Clears the SSPRORINTR interrupt
|
||||
#define SPI_SSPICR_RORIC_RESET _u(0x0)
|
||||
#define SPI_SSPICR_RORIC_BITS _u(0x00000001)
|
||||
#define SPI_SSPICR_RORIC_MSB _u(0)
|
||||
#define SPI_SSPICR_RORIC_LSB _u(0)
|
||||
#define SPI_SSPICR_RORIC_ACCESS "WC"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPDMACR
|
||||
// Description : DMA control register, SSPDMACR on page 3-12
|
||||
#define SPI_SSPDMACR_OFFSET _u(0x00000024)
|
||||
#define SPI_SSPDMACR_BITS _u(0x00000003)
|
||||
#define SPI_SSPDMACR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPDMACR_TXDMAE
|
||||
// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the
|
||||
// transmit FIFO is enabled.
|
||||
#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0)
|
||||
#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002)
|
||||
#define SPI_SSPDMACR_TXDMAE_MSB _u(1)
|
||||
#define SPI_SSPDMACR_TXDMAE_LSB _u(1)
|
||||
#define SPI_SSPDMACR_TXDMAE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPDMACR_RXDMAE
|
||||
// Description : Receive DMA Enable. If this bit is set to 1, DMA for the
|
||||
// receive FIFO is enabled.
|
||||
#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0)
|
||||
#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001)
|
||||
#define SPI_SSPDMACR_RXDMAE_MSB _u(0)
|
||||
#define SPI_SSPDMACR_RXDMAE_LSB _u(0)
|
||||
#define SPI_SSPDMACR_RXDMAE_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPPERIPHID0
|
||||
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
|
||||
// 3-13
|
||||
#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0)
|
||||
#define SPI_SSPPERIPHID0_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPERIPHID0_RESET _u(0x00000022)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPPERIPHID0_PARTNUMBER0
|
||||
// Description : These bits read back as 0x22
|
||||
#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22)
|
||||
#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7)
|
||||
#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0)
|
||||
#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPPERIPHID1
|
||||
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
|
||||
// 3-13
|
||||
#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4)
|
||||
#define SPI_SSPPERIPHID1_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPERIPHID1_RESET _u(0x00000010)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPPERIPHID1_DESIGNER0
|
||||
// Description : These bits read back as 0x1
|
||||
#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1)
|
||||
#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0)
|
||||
#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7)
|
||||
#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4)
|
||||
#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPPERIPHID1_PARTNUMBER1
|
||||
// Description : These bits read back as 0x0
|
||||
#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0)
|
||||
#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f)
|
||||
#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3)
|
||||
#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0)
|
||||
#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPPERIPHID2
|
||||
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
|
||||
// 3-13
|
||||
#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8)
|
||||
#define SPI_SSPPERIPHID2_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPERIPHID2_RESET _u(0x00000034)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPPERIPHID2_REVISION
|
||||
// Description : These bits return the peripheral revision
|
||||
#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3)
|
||||
#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0)
|
||||
#define SPI_SSPPERIPHID2_REVISION_MSB _u(7)
|
||||
#define SPI_SSPPERIPHID2_REVISION_LSB _u(4)
|
||||
#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPPERIPHID2_DESIGNER1
|
||||
// Description : These bits read back as 0x4
|
||||
#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4)
|
||||
#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f)
|
||||
#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3)
|
||||
#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0)
|
||||
#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPPERIPHID3
|
||||
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
|
||||
// 3-13
|
||||
#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec)
|
||||
#define SPI_SSPPERIPHID3_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPERIPHID3_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPPERIPHID3_CONFIGURATION
|
||||
// Description : These bits read back as 0x00
|
||||
#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00)
|
||||
#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7)
|
||||
#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0)
|
||||
#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPPCELLID0
|
||||
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
|
||||
#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0)
|
||||
#define SPI_SSPPCELLID0_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPCELLID0_RESET _u(0x0000000d)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPPCELLID0_SSPPCELLID0
|
||||
// Description : These bits read back as 0x0D
|
||||
#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d)
|
||||
#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7)
|
||||
#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0)
|
||||
#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPPCELLID1
|
||||
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
|
||||
#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4)
|
||||
#define SPI_SSPPCELLID1_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPCELLID1_RESET _u(0x000000f0)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPPCELLID1_SSPPCELLID1
|
||||
// Description : These bits read back as 0xF0
|
||||
#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0)
|
||||
#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7)
|
||||
#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0)
|
||||
#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPPCELLID2
|
||||
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
|
||||
#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8)
|
||||
#define SPI_SSPPCELLID2_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPCELLID2_RESET _u(0x00000005)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPPCELLID2_SSPPCELLID2
|
||||
// Description : These bits read back as 0x05
|
||||
#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05)
|
||||
#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7)
|
||||
#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0)
|
||||
#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SPI_SSPPCELLID3
|
||||
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
|
||||
#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc)
|
||||
#define SPI_SSPPCELLID3_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPCELLID3_RESET _u(0x000000b1)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SPI_SSPPCELLID3_SSPPCELLID3
|
||||
// Description : These bits read back as 0xB1
|
||||
#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1)
|
||||
#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff)
|
||||
#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7)
|
||||
#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0)
|
||||
#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_SPI_H
|
||||
|
||||
|
|
@ -0,0 +1,808 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : SSI
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// Description : DW_apb_ssi has the following features:
|
||||
// * APB interface – Allows for easy integration into a
|
||||
// DesignWare Synthesizable Components for AMBA 2
|
||||
// implementation.
|
||||
// * APB3 and APB4 protocol support.
|
||||
// * Scalable APB data bus width – Supports APB data bus widths
|
||||
// of 8, 16, and 32 bits.
|
||||
// * Serial-master or serial-slave operation – Enables serial
|
||||
// communication with serial-master or serial-slave peripheral
|
||||
// devices.
|
||||
// * Programmable Dual/Quad/Octal SPI support in Master Mode.
|
||||
// * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support -
|
||||
// Enables the DW_apb_ssi master to perform operations with the
|
||||
// device in DDR and RDS modes when working in Dual/Quad/Octal
|
||||
// mode of operation.
|
||||
// * Data Mask Support - Enables the DW_apb_ssi to selectively
|
||||
// update the bytes in the device. This feature is applicable
|
||||
// only in enhanced SPI modes.
|
||||
// * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi
|
||||
// master to behave as a memory mapped I/O and fetches the data
|
||||
// from the device based on the APB read request. This feature
|
||||
// is applicable only in enhanced SPI modes.
|
||||
// * DMA Controller Interface – Enables the DW_apb_ssi to
|
||||
// interface to a DMA controller over the bus using a
|
||||
// handshaking interface for transfer requests.
|
||||
// * Independent masking of interrupts – Master collision,
|
||||
// transmit FIFO overflow, transmit FIFO empty, receive FIFO
|
||||
// full, receive FIFO underflow, and receive FIFO overflow
|
||||
// interrupts can all be masked independently.
|
||||
// * Multi-master contention detection – Informs the processor
|
||||
// of multiple serial-master accesses on the serial bus.
|
||||
// * Bypass of meta-stability flip-flops for synchronous clocks
|
||||
// – When the APB clock (pclk) and the DW_apb_ssi serial clock
|
||||
// (ssi_clk) are synchronous, meta-stable flip-flops are not
|
||||
// used when transferring control signals across these clock
|
||||
// domains.
|
||||
// * Programmable delay on the sample time of the received
|
||||
// serial data bit (rxd); enables programmable control of
|
||||
// routing delays resulting in higher serial data-bit rates.
|
||||
// * Programmable features:
|
||||
// - Serial interface operation – Choice of Motorola SPI, Texas
|
||||
// Instruments Synchronous Serial Protocol or National
|
||||
// Semiconductor Microwire.
|
||||
// - Clock bit-rate – Dynamic control of the serial bit rate of
|
||||
// the data transfer; used in only serial-master mode of
|
||||
// operation.
|
||||
// - Data Item size (4 to 32 bits) – Item size of each data
|
||||
// transfer under the control of the programmer.
|
||||
// * Configured features:
|
||||
// - FIFO depth – 16 words deep. The FIFO width is fixed at 32
|
||||
// bits.
|
||||
// - 1 slave select output.
|
||||
// - Hardware slave-select – Dedicated hardware slave-select
|
||||
// line.
|
||||
// - Combined interrupt line - one combined interrupt line from
|
||||
// the DW_apb_ssi to the interrupt controller.
|
||||
// - Interrupt polarity – active high interrupt lines.
|
||||
// - Serial clock polarity – low serial-clock polarity directly
|
||||
// after reset.
|
||||
// - Serial clock phase – capture on first edge of serial-clock
|
||||
// directly after reset.
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_SSI_H
|
||||
#define _HARDWARE_REGS_SSI_H
|
||||
// =============================================================================
|
||||
// Register : SSI_CTRLR0
|
||||
// Description : Control register 0
|
||||
#define SSI_CTRLR0_OFFSET _u(0x00000000)
|
||||
#define SSI_CTRLR0_BITS _u(0x017fffff)
|
||||
#define SSI_CTRLR0_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR0_SSTE
|
||||
// Description : Slave select toggle enable
|
||||
#define SSI_CTRLR0_SSTE_RESET _u(0x0)
|
||||
#define SSI_CTRLR0_SSTE_BITS _u(0x01000000)
|
||||
#define SSI_CTRLR0_SSTE_MSB _u(24)
|
||||
#define SSI_CTRLR0_SSTE_LSB _u(24)
|
||||
#define SSI_CTRLR0_SSTE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR0_SPI_FRF
|
||||
// Description : SPI frame format
|
||||
// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex
|
||||
// 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex
|
||||
// 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex
|
||||
#define SSI_CTRLR0_SPI_FRF_RESET _u(0x0)
|
||||
#define SSI_CTRLR0_SPI_FRF_BITS _u(0x00600000)
|
||||
#define SSI_CTRLR0_SPI_FRF_MSB _u(22)
|
||||
#define SSI_CTRLR0_SPI_FRF_LSB _u(21)
|
||||
#define SSI_CTRLR0_SPI_FRF_ACCESS "RW"
|
||||
#define SSI_CTRLR0_SPI_FRF_VALUE_STD _u(0x0)
|
||||
#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL _u(0x1)
|
||||
#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD _u(0x2)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR0_DFS_32
|
||||
// Description : Data frame size in 32b transfer mode
|
||||
// Value of n -> n+1 clocks per frame.
|
||||
#define SSI_CTRLR0_DFS_32_RESET _u(0x00)
|
||||
#define SSI_CTRLR0_DFS_32_BITS _u(0x001f0000)
|
||||
#define SSI_CTRLR0_DFS_32_MSB _u(20)
|
||||
#define SSI_CTRLR0_DFS_32_LSB _u(16)
|
||||
#define SSI_CTRLR0_DFS_32_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR0_CFS
|
||||
// Description : Control frame size
|
||||
// Value of n -> n+1 clocks per frame.
|
||||
#define SSI_CTRLR0_CFS_RESET _u(0x0)
|
||||
#define SSI_CTRLR0_CFS_BITS _u(0x0000f000)
|
||||
#define SSI_CTRLR0_CFS_MSB _u(15)
|
||||
#define SSI_CTRLR0_CFS_LSB _u(12)
|
||||
#define SSI_CTRLR0_CFS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR0_SRL
|
||||
// Description : Shift register loop (test mode)
|
||||
#define SSI_CTRLR0_SRL_RESET _u(0x0)
|
||||
#define SSI_CTRLR0_SRL_BITS _u(0x00000800)
|
||||
#define SSI_CTRLR0_SRL_MSB _u(11)
|
||||
#define SSI_CTRLR0_SRL_LSB _u(11)
|
||||
#define SSI_CTRLR0_SRL_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR0_SLV_OE
|
||||
// Description : Slave output enable
|
||||
#define SSI_CTRLR0_SLV_OE_RESET _u(0x0)
|
||||
#define SSI_CTRLR0_SLV_OE_BITS _u(0x00000400)
|
||||
#define SSI_CTRLR0_SLV_OE_MSB _u(10)
|
||||
#define SSI_CTRLR0_SLV_OE_LSB _u(10)
|
||||
#define SSI_CTRLR0_SLV_OE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR0_TMOD
|
||||
// Description : Transfer mode
|
||||
// 0x0 -> Both transmit and receive
|
||||
// 0x1 -> Transmit only (not for FRF == 0, standard SPI mode)
|
||||
// 0x2 -> Receive only (not for FRF == 0, standard SPI mode)
|
||||
// 0x3 -> EEPROM read mode (TX then RX; RX starts after control data TX'd)
|
||||
#define SSI_CTRLR0_TMOD_RESET _u(0x0)
|
||||
#define SSI_CTRLR0_TMOD_BITS _u(0x00000300)
|
||||
#define SSI_CTRLR0_TMOD_MSB _u(9)
|
||||
#define SSI_CTRLR0_TMOD_LSB _u(8)
|
||||
#define SSI_CTRLR0_TMOD_ACCESS "RW"
|
||||
#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX _u(0x0)
|
||||
#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY _u(0x1)
|
||||
#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY _u(0x2)
|
||||
#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ _u(0x3)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR0_SCPOL
|
||||
// Description : Serial clock polarity
|
||||
#define SSI_CTRLR0_SCPOL_RESET _u(0x0)
|
||||
#define SSI_CTRLR0_SCPOL_BITS _u(0x00000080)
|
||||
#define SSI_CTRLR0_SCPOL_MSB _u(7)
|
||||
#define SSI_CTRLR0_SCPOL_LSB _u(7)
|
||||
#define SSI_CTRLR0_SCPOL_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR0_SCPH
|
||||
// Description : Serial clock phase
|
||||
#define SSI_CTRLR0_SCPH_RESET _u(0x0)
|
||||
#define SSI_CTRLR0_SCPH_BITS _u(0x00000040)
|
||||
#define SSI_CTRLR0_SCPH_MSB _u(6)
|
||||
#define SSI_CTRLR0_SCPH_LSB _u(6)
|
||||
#define SSI_CTRLR0_SCPH_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR0_FRF
|
||||
// Description : Frame format
|
||||
#define SSI_CTRLR0_FRF_RESET _u(0x0)
|
||||
#define SSI_CTRLR0_FRF_BITS _u(0x00000030)
|
||||
#define SSI_CTRLR0_FRF_MSB _u(5)
|
||||
#define SSI_CTRLR0_FRF_LSB _u(4)
|
||||
#define SSI_CTRLR0_FRF_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR0_DFS
|
||||
// Description : Data frame size
|
||||
#define SSI_CTRLR0_DFS_RESET _u(0x0)
|
||||
#define SSI_CTRLR0_DFS_BITS _u(0x0000000f)
|
||||
#define SSI_CTRLR0_DFS_MSB _u(3)
|
||||
#define SSI_CTRLR0_DFS_LSB _u(0)
|
||||
#define SSI_CTRLR0_DFS_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_CTRLR1
|
||||
// Description : Master Control register 1
|
||||
#define SSI_CTRLR1_OFFSET _u(0x00000004)
|
||||
#define SSI_CTRLR1_BITS _u(0x0000ffff)
|
||||
#define SSI_CTRLR1_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_CTRLR1_NDF
|
||||
// Description : Number of data frames
|
||||
#define SSI_CTRLR1_NDF_RESET _u(0x0000)
|
||||
#define SSI_CTRLR1_NDF_BITS _u(0x0000ffff)
|
||||
#define SSI_CTRLR1_NDF_MSB _u(15)
|
||||
#define SSI_CTRLR1_NDF_LSB _u(0)
|
||||
#define SSI_CTRLR1_NDF_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_SSIENR
|
||||
// Description : SSI Enable
|
||||
#define SSI_SSIENR_OFFSET _u(0x00000008)
|
||||
#define SSI_SSIENR_BITS _u(0x00000001)
|
||||
#define SSI_SSIENR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SSIENR_SSI_EN
|
||||
// Description : SSI enable
|
||||
#define SSI_SSIENR_SSI_EN_RESET _u(0x0)
|
||||
#define SSI_SSIENR_SSI_EN_BITS _u(0x00000001)
|
||||
#define SSI_SSIENR_SSI_EN_MSB _u(0)
|
||||
#define SSI_SSIENR_SSI_EN_LSB _u(0)
|
||||
#define SSI_SSIENR_SSI_EN_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_MWCR
|
||||
// Description : Microwire Control
|
||||
#define SSI_MWCR_OFFSET _u(0x0000000c)
|
||||
#define SSI_MWCR_BITS _u(0x00000007)
|
||||
#define SSI_MWCR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_MWCR_MHS
|
||||
// Description : Microwire handshaking
|
||||
#define SSI_MWCR_MHS_RESET _u(0x0)
|
||||
#define SSI_MWCR_MHS_BITS _u(0x00000004)
|
||||
#define SSI_MWCR_MHS_MSB _u(2)
|
||||
#define SSI_MWCR_MHS_LSB _u(2)
|
||||
#define SSI_MWCR_MHS_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_MWCR_MDD
|
||||
// Description : Microwire control
|
||||
#define SSI_MWCR_MDD_RESET _u(0x0)
|
||||
#define SSI_MWCR_MDD_BITS _u(0x00000002)
|
||||
#define SSI_MWCR_MDD_MSB _u(1)
|
||||
#define SSI_MWCR_MDD_LSB _u(1)
|
||||
#define SSI_MWCR_MDD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_MWCR_MWMOD
|
||||
// Description : Microwire transfer mode
|
||||
#define SSI_MWCR_MWMOD_RESET _u(0x0)
|
||||
#define SSI_MWCR_MWMOD_BITS _u(0x00000001)
|
||||
#define SSI_MWCR_MWMOD_MSB _u(0)
|
||||
#define SSI_MWCR_MWMOD_LSB _u(0)
|
||||
#define SSI_MWCR_MWMOD_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_SER
|
||||
// Description : Slave enable
|
||||
// For each bit:
|
||||
// 0 -> slave not selected
|
||||
// 1 -> slave selected
|
||||
#define SSI_SER_OFFSET _u(0x00000010)
|
||||
#define SSI_SER_BITS _u(0x00000001)
|
||||
#define SSI_SER_RESET _u(0x00000000)
|
||||
#define SSI_SER_MSB _u(0)
|
||||
#define SSI_SER_LSB _u(0)
|
||||
#define SSI_SER_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_BAUDR
|
||||
// Description : Baud rate
|
||||
#define SSI_BAUDR_OFFSET _u(0x00000014)
|
||||
#define SSI_BAUDR_BITS _u(0x0000ffff)
|
||||
#define SSI_BAUDR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_BAUDR_SCKDV
|
||||
// Description : SSI clock divider
|
||||
#define SSI_BAUDR_SCKDV_RESET _u(0x0000)
|
||||
#define SSI_BAUDR_SCKDV_BITS _u(0x0000ffff)
|
||||
#define SSI_BAUDR_SCKDV_MSB _u(15)
|
||||
#define SSI_BAUDR_SCKDV_LSB _u(0)
|
||||
#define SSI_BAUDR_SCKDV_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_TXFTLR
|
||||
// Description : TX FIFO threshold level
|
||||
#define SSI_TXFTLR_OFFSET _u(0x00000018)
|
||||
#define SSI_TXFTLR_BITS _u(0x000000ff)
|
||||
#define SSI_TXFTLR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_TXFTLR_TFT
|
||||
// Description : Transmit FIFO threshold
|
||||
#define SSI_TXFTLR_TFT_RESET _u(0x00)
|
||||
#define SSI_TXFTLR_TFT_BITS _u(0x000000ff)
|
||||
#define SSI_TXFTLR_TFT_MSB _u(7)
|
||||
#define SSI_TXFTLR_TFT_LSB _u(0)
|
||||
#define SSI_TXFTLR_TFT_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_RXFTLR
|
||||
// Description : RX FIFO threshold level
|
||||
#define SSI_RXFTLR_OFFSET _u(0x0000001c)
|
||||
#define SSI_RXFTLR_BITS _u(0x000000ff)
|
||||
#define SSI_RXFTLR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_RXFTLR_RFT
|
||||
// Description : Receive FIFO threshold
|
||||
#define SSI_RXFTLR_RFT_RESET _u(0x00)
|
||||
#define SSI_RXFTLR_RFT_BITS _u(0x000000ff)
|
||||
#define SSI_RXFTLR_RFT_MSB _u(7)
|
||||
#define SSI_RXFTLR_RFT_LSB _u(0)
|
||||
#define SSI_RXFTLR_RFT_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_TXFLR
|
||||
// Description : TX FIFO level
|
||||
#define SSI_TXFLR_OFFSET _u(0x00000020)
|
||||
#define SSI_TXFLR_BITS _u(0x000000ff)
|
||||
#define SSI_TXFLR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_TXFLR_TFTFL
|
||||
// Description : Transmit FIFO level
|
||||
#define SSI_TXFLR_TFTFL_RESET _u(0x00)
|
||||
#define SSI_TXFLR_TFTFL_BITS _u(0x000000ff)
|
||||
#define SSI_TXFLR_TFTFL_MSB _u(7)
|
||||
#define SSI_TXFLR_TFTFL_LSB _u(0)
|
||||
#define SSI_TXFLR_TFTFL_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_RXFLR
|
||||
// Description : RX FIFO level
|
||||
#define SSI_RXFLR_OFFSET _u(0x00000024)
|
||||
#define SSI_RXFLR_BITS _u(0x000000ff)
|
||||
#define SSI_RXFLR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_RXFLR_RXTFL
|
||||
// Description : Receive FIFO level
|
||||
#define SSI_RXFLR_RXTFL_RESET _u(0x00)
|
||||
#define SSI_RXFLR_RXTFL_BITS _u(0x000000ff)
|
||||
#define SSI_RXFLR_RXTFL_MSB _u(7)
|
||||
#define SSI_RXFLR_RXTFL_LSB _u(0)
|
||||
#define SSI_RXFLR_RXTFL_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_SR
|
||||
// Description : Status register
|
||||
#define SSI_SR_OFFSET _u(0x00000028)
|
||||
#define SSI_SR_BITS _u(0x0000007f)
|
||||
#define SSI_SR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SR_DCOL
|
||||
// Description : Data collision error
|
||||
#define SSI_SR_DCOL_RESET _u(0x0)
|
||||
#define SSI_SR_DCOL_BITS _u(0x00000040)
|
||||
#define SSI_SR_DCOL_MSB _u(6)
|
||||
#define SSI_SR_DCOL_LSB _u(6)
|
||||
#define SSI_SR_DCOL_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SR_TXE
|
||||
// Description : Transmission error
|
||||
#define SSI_SR_TXE_RESET _u(0x0)
|
||||
#define SSI_SR_TXE_BITS _u(0x00000020)
|
||||
#define SSI_SR_TXE_MSB _u(5)
|
||||
#define SSI_SR_TXE_LSB _u(5)
|
||||
#define SSI_SR_TXE_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SR_RFF
|
||||
// Description : Receive FIFO full
|
||||
#define SSI_SR_RFF_RESET _u(0x0)
|
||||
#define SSI_SR_RFF_BITS _u(0x00000010)
|
||||
#define SSI_SR_RFF_MSB _u(4)
|
||||
#define SSI_SR_RFF_LSB _u(4)
|
||||
#define SSI_SR_RFF_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SR_RFNE
|
||||
// Description : Receive FIFO not empty
|
||||
#define SSI_SR_RFNE_RESET _u(0x0)
|
||||
#define SSI_SR_RFNE_BITS _u(0x00000008)
|
||||
#define SSI_SR_RFNE_MSB _u(3)
|
||||
#define SSI_SR_RFNE_LSB _u(3)
|
||||
#define SSI_SR_RFNE_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SR_TFE
|
||||
// Description : Transmit FIFO empty
|
||||
#define SSI_SR_TFE_RESET _u(0x0)
|
||||
#define SSI_SR_TFE_BITS _u(0x00000004)
|
||||
#define SSI_SR_TFE_MSB _u(2)
|
||||
#define SSI_SR_TFE_LSB _u(2)
|
||||
#define SSI_SR_TFE_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SR_TFNF
|
||||
// Description : Transmit FIFO not full
|
||||
#define SSI_SR_TFNF_RESET _u(0x0)
|
||||
#define SSI_SR_TFNF_BITS _u(0x00000002)
|
||||
#define SSI_SR_TFNF_MSB _u(1)
|
||||
#define SSI_SR_TFNF_LSB _u(1)
|
||||
#define SSI_SR_TFNF_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SR_BUSY
|
||||
// Description : SSI busy flag
|
||||
#define SSI_SR_BUSY_RESET _u(0x0)
|
||||
#define SSI_SR_BUSY_BITS _u(0x00000001)
|
||||
#define SSI_SR_BUSY_MSB _u(0)
|
||||
#define SSI_SR_BUSY_LSB _u(0)
|
||||
#define SSI_SR_BUSY_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_IMR
|
||||
// Description : Interrupt mask
|
||||
#define SSI_IMR_OFFSET _u(0x0000002c)
|
||||
#define SSI_IMR_BITS _u(0x0000003f)
|
||||
#define SSI_IMR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_IMR_MSTIM
|
||||
// Description : Multi-master contention interrupt mask
|
||||
#define SSI_IMR_MSTIM_RESET _u(0x0)
|
||||
#define SSI_IMR_MSTIM_BITS _u(0x00000020)
|
||||
#define SSI_IMR_MSTIM_MSB _u(5)
|
||||
#define SSI_IMR_MSTIM_LSB _u(5)
|
||||
#define SSI_IMR_MSTIM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_IMR_RXFIM
|
||||
// Description : Receive FIFO full interrupt mask
|
||||
#define SSI_IMR_RXFIM_RESET _u(0x0)
|
||||
#define SSI_IMR_RXFIM_BITS _u(0x00000010)
|
||||
#define SSI_IMR_RXFIM_MSB _u(4)
|
||||
#define SSI_IMR_RXFIM_LSB _u(4)
|
||||
#define SSI_IMR_RXFIM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_IMR_RXOIM
|
||||
// Description : Receive FIFO overflow interrupt mask
|
||||
#define SSI_IMR_RXOIM_RESET _u(0x0)
|
||||
#define SSI_IMR_RXOIM_BITS _u(0x00000008)
|
||||
#define SSI_IMR_RXOIM_MSB _u(3)
|
||||
#define SSI_IMR_RXOIM_LSB _u(3)
|
||||
#define SSI_IMR_RXOIM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_IMR_RXUIM
|
||||
// Description : Receive FIFO underflow interrupt mask
|
||||
#define SSI_IMR_RXUIM_RESET _u(0x0)
|
||||
#define SSI_IMR_RXUIM_BITS _u(0x00000004)
|
||||
#define SSI_IMR_RXUIM_MSB _u(2)
|
||||
#define SSI_IMR_RXUIM_LSB _u(2)
|
||||
#define SSI_IMR_RXUIM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_IMR_TXOIM
|
||||
// Description : Transmit FIFO overflow interrupt mask
|
||||
#define SSI_IMR_TXOIM_RESET _u(0x0)
|
||||
#define SSI_IMR_TXOIM_BITS _u(0x00000002)
|
||||
#define SSI_IMR_TXOIM_MSB _u(1)
|
||||
#define SSI_IMR_TXOIM_LSB _u(1)
|
||||
#define SSI_IMR_TXOIM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_IMR_TXEIM
|
||||
// Description : Transmit FIFO empty interrupt mask
|
||||
#define SSI_IMR_TXEIM_RESET _u(0x0)
|
||||
#define SSI_IMR_TXEIM_BITS _u(0x00000001)
|
||||
#define SSI_IMR_TXEIM_MSB _u(0)
|
||||
#define SSI_IMR_TXEIM_LSB _u(0)
|
||||
#define SSI_IMR_TXEIM_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_ISR
|
||||
// Description : Interrupt status
|
||||
#define SSI_ISR_OFFSET _u(0x00000030)
|
||||
#define SSI_ISR_BITS _u(0x0000003f)
|
||||
#define SSI_ISR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_ISR_MSTIS
|
||||
// Description : Multi-master contention interrupt status
|
||||
#define SSI_ISR_MSTIS_RESET _u(0x0)
|
||||
#define SSI_ISR_MSTIS_BITS _u(0x00000020)
|
||||
#define SSI_ISR_MSTIS_MSB _u(5)
|
||||
#define SSI_ISR_MSTIS_LSB _u(5)
|
||||
#define SSI_ISR_MSTIS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_ISR_RXFIS
|
||||
// Description : Receive FIFO full interrupt status
|
||||
#define SSI_ISR_RXFIS_RESET _u(0x0)
|
||||
#define SSI_ISR_RXFIS_BITS _u(0x00000010)
|
||||
#define SSI_ISR_RXFIS_MSB _u(4)
|
||||
#define SSI_ISR_RXFIS_LSB _u(4)
|
||||
#define SSI_ISR_RXFIS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_ISR_RXOIS
|
||||
// Description : Receive FIFO overflow interrupt status
|
||||
#define SSI_ISR_RXOIS_RESET _u(0x0)
|
||||
#define SSI_ISR_RXOIS_BITS _u(0x00000008)
|
||||
#define SSI_ISR_RXOIS_MSB _u(3)
|
||||
#define SSI_ISR_RXOIS_LSB _u(3)
|
||||
#define SSI_ISR_RXOIS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_ISR_RXUIS
|
||||
// Description : Receive FIFO underflow interrupt status
|
||||
#define SSI_ISR_RXUIS_RESET _u(0x0)
|
||||
#define SSI_ISR_RXUIS_BITS _u(0x00000004)
|
||||
#define SSI_ISR_RXUIS_MSB _u(2)
|
||||
#define SSI_ISR_RXUIS_LSB _u(2)
|
||||
#define SSI_ISR_RXUIS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_ISR_TXOIS
|
||||
// Description : Transmit FIFO overflow interrupt status
|
||||
#define SSI_ISR_TXOIS_RESET _u(0x0)
|
||||
#define SSI_ISR_TXOIS_BITS _u(0x00000002)
|
||||
#define SSI_ISR_TXOIS_MSB _u(1)
|
||||
#define SSI_ISR_TXOIS_LSB _u(1)
|
||||
#define SSI_ISR_TXOIS_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_ISR_TXEIS
|
||||
// Description : Transmit FIFO empty interrupt status
|
||||
#define SSI_ISR_TXEIS_RESET _u(0x0)
|
||||
#define SSI_ISR_TXEIS_BITS _u(0x00000001)
|
||||
#define SSI_ISR_TXEIS_MSB _u(0)
|
||||
#define SSI_ISR_TXEIS_LSB _u(0)
|
||||
#define SSI_ISR_TXEIS_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_RISR
|
||||
// Description : Raw interrupt status
|
||||
#define SSI_RISR_OFFSET _u(0x00000034)
|
||||
#define SSI_RISR_BITS _u(0x0000003f)
|
||||
#define SSI_RISR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_RISR_MSTIR
|
||||
// Description : Multi-master contention raw interrupt status
|
||||
#define SSI_RISR_MSTIR_RESET _u(0x0)
|
||||
#define SSI_RISR_MSTIR_BITS _u(0x00000020)
|
||||
#define SSI_RISR_MSTIR_MSB _u(5)
|
||||
#define SSI_RISR_MSTIR_LSB _u(5)
|
||||
#define SSI_RISR_MSTIR_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_RISR_RXFIR
|
||||
// Description : Receive FIFO full raw interrupt status
|
||||
#define SSI_RISR_RXFIR_RESET _u(0x0)
|
||||
#define SSI_RISR_RXFIR_BITS _u(0x00000010)
|
||||
#define SSI_RISR_RXFIR_MSB _u(4)
|
||||
#define SSI_RISR_RXFIR_LSB _u(4)
|
||||
#define SSI_RISR_RXFIR_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_RISR_RXOIR
|
||||
// Description : Receive FIFO overflow raw interrupt status
|
||||
#define SSI_RISR_RXOIR_RESET _u(0x0)
|
||||
#define SSI_RISR_RXOIR_BITS _u(0x00000008)
|
||||
#define SSI_RISR_RXOIR_MSB _u(3)
|
||||
#define SSI_RISR_RXOIR_LSB _u(3)
|
||||
#define SSI_RISR_RXOIR_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_RISR_RXUIR
|
||||
// Description : Receive FIFO underflow raw interrupt status
|
||||
#define SSI_RISR_RXUIR_RESET _u(0x0)
|
||||
#define SSI_RISR_RXUIR_BITS _u(0x00000004)
|
||||
#define SSI_RISR_RXUIR_MSB _u(2)
|
||||
#define SSI_RISR_RXUIR_LSB _u(2)
|
||||
#define SSI_RISR_RXUIR_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_RISR_TXOIR
|
||||
// Description : Transmit FIFO overflow raw interrupt status
|
||||
#define SSI_RISR_TXOIR_RESET _u(0x0)
|
||||
#define SSI_RISR_TXOIR_BITS _u(0x00000002)
|
||||
#define SSI_RISR_TXOIR_MSB _u(1)
|
||||
#define SSI_RISR_TXOIR_LSB _u(1)
|
||||
#define SSI_RISR_TXOIR_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_RISR_TXEIR
|
||||
// Description : Transmit FIFO empty raw interrupt status
|
||||
#define SSI_RISR_TXEIR_RESET _u(0x0)
|
||||
#define SSI_RISR_TXEIR_BITS _u(0x00000001)
|
||||
#define SSI_RISR_TXEIR_MSB _u(0)
|
||||
#define SSI_RISR_TXEIR_LSB _u(0)
|
||||
#define SSI_RISR_TXEIR_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_TXOICR
|
||||
// Description : TX FIFO overflow interrupt clear
|
||||
// Clear-on-read transmit FIFO overflow interrupt
|
||||
#define SSI_TXOICR_OFFSET _u(0x00000038)
|
||||
#define SSI_TXOICR_BITS _u(0x00000001)
|
||||
#define SSI_TXOICR_RESET _u(0x00000000)
|
||||
#define SSI_TXOICR_MSB _u(0)
|
||||
#define SSI_TXOICR_LSB _u(0)
|
||||
#define SSI_TXOICR_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_RXOICR
|
||||
// Description : RX FIFO overflow interrupt clear
|
||||
// Clear-on-read receive FIFO overflow interrupt
|
||||
#define SSI_RXOICR_OFFSET _u(0x0000003c)
|
||||
#define SSI_RXOICR_BITS _u(0x00000001)
|
||||
#define SSI_RXOICR_RESET _u(0x00000000)
|
||||
#define SSI_RXOICR_MSB _u(0)
|
||||
#define SSI_RXOICR_LSB _u(0)
|
||||
#define SSI_RXOICR_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_RXUICR
|
||||
// Description : RX FIFO underflow interrupt clear
|
||||
// Clear-on-read receive FIFO underflow interrupt
|
||||
#define SSI_RXUICR_OFFSET _u(0x00000040)
|
||||
#define SSI_RXUICR_BITS _u(0x00000001)
|
||||
#define SSI_RXUICR_RESET _u(0x00000000)
|
||||
#define SSI_RXUICR_MSB _u(0)
|
||||
#define SSI_RXUICR_LSB _u(0)
|
||||
#define SSI_RXUICR_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_MSTICR
|
||||
// Description : Multi-master interrupt clear
|
||||
// Clear-on-read multi-master contention interrupt
|
||||
#define SSI_MSTICR_OFFSET _u(0x00000044)
|
||||
#define SSI_MSTICR_BITS _u(0x00000001)
|
||||
#define SSI_MSTICR_RESET _u(0x00000000)
|
||||
#define SSI_MSTICR_MSB _u(0)
|
||||
#define SSI_MSTICR_LSB _u(0)
|
||||
#define SSI_MSTICR_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_ICR
|
||||
// Description : Interrupt clear
|
||||
// Clear-on-read all active interrupts
|
||||
#define SSI_ICR_OFFSET _u(0x00000048)
|
||||
#define SSI_ICR_BITS _u(0x00000001)
|
||||
#define SSI_ICR_RESET _u(0x00000000)
|
||||
#define SSI_ICR_MSB _u(0)
|
||||
#define SSI_ICR_LSB _u(0)
|
||||
#define SSI_ICR_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_DMACR
|
||||
// Description : DMA control
|
||||
#define SSI_DMACR_OFFSET _u(0x0000004c)
|
||||
#define SSI_DMACR_BITS _u(0x00000003)
|
||||
#define SSI_DMACR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_DMACR_TDMAE
|
||||
// Description : Transmit DMA enable
|
||||
#define SSI_DMACR_TDMAE_RESET _u(0x0)
|
||||
#define SSI_DMACR_TDMAE_BITS _u(0x00000002)
|
||||
#define SSI_DMACR_TDMAE_MSB _u(1)
|
||||
#define SSI_DMACR_TDMAE_LSB _u(1)
|
||||
#define SSI_DMACR_TDMAE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_DMACR_RDMAE
|
||||
// Description : Receive DMA enable
|
||||
#define SSI_DMACR_RDMAE_RESET _u(0x0)
|
||||
#define SSI_DMACR_RDMAE_BITS _u(0x00000001)
|
||||
#define SSI_DMACR_RDMAE_MSB _u(0)
|
||||
#define SSI_DMACR_RDMAE_LSB _u(0)
|
||||
#define SSI_DMACR_RDMAE_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_DMATDLR
|
||||
// Description : DMA TX data level
|
||||
#define SSI_DMATDLR_OFFSET _u(0x00000050)
|
||||
#define SSI_DMATDLR_BITS _u(0x000000ff)
|
||||
#define SSI_DMATDLR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_DMATDLR_DMATDL
|
||||
// Description : Transmit data watermark level
|
||||
#define SSI_DMATDLR_DMATDL_RESET _u(0x00)
|
||||
#define SSI_DMATDLR_DMATDL_BITS _u(0x000000ff)
|
||||
#define SSI_DMATDLR_DMATDL_MSB _u(7)
|
||||
#define SSI_DMATDLR_DMATDL_LSB _u(0)
|
||||
#define SSI_DMATDLR_DMATDL_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_DMARDLR
|
||||
// Description : DMA RX data level
|
||||
#define SSI_DMARDLR_OFFSET _u(0x00000054)
|
||||
#define SSI_DMARDLR_BITS _u(0x000000ff)
|
||||
#define SSI_DMARDLR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_DMARDLR_DMARDL
|
||||
// Description : Receive data watermark level (DMARDLR+1)
|
||||
#define SSI_DMARDLR_DMARDL_RESET _u(0x00)
|
||||
#define SSI_DMARDLR_DMARDL_BITS _u(0x000000ff)
|
||||
#define SSI_DMARDLR_DMARDL_MSB _u(7)
|
||||
#define SSI_DMARDLR_DMARDL_LSB _u(0)
|
||||
#define SSI_DMARDLR_DMARDL_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_IDR
|
||||
// Description : Identification register
|
||||
#define SSI_IDR_OFFSET _u(0x00000058)
|
||||
#define SSI_IDR_BITS _u(0xffffffff)
|
||||
#define SSI_IDR_RESET _u(0x51535049)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_IDR_IDCODE
|
||||
// Description : Peripheral dentification code
|
||||
#define SSI_IDR_IDCODE_RESET _u(0x51535049)
|
||||
#define SSI_IDR_IDCODE_BITS _u(0xffffffff)
|
||||
#define SSI_IDR_IDCODE_MSB _u(31)
|
||||
#define SSI_IDR_IDCODE_LSB _u(0)
|
||||
#define SSI_IDR_IDCODE_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_SSI_VERSION_ID
|
||||
// Description : Version ID
|
||||
#define SSI_SSI_VERSION_ID_OFFSET _u(0x0000005c)
|
||||
#define SSI_SSI_VERSION_ID_BITS _u(0xffffffff)
|
||||
#define SSI_SSI_VERSION_ID_RESET _u(0x3430312a)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SSI_VERSION_ID_SSI_COMP_VERSION
|
||||
// Description : SNPS component version (format X.YY)
|
||||
#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET _u(0x3430312a)
|
||||
#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS _u(0xffffffff)
|
||||
#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB _u(31)
|
||||
#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB _u(0)
|
||||
#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SSI_DR0
|
||||
// Description : Data Register 0 (of 36)
|
||||
#define SSI_DR0_OFFSET _u(0x00000060)
|
||||
#define SSI_DR0_BITS _u(0xffffffff)
|
||||
#define SSI_DR0_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_DR0_DR
|
||||
// Description : First data register of 36
|
||||
#define SSI_DR0_DR_RESET _u(0x00000000)
|
||||
#define SSI_DR0_DR_BITS _u(0xffffffff)
|
||||
#define SSI_DR0_DR_MSB _u(31)
|
||||
#define SSI_DR0_DR_LSB _u(0)
|
||||
#define SSI_DR0_DR_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_RX_SAMPLE_DLY
|
||||
// Description : RX sample delay
|
||||
#define SSI_RX_SAMPLE_DLY_OFFSET _u(0x000000f0)
|
||||
#define SSI_RX_SAMPLE_DLY_BITS _u(0x000000ff)
|
||||
#define SSI_RX_SAMPLE_DLY_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_RX_SAMPLE_DLY_RSD
|
||||
// Description : RXD sample delay (in SCLK cycles)
|
||||
#define SSI_RX_SAMPLE_DLY_RSD_RESET _u(0x00)
|
||||
#define SSI_RX_SAMPLE_DLY_RSD_BITS _u(0x000000ff)
|
||||
#define SSI_RX_SAMPLE_DLY_RSD_MSB _u(7)
|
||||
#define SSI_RX_SAMPLE_DLY_RSD_LSB _u(0)
|
||||
#define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SSI_SPI_CTRLR0
|
||||
// Description : SPI control
|
||||
#define SSI_SPI_CTRLR0_OFFSET _u(0x000000f4)
|
||||
#define SSI_SPI_CTRLR0_BITS _u(0xff07fb3f)
|
||||
#define SSI_SPI_CTRLR0_RESET _u(0x03000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SPI_CTRLR0_XIP_CMD
|
||||
// Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append
|
||||
// to Address (INST_L = 0-bit)
|
||||
#define SSI_SPI_CTRLR0_XIP_CMD_RESET _u(0x03)
|
||||
#define SSI_SPI_CTRLR0_XIP_CMD_BITS _u(0xff000000)
|
||||
#define SSI_SPI_CTRLR0_XIP_CMD_MSB _u(31)
|
||||
#define SSI_SPI_CTRLR0_XIP_CMD_LSB _u(24)
|
||||
#define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SPI_CTRLR0_SPI_RXDS_EN
|
||||
// Description : Read data strobe enable
|
||||
#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET _u(0x0)
|
||||
#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS _u(0x00040000)
|
||||
#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB _u(18)
|
||||
#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB _u(18)
|
||||
#define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SPI_CTRLR0_INST_DDR_EN
|
||||
// Description : Instruction DDR transfer enable
|
||||
#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET _u(0x0)
|
||||
#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS _u(0x00020000)
|
||||
#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB _u(17)
|
||||
#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB _u(17)
|
||||
#define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SPI_CTRLR0_SPI_DDR_EN
|
||||
// Description : SPI DDR transfer enable
|
||||
#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET _u(0x0)
|
||||
#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS _u(0x00010000)
|
||||
#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB _u(16)
|
||||
#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB _u(16)
|
||||
#define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SPI_CTRLR0_WAIT_CYCLES
|
||||
// Description : Wait cycles between control frame transmit and data reception
|
||||
// (in SCLK cycles)
|
||||
#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET _u(0x00)
|
||||
#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS _u(0x0000f800)
|
||||
#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB _u(15)
|
||||
#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB _u(11)
|
||||
#define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SPI_CTRLR0_INST_L
|
||||
// Description : Instruction length (0/4/8/16b)
|
||||
// 0x0 -> No instruction
|
||||
// 0x1 -> 4-bit instruction
|
||||
// 0x2 -> 8-bit instruction
|
||||
// 0x3 -> 16-bit instruction
|
||||
#define SSI_SPI_CTRLR0_INST_L_RESET _u(0x0)
|
||||
#define SSI_SPI_CTRLR0_INST_L_BITS _u(0x00000300)
|
||||
#define SSI_SPI_CTRLR0_INST_L_MSB _u(9)
|
||||
#define SSI_SPI_CTRLR0_INST_L_LSB _u(8)
|
||||
#define SSI_SPI_CTRLR0_INST_L_ACCESS "RW"
|
||||
#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE _u(0x0)
|
||||
#define SSI_SPI_CTRLR0_INST_L_VALUE_4B _u(0x1)
|
||||
#define SSI_SPI_CTRLR0_INST_L_VALUE_8B _u(0x2)
|
||||
#define SSI_SPI_CTRLR0_INST_L_VALUE_16B _u(0x3)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SPI_CTRLR0_ADDR_L
|
||||
// Description : Address length (0b-60b in 4b increments)
|
||||
#define SSI_SPI_CTRLR0_ADDR_L_RESET _u(0x0)
|
||||
#define SSI_SPI_CTRLR0_ADDR_L_BITS _u(0x0000003c)
|
||||
#define SSI_SPI_CTRLR0_ADDR_L_MSB _u(5)
|
||||
#define SSI_SPI_CTRLR0_ADDR_L_LSB _u(2)
|
||||
#define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_SPI_CTRLR0_TRANS_TYPE
|
||||
// Description : Address and instruction transfer format
|
||||
// 0x0 -> Command and address both in standard SPI frame format
|
||||
// 0x1 -> Command in standard SPI format, address in format specified by FRF
|
||||
// 0x2 -> Command and address both in format specified by FRF (e.g. Dual-SPI)
|
||||
#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0)
|
||||
#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003)
|
||||
#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1)
|
||||
#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB _u(0)
|
||||
#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW"
|
||||
#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A _u(0x0)
|
||||
#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A _u(0x1)
|
||||
#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A _u(0x2)
|
||||
// =============================================================================
|
||||
// Register : SSI_TXD_DRIVE_EDGE
|
||||
// Description : TX drive edge
|
||||
#define SSI_TXD_DRIVE_EDGE_OFFSET _u(0x000000f8)
|
||||
#define SSI_TXD_DRIVE_EDGE_BITS _u(0x000000ff)
|
||||
#define SSI_TXD_DRIVE_EDGE_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SSI_TXD_DRIVE_EDGE_TDE
|
||||
// Description : TXD drive edge
|
||||
#define SSI_TXD_DRIVE_EDGE_TDE_RESET _u(0x00)
|
||||
#define SSI_TXD_DRIVE_EDGE_TDE_BITS _u(0x000000ff)
|
||||
#define SSI_TXD_DRIVE_EDGE_TDE_MSB _u(7)
|
||||
#define SSI_TXD_DRIVE_EDGE_TDE_LSB _u(0)
|
||||
#define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_SSI_H
|
||||
|
||||
|
|
@ -0,0 +1,252 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : SYSCFG
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// Description : Register block for various chip control signals
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_SYSCFG_H
|
||||
#define _HARDWARE_REGS_SYSCFG_H
|
||||
// =============================================================================
|
||||
// Register : SYSCFG_PROC0_NMI_MASK
|
||||
// Description : Processor core 0 NMI source mask
|
||||
// Set a bit high to enable NMI from that IRQ
|
||||
#define SYSCFG_PROC0_NMI_MASK_OFFSET _u(0x00000000)
|
||||
#define SYSCFG_PROC0_NMI_MASK_BITS _u(0xffffffff)
|
||||
#define SYSCFG_PROC0_NMI_MASK_RESET _u(0x00000000)
|
||||
#define SYSCFG_PROC0_NMI_MASK_MSB _u(31)
|
||||
#define SYSCFG_PROC0_NMI_MASK_LSB _u(0)
|
||||
#define SYSCFG_PROC0_NMI_MASK_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SYSCFG_PROC1_NMI_MASK
|
||||
// Description : Processor core 1 NMI source mask
|
||||
// Set a bit high to enable NMI from that IRQ
|
||||
#define SYSCFG_PROC1_NMI_MASK_OFFSET _u(0x00000004)
|
||||
#define SYSCFG_PROC1_NMI_MASK_BITS _u(0xffffffff)
|
||||
#define SYSCFG_PROC1_NMI_MASK_RESET _u(0x00000000)
|
||||
#define SYSCFG_PROC1_NMI_MASK_MSB _u(31)
|
||||
#define SYSCFG_PROC1_NMI_MASK_LSB _u(0)
|
||||
#define SYSCFG_PROC1_NMI_MASK_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SYSCFG_PROC_CONFIG
|
||||
// Description : Configuration for processors
|
||||
#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000008)
|
||||
#define SYSCFG_PROC_CONFIG_BITS _u(0xff000003)
|
||||
#define SYSCFG_PROC_CONFIG_RESET _u(0x10000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID
|
||||
// Description : Configure proc1 DAP instance ID.
|
||||
// Recommend that this is NOT changed until you require debug
|
||||
// access in multi-chip environment
|
||||
// WARNING: do not set to 15 as this is reserved for RescueDP
|
||||
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET _u(0x1)
|
||||
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS _u(0xf0000000)
|
||||
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB _u(31)
|
||||
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB _u(28)
|
||||
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID
|
||||
// Description : Configure proc0 DAP instance ID.
|
||||
// Recommend that this is NOT changed until you require debug
|
||||
// access in multi-chip environment
|
||||
// WARNING: do not set to 15 as this is reserved for RescueDP
|
||||
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET _u(0x0)
|
||||
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS _u(0x0f000000)
|
||||
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB _u(27)
|
||||
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB _u(24)
|
||||
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED
|
||||
// Description : Indication that proc1 has halted
|
||||
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0)
|
||||
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002)
|
||||
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1)
|
||||
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1)
|
||||
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED
|
||||
// Description : Indication that proc0 has halted
|
||||
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0)
|
||||
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001)
|
||||
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0)
|
||||
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0)
|
||||
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SYSCFG_PROC_IN_SYNC_BYPASS
|
||||
// Description : For each bit, if 1, bypass the input synchronizer between that
|
||||
// GPIO
|
||||
// and the GPIO input register in the SIO. The input synchronizers
|
||||
// should
|
||||
// generally be unbypassed, to avoid injecting metastabilities
|
||||
// into processors.
|
||||
// If you're feeling brave, you can bypass to save two cycles of
|
||||
// input
|
||||
// latency. This register applies to GPIO 0...29.
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x0000000c)
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0x3fffffff)
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000)
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB _u(29)
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB _u(0)
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI
|
||||
// Description : For each bit, if 1, bypass the input synchronizer between that
|
||||
// GPIO
|
||||
// and the GPIO input register in the SIO. The input synchronizers
|
||||
// should
|
||||
// generally be unbypassed, to avoid injecting metastabilities
|
||||
// into processors.
|
||||
// If you're feeling brave, you can bypass to save two cycles of
|
||||
// input
|
||||
// latency. This register applies to GPIO 30...35 (the QSPI IOs).
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000010)
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0x0000003f)
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000)
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB _u(5)
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB _u(0)
|
||||
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : SYSCFG_DBGFORCE
|
||||
// Description : Directly control the SWD debug port of either processor
|
||||
#define SYSCFG_DBGFORCE_OFFSET _u(0x00000014)
|
||||
#define SYSCFG_DBGFORCE_BITS _u(0x000000ff)
|
||||
#define SYSCFG_DBGFORCE_RESET _u(0x00000066)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_DBGFORCE_PROC1_ATTACH
|
||||
// Description : Attach processor 1 debug port to syscfg controls, and
|
||||
// disconnect it from external SWD pads.
|
||||
#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET _u(0x0)
|
||||
#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS _u(0x00000080)
|
||||
#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB _u(7)
|
||||
#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB _u(7)
|
||||
#define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_DBGFORCE_PROC1_SWCLK
|
||||
// Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET _u(0x1)
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS _u(0x00000040)
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB _u(6)
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB _u(6)
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_DBGFORCE_PROC1_SWDI
|
||||
// Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET _u(0x1)
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS _u(0x00000020)
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB _u(5)
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB _u(5)
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_DBGFORCE_PROC1_SWDO
|
||||
// Description : Observe the value of processor 1 SWDIO output.
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-"
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS _u(0x00000010)
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB _u(4)
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB _u(4)
|
||||
#define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_DBGFORCE_PROC0_ATTACH
|
||||
// Description : Attach processor 0 debug port to syscfg controls, and
|
||||
// disconnect it from external SWD pads.
|
||||
#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET _u(0x0)
|
||||
#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS _u(0x00000008)
|
||||
#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB _u(3)
|
||||
#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB _u(3)
|
||||
#define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_DBGFORCE_PROC0_SWCLK
|
||||
// Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET _u(0x1)
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS _u(0x00000004)
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB _u(2)
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB _u(2)
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_DBGFORCE_PROC0_SWDI
|
||||
// Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET _u(0x1)
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS _u(0x00000002)
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB _u(1)
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB _u(1)
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_DBGFORCE_PROC0_SWDO
|
||||
// Description : Observe the value of processor 0 SWDIO output.
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-"
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS _u(0x00000001)
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB _u(0)
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB _u(0)
|
||||
#define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SYSCFG_MEMPOWERDOWN
|
||||
// Description : Control power downs to memories. Set high to power down
|
||||
// memories.
|
||||
// Use with extreme caution
|
||||
#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000018)
|
||||
#define SYSCFG_MEMPOWERDOWN_BITS _u(0x000000ff)
|
||||
#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_MEMPOWERDOWN_ROM
|
||||
#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0)
|
||||
#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080)
|
||||
#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7)
|
||||
#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(7)
|
||||
#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_MEMPOWERDOWN_USB
|
||||
#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0)
|
||||
#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040)
|
||||
#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6)
|
||||
#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(6)
|
||||
#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_MEMPOWERDOWN_SRAM5
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_MEMPOWERDOWN_SRAM4
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_MEMPOWERDOWN_SRAM3
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_MEMPOWERDOWN_SRAM2
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_MEMPOWERDOWN_SRAM1
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSCFG_MEMPOWERDOWN_SRAM0
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0)
|
||||
#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_SYSCFG_H
|
||||
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : SYSINFO
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_SYSINFO_H
|
||||
#define _HARDWARE_REGS_SYSINFO_H
|
||||
// =============================================================================
|
||||
// Register : SYSINFO_CHIP_ID
|
||||
// Description : JEDEC JEP-106 compliant chip identifier.
|
||||
#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000)
|
||||
#define SYSINFO_CHIP_ID_BITS _u(0xffffffff)
|
||||
#define SYSINFO_CHIP_ID_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSINFO_CHIP_ID_REVISION
|
||||
#define SYSINFO_CHIP_ID_REVISION_RESET "-"
|
||||
#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000)
|
||||
#define SYSINFO_CHIP_ID_REVISION_MSB _u(31)
|
||||
#define SYSINFO_CHIP_ID_REVISION_LSB _u(28)
|
||||
#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSINFO_CHIP_ID_PART
|
||||
#define SYSINFO_CHIP_ID_PART_RESET "-"
|
||||
#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000)
|
||||
#define SYSINFO_CHIP_ID_PART_MSB _u(27)
|
||||
#define SYSINFO_CHIP_ID_PART_LSB _u(12)
|
||||
#define SYSINFO_CHIP_ID_PART_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSINFO_CHIP_ID_MANUFACTURER
|
||||
#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-"
|
||||
#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000fff)
|
||||
#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11)
|
||||
#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(0)
|
||||
#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SYSINFO_PLATFORM
|
||||
// Description : Platform register. Allows software to know what environment it
|
||||
// is running in.
|
||||
#define SYSINFO_PLATFORM_OFFSET _u(0x00000004)
|
||||
#define SYSINFO_PLATFORM_BITS _u(0x00000003)
|
||||
#define SYSINFO_PLATFORM_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSINFO_PLATFORM_ASIC
|
||||
#define SYSINFO_PLATFORM_ASIC_RESET _u(0x0)
|
||||
#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002)
|
||||
#define SYSINFO_PLATFORM_ASIC_MSB _u(1)
|
||||
#define SYSINFO_PLATFORM_ASIC_LSB _u(1)
|
||||
#define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : SYSINFO_PLATFORM_FPGA
|
||||
#define SYSINFO_PLATFORM_FPGA_RESET _u(0x0)
|
||||
#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001)
|
||||
#define SYSINFO_PLATFORM_FPGA_MSB _u(0)
|
||||
#define SYSINFO_PLATFORM_FPGA_LSB _u(0)
|
||||
#define SYSINFO_PLATFORM_FPGA_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : SYSINFO_GITREF_RP2040
|
||||
// Description : Git hash of the chip source. Used to identify chip version.
|
||||
#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000010)
|
||||
#define SYSINFO_GITREF_RP2040_BITS _u(0xffffffff)
|
||||
#define SYSINFO_GITREF_RP2040_RESET "-"
|
||||
#define SYSINFO_GITREF_RP2040_MSB _u(31)
|
||||
#define SYSINFO_GITREF_RP2040_LSB _u(0)
|
||||
#define SYSINFO_GITREF_RP2040_ACCESS "RO"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_SYSINFO_H
|
||||
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : TBMAN
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// Description : Testbench manager. Allows the programmer to know what
|
||||
// platform their software is running on.
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_TBMAN_H
|
||||
#define _HARDWARE_REGS_TBMAN_H
|
||||
// =============================================================================
|
||||
// Register : TBMAN_PLATFORM
|
||||
// Description : Indicates the type of platform in use
|
||||
#define TBMAN_PLATFORM_OFFSET _u(0x00000000)
|
||||
#define TBMAN_PLATFORM_BITS _u(0x00000003)
|
||||
#define TBMAN_PLATFORM_RESET _u(0x00000005)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TBMAN_PLATFORM_FPGA
|
||||
// Description : Indicates the platform is an FPGA
|
||||
#define TBMAN_PLATFORM_FPGA_RESET _u(0x0)
|
||||
#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002)
|
||||
#define TBMAN_PLATFORM_FPGA_MSB _u(1)
|
||||
#define TBMAN_PLATFORM_FPGA_LSB _u(1)
|
||||
#define TBMAN_PLATFORM_FPGA_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TBMAN_PLATFORM_ASIC
|
||||
// Description : Indicates the platform is an ASIC
|
||||
#define TBMAN_PLATFORM_ASIC_RESET _u(0x1)
|
||||
#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001)
|
||||
#define TBMAN_PLATFORM_ASIC_MSB _u(0)
|
||||
#define TBMAN_PLATFORM_ASIC_LSB _u(0)
|
||||
#define TBMAN_PLATFORM_ASIC_ACCESS "RO"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_TBMAN_H
|
||||
|
||||
|
|
@ -0,0 +1,319 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : TIMER
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// Description : Controls time and alarms
|
||||
// time is a 64 bit value indicating the time in usec since
|
||||
// power-on
|
||||
// timeh is the top 32 bits of time & timel is the bottom 32
|
||||
// bits
|
||||
// to change time write to timelw before timehw
|
||||
// to read time read from timelr before timehr
|
||||
// An alarm is set by setting alarm_enable and writing to the
|
||||
// corresponding alarm register
|
||||
// When an alarm is pending, the corresponding alarm_running
|
||||
// signal will be high
|
||||
// An alarm can be cancelled before it has finished by clearing
|
||||
// the alarm_enable
|
||||
// When an alarm fires, the corresponding alarm_irq is set and
|
||||
// alarm_running is cleared
|
||||
// To clear the interrupt write a 1 to the corresponding
|
||||
// alarm_irq
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_TIMER_H
|
||||
#define _HARDWARE_REGS_TIMER_H
|
||||
// =============================================================================
|
||||
// Register : TIMER_TIMEHW
|
||||
// Description : Write to bits 63:32 of time
|
||||
// always write timelw before timehw
|
||||
#define TIMER_TIMEHW_OFFSET _u(0x00000000)
|
||||
#define TIMER_TIMEHW_BITS _u(0xffffffff)
|
||||
#define TIMER_TIMEHW_RESET _u(0x00000000)
|
||||
#define TIMER_TIMEHW_MSB _u(31)
|
||||
#define TIMER_TIMEHW_LSB _u(0)
|
||||
#define TIMER_TIMEHW_ACCESS "WF"
|
||||
// =============================================================================
|
||||
// Register : TIMER_TIMELW
|
||||
// Description : Write to bits 31:0 of time
|
||||
// writes do not get copied to time until timehw is written
|
||||
#define TIMER_TIMELW_OFFSET _u(0x00000004)
|
||||
#define TIMER_TIMELW_BITS _u(0xffffffff)
|
||||
#define TIMER_TIMELW_RESET _u(0x00000000)
|
||||
#define TIMER_TIMELW_MSB _u(31)
|
||||
#define TIMER_TIMELW_LSB _u(0)
|
||||
#define TIMER_TIMELW_ACCESS "WF"
|
||||
// =============================================================================
|
||||
// Register : TIMER_TIMEHR
|
||||
// Description : Read from bits 63:32 of time
|
||||
// always read timelr before timehr
|
||||
#define TIMER_TIMEHR_OFFSET _u(0x00000008)
|
||||
#define TIMER_TIMEHR_BITS _u(0xffffffff)
|
||||
#define TIMER_TIMEHR_RESET _u(0x00000000)
|
||||
#define TIMER_TIMEHR_MSB _u(31)
|
||||
#define TIMER_TIMEHR_LSB _u(0)
|
||||
#define TIMER_TIMEHR_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : TIMER_TIMELR
|
||||
// Description : Read from bits 31:0 of time
|
||||
#define TIMER_TIMELR_OFFSET _u(0x0000000c)
|
||||
#define TIMER_TIMELR_BITS _u(0xffffffff)
|
||||
#define TIMER_TIMELR_RESET _u(0x00000000)
|
||||
#define TIMER_TIMELR_MSB _u(31)
|
||||
#define TIMER_TIMELR_LSB _u(0)
|
||||
#define TIMER_TIMELR_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : TIMER_ALARM0
|
||||
// Description : Arm alarm 0, and configure the time it will fire.
|
||||
// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
|
||||
// The alarm will disarm itself once it fires, and can
|
||||
// be disarmed early using the ARMED status register.
|
||||
#define TIMER_ALARM0_OFFSET _u(0x00000010)
|
||||
#define TIMER_ALARM0_BITS _u(0xffffffff)
|
||||
#define TIMER_ALARM0_RESET _u(0x00000000)
|
||||
#define TIMER_ALARM0_MSB _u(31)
|
||||
#define TIMER_ALARM0_LSB _u(0)
|
||||
#define TIMER_ALARM0_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TIMER_ALARM1
|
||||
// Description : Arm alarm 1, and configure the time it will fire.
|
||||
// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
|
||||
// The alarm will disarm itself once it fires, and can
|
||||
// be disarmed early using the ARMED status register.
|
||||
#define TIMER_ALARM1_OFFSET _u(0x00000014)
|
||||
#define TIMER_ALARM1_BITS _u(0xffffffff)
|
||||
#define TIMER_ALARM1_RESET _u(0x00000000)
|
||||
#define TIMER_ALARM1_MSB _u(31)
|
||||
#define TIMER_ALARM1_LSB _u(0)
|
||||
#define TIMER_ALARM1_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TIMER_ALARM2
|
||||
// Description : Arm alarm 2, and configure the time it will fire.
|
||||
// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
|
||||
// The alarm will disarm itself once it fires, and can
|
||||
// be disarmed early using the ARMED status register.
|
||||
#define TIMER_ALARM2_OFFSET _u(0x00000018)
|
||||
#define TIMER_ALARM2_BITS _u(0xffffffff)
|
||||
#define TIMER_ALARM2_RESET _u(0x00000000)
|
||||
#define TIMER_ALARM2_MSB _u(31)
|
||||
#define TIMER_ALARM2_LSB _u(0)
|
||||
#define TIMER_ALARM2_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TIMER_ALARM3
|
||||
// Description : Arm alarm 3, and configure the time it will fire.
|
||||
// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
|
||||
// The alarm will disarm itself once it fires, and can
|
||||
// be disarmed early using the ARMED status register.
|
||||
#define TIMER_ALARM3_OFFSET _u(0x0000001c)
|
||||
#define TIMER_ALARM3_BITS _u(0xffffffff)
|
||||
#define TIMER_ALARM3_RESET _u(0x00000000)
|
||||
#define TIMER_ALARM3_MSB _u(31)
|
||||
#define TIMER_ALARM3_LSB _u(0)
|
||||
#define TIMER_ALARM3_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TIMER_ARMED
|
||||
// Description : Indicates the armed/disarmed status of each alarm.
|
||||
// A write to the corresponding ALARMx register arms the alarm.
|
||||
// Alarms automatically disarm upon firing, but writing ones here
|
||||
// will disarm immediately without waiting to fire.
|
||||
#define TIMER_ARMED_OFFSET _u(0x00000020)
|
||||
#define TIMER_ARMED_BITS _u(0x0000000f)
|
||||
#define TIMER_ARMED_RESET _u(0x00000000)
|
||||
#define TIMER_ARMED_MSB _u(3)
|
||||
#define TIMER_ARMED_LSB _u(0)
|
||||
#define TIMER_ARMED_ACCESS "WC"
|
||||
// =============================================================================
|
||||
// Register : TIMER_TIMERAWH
|
||||
// Description : Raw read from bits 63:32 of time (no side effects)
|
||||
#define TIMER_TIMERAWH_OFFSET _u(0x00000024)
|
||||
#define TIMER_TIMERAWH_BITS _u(0xffffffff)
|
||||
#define TIMER_TIMERAWH_RESET _u(0x00000000)
|
||||
#define TIMER_TIMERAWH_MSB _u(31)
|
||||
#define TIMER_TIMERAWH_LSB _u(0)
|
||||
#define TIMER_TIMERAWH_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : TIMER_TIMERAWL
|
||||
// Description : Raw read from bits 31:0 of time (no side effects)
|
||||
#define TIMER_TIMERAWL_OFFSET _u(0x00000028)
|
||||
#define TIMER_TIMERAWL_BITS _u(0xffffffff)
|
||||
#define TIMER_TIMERAWL_RESET _u(0x00000000)
|
||||
#define TIMER_TIMERAWL_MSB _u(31)
|
||||
#define TIMER_TIMERAWL_LSB _u(0)
|
||||
#define TIMER_TIMERAWL_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : TIMER_DBGPAUSE
|
||||
// Description : Set bits high to enable pause when the corresponding debug
|
||||
// ports are active
|
||||
#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c)
|
||||
#define TIMER_DBGPAUSE_BITS _u(0x00000006)
|
||||
#define TIMER_DBGPAUSE_RESET _u(0x00000007)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_DBGPAUSE_DBG1
|
||||
// Description : Pause when processor 1 is in debug mode
|
||||
#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1)
|
||||
#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004)
|
||||
#define TIMER_DBGPAUSE_DBG1_MSB _u(2)
|
||||
#define TIMER_DBGPAUSE_DBG1_LSB _u(2)
|
||||
#define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_DBGPAUSE_DBG0
|
||||
// Description : Pause when processor 0 is in debug mode
|
||||
#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1)
|
||||
#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002)
|
||||
#define TIMER_DBGPAUSE_DBG0_MSB _u(1)
|
||||
#define TIMER_DBGPAUSE_DBG0_LSB _u(1)
|
||||
#define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TIMER_PAUSE
|
||||
// Description : Set high to pause the timer
|
||||
#define TIMER_PAUSE_OFFSET _u(0x00000030)
|
||||
#define TIMER_PAUSE_BITS _u(0x00000001)
|
||||
#define TIMER_PAUSE_RESET _u(0x00000000)
|
||||
#define TIMER_PAUSE_MSB _u(0)
|
||||
#define TIMER_PAUSE_LSB _u(0)
|
||||
#define TIMER_PAUSE_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TIMER_INTR
|
||||
// Description : Raw Interrupts
|
||||
#define TIMER_INTR_OFFSET _u(0x00000034)
|
||||
#define TIMER_INTR_BITS _u(0x0000000f)
|
||||
#define TIMER_INTR_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTR_ALARM_3
|
||||
#define TIMER_INTR_ALARM_3_RESET _u(0x0)
|
||||
#define TIMER_INTR_ALARM_3_BITS _u(0x00000008)
|
||||
#define TIMER_INTR_ALARM_3_MSB _u(3)
|
||||
#define TIMER_INTR_ALARM_3_LSB _u(3)
|
||||
#define TIMER_INTR_ALARM_3_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTR_ALARM_2
|
||||
#define TIMER_INTR_ALARM_2_RESET _u(0x0)
|
||||
#define TIMER_INTR_ALARM_2_BITS _u(0x00000004)
|
||||
#define TIMER_INTR_ALARM_2_MSB _u(2)
|
||||
#define TIMER_INTR_ALARM_2_LSB _u(2)
|
||||
#define TIMER_INTR_ALARM_2_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTR_ALARM_1
|
||||
#define TIMER_INTR_ALARM_1_RESET _u(0x0)
|
||||
#define TIMER_INTR_ALARM_1_BITS _u(0x00000002)
|
||||
#define TIMER_INTR_ALARM_1_MSB _u(1)
|
||||
#define TIMER_INTR_ALARM_1_LSB _u(1)
|
||||
#define TIMER_INTR_ALARM_1_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTR_ALARM_0
|
||||
#define TIMER_INTR_ALARM_0_RESET _u(0x0)
|
||||
#define TIMER_INTR_ALARM_0_BITS _u(0x00000001)
|
||||
#define TIMER_INTR_ALARM_0_MSB _u(0)
|
||||
#define TIMER_INTR_ALARM_0_LSB _u(0)
|
||||
#define TIMER_INTR_ALARM_0_ACCESS "WC"
|
||||
// =============================================================================
|
||||
// Register : TIMER_INTE
|
||||
// Description : Interrupt Enable
|
||||
#define TIMER_INTE_OFFSET _u(0x00000038)
|
||||
#define TIMER_INTE_BITS _u(0x0000000f)
|
||||
#define TIMER_INTE_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTE_ALARM_3
|
||||
#define TIMER_INTE_ALARM_3_RESET _u(0x0)
|
||||
#define TIMER_INTE_ALARM_3_BITS _u(0x00000008)
|
||||
#define TIMER_INTE_ALARM_3_MSB _u(3)
|
||||
#define TIMER_INTE_ALARM_3_LSB _u(3)
|
||||
#define TIMER_INTE_ALARM_3_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTE_ALARM_2
|
||||
#define TIMER_INTE_ALARM_2_RESET _u(0x0)
|
||||
#define TIMER_INTE_ALARM_2_BITS _u(0x00000004)
|
||||
#define TIMER_INTE_ALARM_2_MSB _u(2)
|
||||
#define TIMER_INTE_ALARM_2_LSB _u(2)
|
||||
#define TIMER_INTE_ALARM_2_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTE_ALARM_1
|
||||
#define TIMER_INTE_ALARM_1_RESET _u(0x0)
|
||||
#define TIMER_INTE_ALARM_1_BITS _u(0x00000002)
|
||||
#define TIMER_INTE_ALARM_1_MSB _u(1)
|
||||
#define TIMER_INTE_ALARM_1_LSB _u(1)
|
||||
#define TIMER_INTE_ALARM_1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTE_ALARM_0
|
||||
#define TIMER_INTE_ALARM_0_RESET _u(0x0)
|
||||
#define TIMER_INTE_ALARM_0_BITS _u(0x00000001)
|
||||
#define TIMER_INTE_ALARM_0_MSB _u(0)
|
||||
#define TIMER_INTE_ALARM_0_LSB _u(0)
|
||||
#define TIMER_INTE_ALARM_0_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TIMER_INTF
|
||||
// Description : Interrupt Force
|
||||
#define TIMER_INTF_OFFSET _u(0x0000003c)
|
||||
#define TIMER_INTF_BITS _u(0x0000000f)
|
||||
#define TIMER_INTF_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTF_ALARM_3
|
||||
#define TIMER_INTF_ALARM_3_RESET _u(0x0)
|
||||
#define TIMER_INTF_ALARM_3_BITS _u(0x00000008)
|
||||
#define TIMER_INTF_ALARM_3_MSB _u(3)
|
||||
#define TIMER_INTF_ALARM_3_LSB _u(3)
|
||||
#define TIMER_INTF_ALARM_3_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTF_ALARM_2
|
||||
#define TIMER_INTF_ALARM_2_RESET _u(0x0)
|
||||
#define TIMER_INTF_ALARM_2_BITS _u(0x00000004)
|
||||
#define TIMER_INTF_ALARM_2_MSB _u(2)
|
||||
#define TIMER_INTF_ALARM_2_LSB _u(2)
|
||||
#define TIMER_INTF_ALARM_2_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTF_ALARM_1
|
||||
#define TIMER_INTF_ALARM_1_RESET _u(0x0)
|
||||
#define TIMER_INTF_ALARM_1_BITS _u(0x00000002)
|
||||
#define TIMER_INTF_ALARM_1_MSB _u(1)
|
||||
#define TIMER_INTF_ALARM_1_LSB _u(1)
|
||||
#define TIMER_INTF_ALARM_1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTF_ALARM_0
|
||||
#define TIMER_INTF_ALARM_0_RESET _u(0x0)
|
||||
#define TIMER_INTF_ALARM_0_BITS _u(0x00000001)
|
||||
#define TIMER_INTF_ALARM_0_MSB _u(0)
|
||||
#define TIMER_INTF_ALARM_0_LSB _u(0)
|
||||
#define TIMER_INTF_ALARM_0_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TIMER_INTS
|
||||
// Description : Interrupt status after masking & forcing
|
||||
#define TIMER_INTS_OFFSET _u(0x00000040)
|
||||
#define TIMER_INTS_BITS _u(0x0000000f)
|
||||
#define TIMER_INTS_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTS_ALARM_3
|
||||
#define TIMER_INTS_ALARM_3_RESET _u(0x0)
|
||||
#define TIMER_INTS_ALARM_3_BITS _u(0x00000008)
|
||||
#define TIMER_INTS_ALARM_3_MSB _u(3)
|
||||
#define TIMER_INTS_ALARM_3_LSB _u(3)
|
||||
#define TIMER_INTS_ALARM_3_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTS_ALARM_2
|
||||
#define TIMER_INTS_ALARM_2_RESET _u(0x0)
|
||||
#define TIMER_INTS_ALARM_2_BITS _u(0x00000004)
|
||||
#define TIMER_INTS_ALARM_2_MSB _u(2)
|
||||
#define TIMER_INTS_ALARM_2_LSB _u(2)
|
||||
#define TIMER_INTS_ALARM_2_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTS_ALARM_1
|
||||
#define TIMER_INTS_ALARM_1_RESET _u(0x0)
|
||||
#define TIMER_INTS_ALARM_1_BITS _u(0x00000002)
|
||||
#define TIMER_INTS_ALARM_1_MSB _u(1)
|
||||
#define TIMER_INTS_ALARM_1_LSB _u(1)
|
||||
#define TIMER_INTS_ALARM_1_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : TIMER_INTS_ALARM_0
|
||||
#define TIMER_INTS_ALARM_0_RESET _u(0x0)
|
||||
#define TIMER_INTS_ALARM_0_BITS _u(0x00000001)
|
||||
#define TIMER_INTS_ALARM_0_MSB _u(0)
|
||||
#define TIMER_INTS_ALARM_0_LSB _u(0)
|
||||
#define TIMER_INTS_ALARM_0_ACCESS "RO"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_TIMER_H
|
||||
|
||||
1150
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h
Normal file
1150
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h
Normal file
File diff suppressed because it is too large
Load diff
3453
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h
Normal file
3453
lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,154 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : VREG_AND_CHIP_RESET
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// Description : control and status for on-chip voltage regulator and chip
|
||||
// level reset subsystem
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_VREG_AND_CHIP_RESET_H
|
||||
#define _HARDWARE_REGS_VREG_AND_CHIP_RESET_H
|
||||
// =============================================================================
|
||||
// Register : VREG_AND_CHIP_RESET_VREG
|
||||
// Description : Voltage regulator control and status
|
||||
#define VREG_AND_CHIP_RESET_VREG_OFFSET _u(0x00000000)
|
||||
#define VREG_AND_CHIP_RESET_VREG_BITS _u(0x000010f3)
|
||||
#define VREG_AND_CHIP_RESET_VREG_RESET _u(0x000000b1)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : VREG_AND_CHIP_RESET_VREG_ROK
|
||||
// Description : regulation status
|
||||
// 0=not in regulation, 1=in regulation
|
||||
#define VREG_AND_CHIP_RESET_VREG_ROK_RESET _u(0x0)
|
||||
#define VREG_AND_CHIP_RESET_VREG_ROK_BITS _u(0x00001000)
|
||||
#define VREG_AND_CHIP_RESET_VREG_ROK_MSB _u(12)
|
||||
#define VREG_AND_CHIP_RESET_VREG_ROK_LSB _u(12)
|
||||
#define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : VREG_AND_CHIP_RESET_VREG_VSEL
|
||||
// Description : output voltage select
|
||||
// 0000 to 0101 - 0.80V
|
||||
// 0110 - 0.85V
|
||||
// 0111 - 0.90V
|
||||
// 1000 - 0.95V
|
||||
// 1001 - 1.00V
|
||||
// 1010 - 1.05V
|
||||
// 1011 - 1.10V (default)
|
||||
// 1100 - 1.15V
|
||||
// 1101 - 1.20V
|
||||
// 1110 - 1.25V
|
||||
// 1111 - 1.30V
|
||||
#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET _u(0xb)
|
||||
#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS _u(0x000000f0)
|
||||
#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB _u(7)
|
||||
#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB _u(4)
|
||||
#define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : VREG_AND_CHIP_RESET_VREG_HIZ
|
||||
// Description : high impedance mode select
|
||||
// 0=not in high impedance mode, 1=in high impedance mode
|
||||
#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET _u(0x0)
|
||||
#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS _u(0x00000002)
|
||||
#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB _u(1)
|
||||
#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB _u(1)
|
||||
#define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : VREG_AND_CHIP_RESET_VREG_EN
|
||||
// Description : enable
|
||||
// 0=not enabled, 1=enabled
|
||||
#define VREG_AND_CHIP_RESET_VREG_EN_RESET _u(0x1)
|
||||
#define VREG_AND_CHIP_RESET_VREG_EN_BITS _u(0x00000001)
|
||||
#define VREG_AND_CHIP_RESET_VREG_EN_MSB _u(0)
|
||||
#define VREG_AND_CHIP_RESET_VREG_EN_LSB _u(0)
|
||||
#define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : VREG_AND_CHIP_RESET_BOD
|
||||
// Description : brown-out detection control
|
||||
#define VREG_AND_CHIP_RESET_BOD_OFFSET _u(0x00000004)
|
||||
#define VREG_AND_CHIP_RESET_BOD_BITS _u(0x000000f1)
|
||||
#define VREG_AND_CHIP_RESET_BOD_RESET _u(0x00000091)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : VREG_AND_CHIP_RESET_BOD_VSEL
|
||||
// Description : threshold select
|
||||
// 0000 - 0.473V
|
||||
// 0001 - 0.516V
|
||||
// 0010 - 0.559V
|
||||
// 0011 - 0.602V
|
||||
// 0100 - 0.645V
|
||||
// 0101 - 0.688V
|
||||
// 0110 - 0.731V
|
||||
// 0111 - 0.774V
|
||||
// 1000 - 0.817V
|
||||
// 1001 - 0.860V (default)
|
||||
// 1010 - 0.903V
|
||||
// 1011 - 0.946V
|
||||
// 1100 - 0.989V
|
||||
// 1101 - 1.032V
|
||||
// 1110 - 1.075V
|
||||
// 1111 - 1.118V
|
||||
#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET _u(0x9)
|
||||
#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS _u(0x000000f0)
|
||||
#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB _u(7)
|
||||
#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB _u(4)
|
||||
#define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : VREG_AND_CHIP_RESET_BOD_EN
|
||||
// Description : enable
|
||||
// 0=not enabled, 1=enabled
|
||||
#define VREG_AND_CHIP_RESET_BOD_EN_RESET _u(0x1)
|
||||
#define VREG_AND_CHIP_RESET_BOD_EN_BITS _u(0x00000001)
|
||||
#define VREG_AND_CHIP_RESET_BOD_EN_MSB _u(0)
|
||||
#define VREG_AND_CHIP_RESET_BOD_EN_LSB _u(0)
|
||||
#define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : VREG_AND_CHIP_RESET_CHIP_RESET
|
||||
// Description : Chip reset control and status
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _u(0x00000008)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS _u(0x01110100)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG
|
||||
// Description : This is set by psm_restart from the debugger.
|
||||
// Its purpose is to branch bootcode to a safe mode when the
|
||||
// debugger has issued a psm_restart in order to recover from a
|
||||
// boot lock-up.
|
||||
// In the safe mode the debugger can repair the boot code, clear
|
||||
// this flag then reboot the processor.
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET _u(0x0)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS _u(0x01000000)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB _u(24)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB _u(24)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART
|
||||
// Description : Last reset was from the debug port
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET _u(0x0)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS _u(0x00100000)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB _u(20)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB _u(20)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN
|
||||
// Description : Last reset was from the RUN pin
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET _u(0x0)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS _u(0x00010000)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB _u(16)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB _u(16)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR
|
||||
// Description : Last reset was from the power-on reset or brown-out detection
|
||||
// blocks
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET _u(0x0)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS _u(0x00000100)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB _u(8)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _u(8)
|
||||
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_VREG_AND_CHIP_RESET_H
|
||||
|
||||
|
|
@ -0,0 +1,226 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : WATCHDOG
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_WATCHDOG_H
|
||||
#define _HARDWARE_REGS_WATCHDOG_H
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_CTRL
|
||||
// Description : Watchdog control
|
||||
// The rst_wdsel register determines which subsystems are reset
|
||||
// when the watchdog is triggered.
|
||||
// The watchdog can be triggered in software.
|
||||
#define WATCHDOG_CTRL_OFFSET _u(0x00000000)
|
||||
#define WATCHDOG_CTRL_BITS _u(0xc7ffffff)
|
||||
#define WATCHDOG_CTRL_RESET _u(0x07000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_CTRL_TRIGGER
|
||||
// Description : Trigger a watchdog reset
|
||||
#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0)
|
||||
#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000)
|
||||
#define WATCHDOG_CTRL_TRIGGER_MSB _u(31)
|
||||
#define WATCHDOG_CTRL_TRIGGER_LSB _u(31)
|
||||
#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_CTRL_ENABLE
|
||||
// Description : When not enabled the watchdog timer is paused
|
||||
#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
|
||||
#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000)
|
||||
#define WATCHDOG_CTRL_ENABLE_MSB _u(30)
|
||||
#define WATCHDOG_CTRL_ENABLE_LSB _u(30)
|
||||
#define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_CTRL_PAUSE_DBG1
|
||||
// Description : Pause the watchdog timer when processor 1 is in debug mode
|
||||
#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1)
|
||||
#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000)
|
||||
#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26)
|
||||
#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26)
|
||||
#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_CTRL_PAUSE_DBG0
|
||||
// Description : Pause the watchdog timer when processor 0 is in debug mode
|
||||
#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1)
|
||||
#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000)
|
||||
#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25)
|
||||
#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25)
|
||||
#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_CTRL_PAUSE_JTAG
|
||||
// Description : Pause the watchdog timer when JTAG is accessing the bus fabric
|
||||
#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1)
|
||||
#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000)
|
||||
#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24)
|
||||
#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24)
|
||||
#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_CTRL_TIME
|
||||
// Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before
|
||||
// a watchdog reset will be triggered
|
||||
#define WATCHDOG_CTRL_TIME_RESET _u(0x000000)
|
||||
#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff)
|
||||
#define WATCHDOG_CTRL_TIME_MSB _u(23)
|
||||
#define WATCHDOG_CTRL_TIME_LSB _u(0)
|
||||
#define WATCHDOG_CTRL_TIME_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_LOAD
|
||||
// Description : Load the watchdog timer. The maximum setting is 0xffffff which
|
||||
// corresponds to 0xffffff / 2 ticks before triggering a watchdog
|
||||
// reset (see errata RP2040-E1).
|
||||
#define WATCHDOG_LOAD_OFFSET _u(0x00000004)
|
||||
#define WATCHDOG_LOAD_BITS _u(0x00ffffff)
|
||||
#define WATCHDOG_LOAD_RESET _u(0x00000000)
|
||||
#define WATCHDOG_LOAD_MSB _u(23)
|
||||
#define WATCHDOG_LOAD_LSB _u(0)
|
||||
#define WATCHDOG_LOAD_ACCESS "WF"
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_REASON
|
||||
// Description : Logs the reason for the last reset. Both bits are zero for the
|
||||
// case of a hardware reset.
|
||||
#define WATCHDOG_REASON_OFFSET _u(0x00000008)
|
||||
#define WATCHDOG_REASON_BITS _u(0x00000003)
|
||||
#define WATCHDOG_REASON_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_REASON_FORCE
|
||||
#define WATCHDOG_REASON_FORCE_RESET _u(0x0)
|
||||
#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002)
|
||||
#define WATCHDOG_REASON_FORCE_MSB _u(1)
|
||||
#define WATCHDOG_REASON_FORCE_LSB _u(1)
|
||||
#define WATCHDOG_REASON_FORCE_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_REASON_TIMER
|
||||
#define WATCHDOG_REASON_TIMER_RESET _u(0x0)
|
||||
#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001)
|
||||
#define WATCHDOG_REASON_TIMER_MSB _u(0)
|
||||
#define WATCHDOG_REASON_TIMER_LSB _u(0)
|
||||
#define WATCHDOG_REASON_TIMER_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_SCRATCH0
|
||||
// Description : Scratch register. Information persists through soft reset of
|
||||
// the chip.
|
||||
#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c)
|
||||
#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff)
|
||||
#define WATCHDOG_SCRATCH0_RESET _u(0x00000000)
|
||||
#define WATCHDOG_SCRATCH0_MSB _u(31)
|
||||
#define WATCHDOG_SCRATCH0_LSB _u(0)
|
||||
#define WATCHDOG_SCRATCH0_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_SCRATCH1
|
||||
// Description : Scratch register. Information persists through soft reset of
|
||||
// the chip.
|
||||
#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010)
|
||||
#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff)
|
||||
#define WATCHDOG_SCRATCH1_RESET _u(0x00000000)
|
||||
#define WATCHDOG_SCRATCH1_MSB _u(31)
|
||||
#define WATCHDOG_SCRATCH1_LSB _u(0)
|
||||
#define WATCHDOG_SCRATCH1_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_SCRATCH2
|
||||
// Description : Scratch register. Information persists through soft reset of
|
||||
// the chip.
|
||||
#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014)
|
||||
#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff)
|
||||
#define WATCHDOG_SCRATCH2_RESET _u(0x00000000)
|
||||
#define WATCHDOG_SCRATCH2_MSB _u(31)
|
||||
#define WATCHDOG_SCRATCH2_LSB _u(0)
|
||||
#define WATCHDOG_SCRATCH2_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_SCRATCH3
|
||||
// Description : Scratch register. Information persists through soft reset of
|
||||
// the chip.
|
||||
#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018)
|
||||
#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff)
|
||||
#define WATCHDOG_SCRATCH3_RESET _u(0x00000000)
|
||||
#define WATCHDOG_SCRATCH3_MSB _u(31)
|
||||
#define WATCHDOG_SCRATCH3_LSB _u(0)
|
||||
#define WATCHDOG_SCRATCH3_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_SCRATCH4
|
||||
// Description : Scratch register. Information persists through soft reset of
|
||||
// the chip.
|
||||
#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c)
|
||||
#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff)
|
||||
#define WATCHDOG_SCRATCH4_RESET _u(0x00000000)
|
||||
#define WATCHDOG_SCRATCH4_MSB _u(31)
|
||||
#define WATCHDOG_SCRATCH4_LSB _u(0)
|
||||
#define WATCHDOG_SCRATCH4_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_SCRATCH5
|
||||
// Description : Scratch register. Information persists through soft reset of
|
||||
// the chip.
|
||||
#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020)
|
||||
#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff)
|
||||
#define WATCHDOG_SCRATCH5_RESET _u(0x00000000)
|
||||
#define WATCHDOG_SCRATCH5_MSB _u(31)
|
||||
#define WATCHDOG_SCRATCH5_LSB _u(0)
|
||||
#define WATCHDOG_SCRATCH5_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_SCRATCH6
|
||||
// Description : Scratch register. Information persists through soft reset of
|
||||
// the chip.
|
||||
#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024)
|
||||
#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff)
|
||||
#define WATCHDOG_SCRATCH6_RESET _u(0x00000000)
|
||||
#define WATCHDOG_SCRATCH6_MSB _u(31)
|
||||
#define WATCHDOG_SCRATCH6_LSB _u(0)
|
||||
#define WATCHDOG_SCRATCH6_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_SCRATCH7
|
||||
// Description : Scratch register. Information persists through soft reset of
|
||||
// the chip.
|
||||
#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028)
|
||||
#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff)
|
||||
#define WATCHDOG_SCRATCH7_RESET _u(0x00000000)
|
||||
#define WATCHDOG_SCRATCH7_MSB _u(31)
|
||||
#define WATCHDOG_SCRATCH7_LSB _u(0)
|
||||
#define WATCHDOG_SCRATCH7_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : WATCHDOG_TICK
|
||||
// Description : Controls the tick generator
|
||||
#define WATCHDOG_TICK_OFFSET _u(0x0000002c)
|
||||
#define WATCHDOG_TICK_BITS _u(0x000fffff)
|
||||
#define WATCHDOG_TICK_RESET _u(0x00000200)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_TICK_COUNT
|
||||
// Description : Count down timer: the remaining number clk_tick cycles before
|
||||
// the next tick is generated.
|
||||
#define WATCHDOG_TICK_COUNT_RESET "-"
|
||||
#define WATCHDOG_TICK_COUNT_BITS _u(0x000ff800)
|
||||
#define WATCHDOG_TICK_COUNT_MSB _u(19)
|
||||
#define WATCHDOG_TICK_COUNT_LSB _u(11)
|
||||
#define WATCHDOG_TICK_COUNT_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_TICK_RUNNING
|
||||
// Description : Is the tick generator running?
|
||||
#define WATCHDOG_TICK_RUNNING_RESET "-"
|
||||
#define WATCHDOG_TICK_RUNNING_BITS _u(0x00000400)
|
||||
#define WATCHDOG_TICK_RUNNING_MSB _u(10)
|
||||
#define WATCHDOG_TICK_RUNNING_LSB _u(10)
|
||||
#define WATCHDOG_TICK_RUNNING_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_TICK_ENABLE
|
||||
// Description : start / stop tick generation
|
||||
#define WATCHDOG_TICK_ENABLE_RESET _u(0x1)
|
||||
#define WATCHDOG_TICK_ENABLE_BITS _u(0x00000200)
|
||||
#define WATCHDOG_TICK_ENABLE_MSB _u(9)
|
||||
#define WATCHDOG_TICK_ENABLE_LSB _u(9)
|
||||
#define WATCHDOG_TICK_ENABLE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : WATCHDOG_TICK_CYCLES
|
||||
// Description : Total number of clk_tick cycles before the next tick.
|
||||
#define WATCHDOG_TICK_CYCLES_RESET _u(0x000)
|
||||
#define WATCHDOG_TICK_CYCLES_BITS _u(0x000001ff)
|
||||
#define WATCHDOG_TICK_CYCLES_MSB _u(8)
|
||||
#define WATCHDOG_TICK_CYCLES_LSB _u(0)
|
||||
#define WATCHDOG_TICK_CYCLES_ACCESS "RW"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_WATCHDOG_H
|
||||
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : XIP
|
||||
// Version : 1
|
||||
// Bus type : ahb
|
||||
// Description : QSPI flash execute-in-place block
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_XIP_H
|
||||
#define _HARDWARE_REGS_XIP_H
|
||||
// =============================================================================
|
||||
// Register : XIP_CTRL
|
||||
// Description : Cache control
|
||||
#define XIP_CTRL_OFFSET _u(0x00000000)
|
||||
#define XIP_CTRL_BITS _u(0x0000000b)
|
||||
#define XIP_CTRL_RESET _u(0x00000003)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XIP_CTRL_POWER_DOWN
|
||||
// Description : When 1, the cache memories are powered down. They retain state,
|
||||
// but can not be accessed. This reduces static power dissipation.
|
||||
// Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache
|
||||
// cannot
|
||||
// be enabled when powered down.
|
||||
// Cache-as-SRAM accesses will produce a bus error response when
|
||||
// the cache is powered down.
|
||||
#define XIP_CTRL_POWER_DOWN_RESET _u(0x0)
|
||||
#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008)
|
||||
#define XIP_CTRL_POWER_DOWN_MSB _u(3)
|
||||
#define XIP_CTRL_POWER_DOWN_LSB _u(3)
|
||||
#define XIP_CTRL_POWER_DOWN_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XIP_CTRL_ERR_BADWRITE
|
||||
// Description : When 1, writes to any alias other than 0x0 (caching,
|
||||
// allocating)
|
||||
// will produce a bus fault. When 0, these writes are silently
|
||||
// ignored.
|
||||
// In either case, writes to the 0x0 alias will deallocate on tag
|
||||
// match,
|
||||
// as usual.
|
||||
#define XIP_CTRL_ERR_BADWRITE_RESET _u(0x1)
|
||||
#define XIP_CTRL_ERR_BADWRITE_BITS _u(0x00000002)
|
||||
#define XIP_CTRL_ERR_BADWRITE_MSB _u(1)
|
||||
#define XIP_CTRL_ERR_BADWRITE_LSB _u(1)
|
||||
#define XIP_CTRL_ERR_BADWRITE_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XIP_CTRL_EN
|
||||
// Description : When 1, enable the cache. When the cache is disabled, all XIP
|
||||
// accesses
|
||||
// will go straight to the flash, without querying the cache. When
|
||||
// enabled,
|
||||
// cacheable XIP accesses will query the cache, and the flash will
|
||||
// not be accessed if the tag matches and the valid bit is set.
|
||||
//
|
||||
// If the cache is enabled, cache-as-SRAM accesses have no effect
|
||||
// on the
|
||||
// cache data RAM, and will produce a bus error response.
|
||||
#define XIP_CTRL_EN_RESET _u(0x1)
|
||||
#define XIP_CTRL_EN_BITS _u(0x00000001)
|
||||
#define XIP_CTRL_EN_MSB _u(0)
|
||||
#define XIP_CTRL_EN_LSB _u(0)
|
||||
#define XIP_CTRL_EN_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : XIP_FLUSH
|
||||
// Description : Cache Flush control
|
||||
// Write 1 to flush the cache. This clears the tag memory, but
|
||||
// the data memory retains its contents. (This means cache-as-SRAM
|
||||
// contents is not affected by flush or reset.)
|
||||
// Reading will hold the bus (stall the processor) until the flush
|
||||
// completes. Alternatively STAT can be polled until completion.
|
||||
#define XIP_FLUSH_OFFSET _u(0x00000004)
|
||||
#define XIP_FLUSH_BITS _u(0x00000001)
|
||||
#define XIP_FLUSH_RESET _u(0x00000000)
|
||||
#define XIP_FLUSH_MSB _u(0)
|
||||
#define XIP_FLUSH_LSB _u(0)
|
||||
#define XIP_FLUSH_ACCESS "SC"
|
||||
// =============================================================================
|
||||
// Register : XIP_STAT
|
||||
// Description : Cache Status
|
||||
#define XIP_STAT_OFFSET _u(0x00000008)
|
||||
#define XIP_STAT_BITS _u(0x00000007)
|
||||
#define XIP_STAT_RESET _u(0x00000002)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XIP_STAT_FIFO_FULL
|
||||
// Description : When 1, indicates the XIP streaming FIFO is completely full.
|
||||
// The streaming FIFO is 2 entries deep, so the full and empty
|
||||
// flag allow its level to be ascertained.
|
||||
#define XIP_STAT_FIFO_FULL_RESET _u(0x0)
|
||||
#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004)
|
||||
#define XIP_STAT_FIFO_FULL_MSB _u(2)
|
||||
#define XIP_STAT_FIFO_FULL_LSB _u(2)
|
||||
#define XIP_STAT_FIFO_FULL_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XIP_STAT_FIFO_EMPTY
|
||||
// Description : When 1, indicates the XIP streaming FIFO is completely empty.
|
||||
#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1)
|
||||
#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002)
|
||||
#define XIP_STAT_FIFO_EMPTY_MSB _u(1)
|
||||
#define XIP_STAT_FIFO_EMPTY_LSB _u(1)
|
||||
#define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XIP_STAT_FLUSH_READY
|
||||
// Description : Reads as 0 while a cache flush is in progress, and 1 otherwise.
|
||||
// The cache is flushed whenever the XIP block is reset, and also
|
||||
// when requested via the FLUSH register.
|
||||
#define XIP_STAT_FLUSH_READY_RESET _u(0x0)
|
||||
#define XIP_STAT_FLUSH_READY_BITS _u(0x00000001)
|
||||
#define XIP_STAT_FLUSH_READY_MSB _u(0)
|
||||
#define XIP_STAT_FLUSH_READY_LSB _u(0)
|
||||
#define XIP_STAT_FLUSH_READY_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : XIP_CTR_HIT
|
||||
// Description : Cache Hit counter
|
||||
// A 32 bit saturating counter that increments upon each cache
|
||||
// hit,
|
||||
// i.e. when an XIP access is serviced directly from cached data.
|
||||
// Write any value to clear.
|
||||
#define XIP_CTR_HIT_OFFSET _u(0x0000000c)
|
||||
#define XIP_CTR_HIT_BITS _u(0xffffffff)
|
||||
#define XIP_CTR_HIT_RESET _u(0x00000000)
|
||||
#define XIP_CTR_HIT_MSB _u(31)
|
||||
#define XIP_CTR_HIT_LSB _u(0)
|
||||
#define XIP_CTR_HIT_ACCESS "WC"
|
||||
// =============================================================================
|
||||
// Register : XIP_CTR_ACC
|
||||
// Description : Cache Access counter
|
||||
// A 32 bit saturating counter that increments upon each XIP
|
||||
// access,
|
||||
// whether the cache is hit or not. This includes noncacheable
|
||||
// accesses.
|
||||
// Write any value to clear.
|
||||
#define XIP_CTR_ACC_OFFSET _u(0x00000010)
|
||||
#define XIP_CTR_ACC_BITS _u(0xffffffff)
|
||||
#define XIP_CTR_ACC_RESET _u(0x00000000)
|
||||
#define XIP_CTR_ACC_MSB _u(31)
|
||||
#define XIP_CTR_ACC_LSB _u(0)
|
||||
#define XIP_CTR_ACC_ACCESS "WC"
|
||||
// =============================================================================
|
||||
// Register : XIP_STREAM_ADDR
|
||||
// Description : FIFO stream address
|
||||
// The address of the next word to be streamed from flash to the
|
||||
// streaming FIFO.
|
||||
// Increments automatically after each flash access.
|
||||
// Write the initial access address here before starting a
|
||||
// streaming read.
|
||||
#define XIP_STREAM_ADDR_OFFSET _u(0x00000014)
|
||||
#define XIP_STREAM_ADDR_BITS _u(0xfffffffc)
|
||||
#define XIP_STREAM_ADDR_RESET _u(0x00000000)
|
||||
#define XIP_STREAM_ADDR_MSB _u(31)
|
||||
#define XIP_STREAM_ADDR_LSB _u(2)
|
||||
#define XIP_STREAM_ADDR_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : XIP_STREAM_CTR
|
||||
// Description : FIFO stream control
|
||||
// Write a nonzero value to start a streaming read. This will then
|
||||
// progress in the background, using flash idle cycles to transfer
|
||||
// a linear data block from flash to the streaming FIFO.
|
||||
// Decrements automatically (1 at a time) as the stream
|
||||
// progresses, and halts on reaching 0.
|
||||
// Write 0 to halt an in-progress stream, and discard any in-
|
||||
// flight
|
||||
// read, so that a new stream can immediately be started (after
|
||||
// draining the FIFO and reinitialising STREAM_ADDR)
|
||||
#define XIP_STREAM_CTR_OFFSET _u(0x00000018)
|
||||
#define XIP_STREAM_CTR_BITS _u(0x003fffff)
|
||||
#define XIP_STREAM_CTR_RESET _u(0x00000000)
|
||||
#define XIP_STREAM_CTR_MSB _u(21)
|
||||
#define XIP_STREAM_CTR_LSB _u(0)
|
||||
#define XIP_STREAM_CTR_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : XIP_STREAM_FIFO
|
||||
// Description : FIFO stream data
|
||||
// Streamed data is buffered here, for retrieval by the system
|
||||
// DMA.
|
||||
// This FIFO can also be accessed via the XIP_AUX slave, to avoid
|
||||
// exposing
|
||||
// the DMA to bus stalls caused by other XIP traffic.
|
||||
#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c)
|
||||
#define XIP_STREAM_FIFO_BITS _u(0xffffffff)
|
||||
#define XIP_STREAM_FIFO_RESET _u(0x00000000)
|
||||
#define XIP_STREAM_FIFO_MSB _u(31)
|
||||
#define XIP_STREAM_FIFO_LSB _u(0)
|
||||
#define XIP_STREAM_FIFO_ACCESS "RF"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_XIP_H
|
||||
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
// =============================================================================
|
||||
// Register block : XOSC
|
||||
// Version : 1
|
||||
// Bus type : apb
|
||||
// Description : Controls the crystal oscillator
|
||||
// =============================================================================
|
||||
#ifndef _HARDWARE_REGS_XOSC_H
|
||||
#define _HARDWARE_REGS_XOSC_H
|
||||
// =============================================================================
|
||||
// Register : XOSC_CTRL
|
||||
// Description : Crystal Oscillator Control
|
||||
#define XOSC_CTRL_OFFSET _u(0x00000000)
|
||||
#define XOSC_CTRL_BITS _u(0x00ffffff)
|
||||
#define XOSC_CTRL_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XOSC_CTRL_ENABLE
|
||||
// Description : On power-up this field is initialised to DISABLE and the chip
|
||||
// runs from the ROSC.
|
||||
// If the chip has subsequently been programmed to run from the
|
||||
// XOSC then DISABLE may lock-up the chip. If this is a concern
|
||||
// then run the clk_ref from the ROSC and enable the clk_sys RESUS
|
||||
// feature.
|
||||
// The 12-bit code is intended to give some protection against
|
||||
// accidental writes. An invalid setting will enable the
|
||||
// oscillator.
|
||||
// 0xd1e -> DISABLE
|
||||
// 0xfab -> ENABLE
|
||||
#define XOSC_CTRL_ENABLE_RESET "-"
|
||||
#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000)
|
||||
#define XOSC_CTRL_ENABLE_MSB _u(23)
|
||||
#define XOSC_CTRL_ENABLE_LSB _u(12)
|
||||
#define XOSC_CTRL_ENABLE_ACCESS "RW"
|
||||
#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
|
||||
#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XOSC_CTRL_FREQ_RANGE
|
||||
// Description : Frequency range. An invalid setting will retain the previous
|
||||
// value. The actual value being used can be read from
|
||||
// STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed.
|
||||
// 0xaa0 -> 1_15MHZ
|
||||
// 0xaa1 -> RESERVED_1
|
||||
// 0xaa2 -> RESERVED_2
|
||||
// 0xaa3 -> RESERVED_3
|
||||
#define XOSC_CTRL_FREQ_RANGE_RESET "-"
|
||||
#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
|
||||
#define XOSC_CTRL_FREQ_RANGE_MSB _u(11)
|
||||
#define XOSC_CTRL_FREQ_RANGE_LSB _u(0)
|
||||
#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW"
|
||||
#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0)
|
||||
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1)
|
||||
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2)
|
||||
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3)
|
||||
// =============================================================================
|
||||
// Register : XOSC_STATUS
|
||||
// Description : Crystal Oscillator Status
|
||||
#define XOSC_STATUS_OFFSET _u(0x00000004)
|
||||
#define XOSC_STATUS_BITS _u(0x81001003)
|
||||
#define XOSC_STATUS_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XOSC_STATUS_STABLE
|
||||
// Description : Oscillator is running and stable
|
||||
#define XOSC_STATUS_STABLE_RESET _u(0x0)
|
||||
#define XOSC_STATUS_STABLE_BITS _u(0x80000000)
|
||||
#define XOSC_STATUS_STABLE_MSB _u(31)
|
||||
#define XOSC_STATUS_STABLE_LSB _u(31)
|
||||
#define XOSC_STATUS_STABLE_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XOSC_STATUS_BADWRITE
|
||||
// Description : An invalid value has been written to CTRL_ENABLE or
|
||||
// CTRL_FREQ_RANGE or DORMANT
|
||||
#define XOSC_STATUS_BADWRITE_RESET _u(0x0)
|
||||
#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000)
|
||||
#define XOSC_STATUS_BADWRITE_MSB _u(24)
|
||||
#define XOSC_STATUS_BADWRITE_LSB _u(24)
|
||||
#define XOSC_STATUS_BADWRITE_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XOSC_STATUS_ENABLED
|
||||
// Description : Oscillator is enabled but not necessarily running and stable,
|
||||
// resets to 0
|
||||
#define XOSC_STATUS_ENABLED_RESET "-"
|
||||
#define XOSC_STATUS_ENABLED_BITS _u(0x00001000)
|
||||
#define XOSC_STATUS_ENABLED_MSB _u(12)
|
||||
#define XOSC_STATUS_ENABLED_LSB _u(12)
|
||||
#define XOSC_STATUS_ENABLED_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XOSC_STATUS_FREQ_RANGE
|
||||
// Description : The current frequency range setting, always reads 0
|
||||
// 0x0 -> 1_15MHZ
|
||||
// 0x1 -> RESERVED_1
|
||||
// 0x2 -> RESERVED_2
|
||||
// 0x3 -> RESERVED_3
|
||||
#define XOSC_STATUS_FREQ_RANGE_RESET "-"
|
||||
#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003)
|
||||
#define XOSC_STATUS_FREQ_RANGE_MSB _u(1)
|
||||
#define XOSC_STATUS_FREQ_RANGE_LSB _u(0)
|
||||
#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO"
|
||||
#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0)
|
||||
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1)
|
||||
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2)
|
||||
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3)
|
||||
// =============================================================================
|
||||
// Register : XOSC_DORMANT
|
||||
// Description : Crystal Oscillator pause control
|
||||
// This is used to save power by pausing the XOSC
|
||||
// On power-up this field is initialised to WAKE
|
||||
// An invalid write will also select WAKE
|
||||
// Warning: stop the PLLs before selecting dormant mode
|
||||
// Warning: setup the irq before selecting dormant mode
|
||||
// 0x636f6d61 -> dormant
|
||||
// 0x77616b65 -> WAKE
|
||||
#define XOSC_DORMANT_OFFSET _u(0x00000008)
|
||||
#define XOSC_DORMANT_BITS _u(0xffffffff)
|
||||
#define XOSC_DORMANT_RESET "-"
|
||||
#define XOSC_DORMANT_MSB _u(31)
|
||||
#define XOSC_DORMANT_LSB _u(0)
|
||||
#define XOSC_DORMANT_ACCESS "RW"
|
||||
#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
|
||||
#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65)
|
||||
// =============================================================================
|
||||
// Register : XOSC_STARTUP
|
||||
// Description : Controls the startup delay
|
||||
#define XOSC_STARTUP_OFFSET _u(0x0000000c)
|
||||
#define XOSC_STARTUP_BITS _u(0x00103fff)
|
||||
#define XOSC_STARTUP_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XOSC_STARTUP_X4
|
||||
// Description : Multiplies the startup_delay by 4. This is of little value to
|
||||
// the user given that the delay can be programmed directly.
|
||||
#define XOSC_STARTUP_X4_RESET "-"
|
||||
#define XOSC_STARTUP_X4_BITS _u(0x00100000)
|
||||
#define XOSC_STARTUP_X4_MSB _u(20)
|
||||
#define XOSC_STARTUP_X4_LSB _u(20)
|
||||
#define XOSC_STARTUP_X4_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : XOSC_STARTUP_DELAY
|
||||
// Description : in multiples of 256*xtal_period. The reset value of 0xc4
|
||||
// corresponds to approx 50 000 cycles.
|
||||
#define XOSC_STARTUP_DELAY_RESET "-"
|
||||
#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff)
|
||||
#define XOSC_STARTUP_DELAY_MSB _u(13)
|
||||
#define XOSC_STARTUP_DELAY_LSB _u(0)
|
||||
#define XOSC_STARTUP_DELAY_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : XOSC_COUNT
|
||||
// Description : A down counter running at the xosc frequency which counts to
|
||||
// zero and stops.
|
||||
// To start the counter write a non-zero value.
|
||||
// Can be used for short software pauses when setting up time
|
||||
// sensitive hardware.
|
||||
#define XOSC_COUNT_OFFSET _u(0x0000001c)
|
||||
#define XOSC_COUNT_BITS _u(0x000000ff)
|
||||
#define XOSC_COUNT_RESET _u(0x00000000)
|
||||
#define XOSC_COUNT_MSB _u(7)
|
||||
#define XOSC_COUNT_LSB _u(0)
|
||||
#define XOSC_COUNT_ACCESS "RW"
|
||||
// =============================================================================
|
||||
#endif // _HARDWARE_REGS_XOSC_H
|
||||
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_ADC_H
|
||||
#define _HARDWARE_STRUCTS_ADC_H
|
||||
|
||||
/**
|
||||
* \file rp2040/adc.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/adc.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(ADC_CS_OFFSET) // ADC_CS
|
||||
// ADC Control and Status
|
||||
// 0x001f0000 [20:16] RROBIN (0x00) Round-robin sampling
|
||||
// 0x00007000 [14:12] AINSEL (0x0) Select analog mux input
|
||||
// 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error
|
||||
// 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;...
|
||||
// 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion
|
||||
// 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1
|
||||
// 0x00000004 [2] START_ONCE (0) Start a single conversion
|
||||
// 0x00000002 [1] TS_EN (0) Power on temperature sensor
|
||||
// 0x00000001 [0] EN (0) Power on ADC and enable its clock
|
||||
io_rw_32 cs;
|
||||
|
||||
_REG_(ADC_RESULT_OFFSET) // ADC_RESULT
|
||||
// Result of most recent ADC conversion
|
||||
// 0x00000fff [11:0] RESULT (0x000)
|
||||
io_ro_32 result;
|
||||
|
||||
_REG_(ADC_FCS_OFFSET) // ADC_FCS
|
||||
// FIFO control and status
|
||||
// 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold
|
||||
// 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO
|
||||
// 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed
|
||||
// 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed
|
||||
// 0x00000200 [9] FULL (0)
|
||||
// 0x00000100 [8] EMPTY (0)
|
||||
// 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data
|
||||
// 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside...
|
||||
// 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size
|
||||
// 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion
|
||||
io_rw_32 fcs;
|
||||
|
||||
_REG_(ADC_FIFO_OFFSET) // ADC_FIFO
|
||||
// Conversion result FIFO
|
||||
// 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error
|
||||
// 0x00000fff [11:0] VAL (-)
|
||||
io_ro_32 fifo;
|
||||
|
||||
_REG_(ADC_DIV_OFFSET) // ADC_DIV
|
||||
// Clock divider
|
||||
// 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor
|
||||
// 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor
|
||||
io_rw_32 div;
|
||||
|
||||
_REG_(ADC_INTR_OFFSET) // ADC_INTR
|
||||
// Raw Interrupts
|
||||
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
|
||||
io_ro_32 intr;
|
||||
|
||||
_REG_(ADC_INTE_OFFSET) // ADC_INTE
|
||||
// Interrupt Enable
|
||||
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
|
||||
io_rw_32 inte;
|
||||
|
||||
_REG_(ADC_INTF_OFFSET) // ADC_INTF
|
||||
// Interrupt Force
|
||||
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
|
||||
io_rw_32 intf;
|
||||
|
||||
_REG_(ADC_INTS_OFFSET) // ADC_INTS
|
||||
// Interrupt status after masking & forcing
|
||||
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
|
||||
io_ro_32 ints;
|
||||
} adc_hw_t;
|
||||
|
||||
#define adc_hw ((adc_hw_t *)ADC_BASE)
|
||||
static_assert(sizeof (adc_hw_t) == 0x0024, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_ADC_H
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
// Support old header for compatibility (and if included, support old variable name)
|
||||
#include "hardware/structs/busctrl.h"
|
||||
#define bus_ctrl_hw busctrl_hw
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_BUSCTRL_H
|
||||
#define _HARDWARE_STRUCTS_BUSCTRL_H
|
||||
|
||||
/**
|
||||
* \file rp2040/busctrl.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/busctrl.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
/** \brief Bus fabric performance counters on RP2040 (used as typedef \ref bus_ctrl_perf_counter_t)
|
||||
* \ingroup hardware_busctrl
|
||||
*/
|
||||
typedef enum bus_ctrl_perf_counter_rp2040 {
|
||||
arbiter_rom_perf_event_access = 19,
|
||||
arbiter_rom_perf_event_access_contested = 18,
|
||||
arbiter_xip_main_perf_event_access = 17,
|
||||
arbiter_xip_main_perf_event_access_contested = 16,
|
||||
arbiter_sram0_perf_event_access = 15,
|
||||
arbiter_sram0_perf_event_access_contested = 14,
|
||||
arbiter_sram1_perf_event_access = 13,
|
||||
arbiter_sram1_perf_event_access_contested = 12,
|
||||
arbiter_sram2_perf_event_access = 11,
|
||||
arbiter_sram2_perf_event_access_contested = 10,
|
||||
arbiter_sram3_perf_event_access = 9,
|
||||
arbiter_sram3_perf_event_access_contested = 8,
|
||||
arbiter_sram4_perf_event_access = 7,
|
||||
arbiter_sram4_perf_event_access_contested = 6,
|
||||
arbiter_sram5_perf_event_access = 5,
|
||||
arbiter_sram5_perf_event_access_contested = 4,
|
||||
arbiter_fastperi_perf_event_access = 3,
|
||||
arbiter_fastperi_perf_event_access_contested = 2,
|
||||
arbiter_apb_perf_event_access = 1,
|
||||
arbiter_apb_perf_event_access_contested = 0
|
||||
} bus_ctrl_perf_counter_t;
|
||||
|
||||
typedef struct {
|
||||
_REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0
|
||||
// Bus fabric performance counter 0
|
||||
// 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 +
|
||||
io_rw_32 value;
|
||||
|
||||
_REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0
|
||||
// Bus fabric performance event select for PERFCTR0
|
||||
// 0x0000001f [4:0] PERFSEL0 (0x1f) Select an event for PERFCTR0
|
||||
io_rw_32 sel;
|
||||
} bus_ctrl_perf_hw_t;
|
||||
|
||||
typedef struct {
|
||||
_REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY
|
||||
// Set the priority of each master for bus arbitration
|
||||
// 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority
|
||||
// 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority
|
||||
// 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority
|
||||
// 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority
|
||||
io_rw_32 priority;
|
||||
|
||||
_REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK
|
||||
// Bus priority acknowledge
|
||||
// 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new...
|
||||
io_ro_32 priority_ack;
|
||||
|
||||
bus_ctrl_perf_hw_t counter[4];
|
||||
} busctrl_hw_t;
|
||||
|
||||
#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE)
|
||||
static_assert(sizeof (busctrl_hw_t) == 0x0028, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_BUSCTRL_H
|
||||
|
||||
|
|
@ -0,0 +1,504 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_CLOCKS_H
|
||||
#define _HARDWARE_STRUCTS_CLOCKS_H
|
||||
|
||||
/**
|
||||
* \file rp2040/clocks.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/clocks.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
/** \brief Clock numbers on RP2040 (used as typedef \ref clock_num_t)
|
||||
* \ingroup hardware_clocks
|
||||
*/
|
||||
/// \tag::clkenum[]
|
||||
typedef enum clock_num_rp2040 {
|
||||
clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source
|
||||
clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source
|
||||
clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source
|
||||
clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source
|
||||
clk_ref = 4, ///< Select CLK_REF as clock source
|
||||
clk_sys = 5, ///< Select CLK_SYS as clock source
|
||||
clk_peri = 6, ///< Select CLK_PERI as clock source
|
||||
clk_usb = 7, ///< Select CLK_USB as clock source
|
||||
clk_adc = 8, ///< Select CLK_ADC as clock source
|
||||
clk_rtc = 9, ///< Select CLK_RTC as clock source
|
||||
CLK_COUNT
|
||||
} clock_num_t;
|
||||
/// \end::clkenum[]
|
||||
|
||||
/** \brief Clock destination numbers on RP2040 (used as typedef \ref clock_dest_num_t)
|
||||
* \ingroup hardware_clocks
|
||||
*/
|
||||
typedef enum clock_dest_num_rp2040 {
|
||||
CLK_DEST_SYS_CLOCKS = 0, ///< Select SYS_CLOCKS as clock destination
|
||||
CLK_DEST_ADC_ADC = 1, ///< Select ADC_ADC as clock destination
|
||||
CLK_DEST_SYS_ADC = 2, ///< Select SYS_ADC as clock destination
|
||||
CLK_DEST_SYS_BUSCTRL = 3, ///< Select SYS_BUSCTRL as clock destination
|
||||
CLK_DEST_SYS_BUSFABRIC = 4, ///< Select SYS_BUSFABRIC as clock destination
|
||||
CLK_DEST_SYS_DMA = 5, ///< Select SYS_DMA as clock destination
|
||||
CLK_DEST_SYS_I2C0 = 6, ///< Select SYS_I2C0 as clock destination
|
||||
CLK_DEST_SYS_I2C1 = 7, ///< Select SYS_I2C1 as clock destination
|
||||
CLK_DEST_SYS_IO = 8, ///< Select SYS_IO as clock destination
|
||||
CLK_DEST_SYS_JTAG = 9, ///< Select SYS_JTAG as clock destination
|
||||
CLK_DEST_SYS_VREG_AND_CHIP_RESET = 10, ///< Select SYS_VREG_AND_CHIP_RESET as clock destination
|
||||
CLK_DEST_SYS_PADS = 11, ///< Select SYS_PADS as clock destination
|
||||
CLK_DEST_SYS_PIO0 = 12, ///< Select SYS_PIO0 as clock destination
|
||||
CLK_DEST_SYS_PIO1 = 13, ///< Select SYS_PIO1 as clock destination
|
||||
CLK_DEST_SYS_PLL_SYS = 14, ///< Select SYS_PLL_SYS as clock destination
|
||||
CLK_DEST_SYS_PLL_USB = 15, ///< Select SYS_PLL_USB as clock destination
|
||||
CLK_DEST_SYS_PSM = 16, ///< Select SYS_PSM as clock destination
|
||||
CLK_DEST_SYS_PWM = 17, ///< Select SYS_PWM as clock destination
|
||||
CLK_DEST_SYS_RESETS = 18, ///< Select SYS_RESETS as clock destination
|
||||
CLK_DEST_SYS_ROM = 19, ///< Select SYS_ROM as clock destination
|
||||
CLK_DEST_SYS_ROSC = 20, ///< Select SYS_ROSC as clock destination
|
||||
CLK_DEST_RTC_RTC = 21, ///< Select RTC_RTC as clock destination
|
||||
CLK_DEST_SYS_RTC = 22, ///< Select SYS_RTC as clock destination
|
||||
CLK_DEST_SYS_SIO = 23, ///< Select SYS_SIO as clock destination
|
||||
CLK_DEST_PERI_SPI0 = 24, ///< Select PERI_SPI0 as clock destination
|
||||
CLK_DEST_SYS_SPI0 = 25, ///< Select SYS_SPI0 as clock destination
|
||||
CLK_DEST_PERI_SPI1 = 26, ///< Select PERI_SPI1 as clock destination
|
||||
CLK_DEST_SYS_SPI1 = 27, ///< Select SYS_SPI1 as clock destination
|
||||
CLK_DEST_SYS_SRAM0 = 28, ///< Select SYS_SRAM0 as clock destination
|
||||
CLK_DEST_SYS_SRAM1 = 29, ///< Select SYS_SRAM1 as clock destination
|
||||
CLK_DEST_SYS_SRAM2 = 30, ///< Select SYS_SRAM2 as clock destination
|
||||
CLK_DEST_SYS_SRAM3 = 31, ///< Select SYS_SRAM3 as clock destination
|
||||
CLK_DEST_SYS_SRAM4 = 32, ///< Select SYS_SRAM4 as clock destination
|
||||
CLK_DEST_SYS_SRAM5 = 33, ///< Select SYS_SRAM5 as clock destination
|
||||
CLK_DEST_SYS_SYSCFG = 34, ///< Select SYS_SYSCFG as clock destination
|
||||
CLK_DEST_SYS_SYSINFO = 35, ///< Select SYS_SYSINFO as clock destination
|
||||
CLK_DEST_SYS_TBMAN = 36, ///< Select SYS_TBMAN as clock destination
|
||||
CLK_DEST_SYS_TIMER = 37, ///< Select SYS_TIMER as clock destination
|
||||
CLK_DEST_PERI_UART0 = 38, ///< Select PERI_UART0 as clock destination
|
||||
CLK_DEST_SYS_UART0 = 39, ///< Select SYS_UART0 as clock destination
|
||||
CLK_DEST_PERI_UART1 = 40, ///< Select PERI_UART1 as clock destination
|
||||
CLK_DEST_SYS_UART1 = 41, ///< Select SYS_UART1 as clock destination
|
||||
CLK_DEST_SYS_USBCTRL = 42, ///< Select SYS_USBCTRL as clock destination
|
||||
CLK_DEST_USB_USBCTRL = 43, ///< Select USB_USBCTRL as clock destination
|
||||
CLK_DEST_SYS_WATCHDOG = 44, ///< Select SYS_WATCHDOG as clock destination
|
||||
CLK_DEST_SYS_XIP = 45, ///< Select SYS_XIP as clock destination
|
||||
CLK_DEST_SYS_XOSC = 46, ///< Select SYS_XOSC as clock destination
|
||||
NUM_CLOCK_DESTINATIONS
|
||||
} clock_dest_num_t;
|
||||
|
||||
/// \tag::clock_hw[]
|
||||
typedef struct {
|
||||
_REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
|
||||
// Clock control, can be changed on-the-fly (except for auxsrc)
|
||||
// 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by...
|
||||
// 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the...
|
||||
// 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors
|
||||
// 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly
|
||||
// 0x00000400 [10] KILL (0) Asynchronously kills the clock generator
|
||||
// 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching
|
||||
io_rw_32 ctrl;
|
||||
|
||||
_REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
|
||||
// Clock divisor, can be changed on-the-fly
|
||||
// 0xffffff00 [31:8] INT (0x000001) Integer component of the divisor, 0 -> divide by 2^16
|
||||
// 0x000000ff [7:0] FRAC (0x00) Fractional component of the divisor
|
||||
io_rw_32 div;
|
||||
|
||||
_REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
|
||||
// Indicates which SRC is currently selected by the glitchless mux (one-hot)
|
||||
// 0xffffffff [31:0] CLK_GPOUT0_SELECTED (0x00000001) This slice does not have a glitchless mux (only the...
|
||||
io_ro_32 selected;
|
||||
} clock_hw_t;
|
||||
/// \end::clock_hw[]
|
||||
|
||||
typedef struct {
|
||||
_REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
|
||||
// 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it...
|
||||
// 0x00001000 [12] FRCE (0) Force a resus, for test purposes only
|
||||
// 0x00000100 [8] ENABLE (0) Enable resus
|
||||
// 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles +
|
||||
io_rw_32 ctrl;
|
||||
|
||||
_REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
|
||||
// 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send...
|
||||
io_ro_32 status;
|
||||
} clock_resus_hw_t;
|
||||
|
||||
typedef struct {
|
||||
_REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
|
||||
// Reference clock frequency in kHz
|
||||
// 0x000fffff [19:0] FC0_REF_KHZ (0x00000)
|
||||
io_rw_32 ref_khz;
|
||||
|
||||
_REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
|
||||
// Minimum pass frequency in kHz
|
||||
// 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000)
|
||||
io_rw_32 min_khz;
|
||||
|
||||
_REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
|
||||
// Maximum pass frequency in kHz
|
||||
// 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff)
|
||||
io_rw_32 max_khz;
|
||||
|
||||
_REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
|
||||
// Delays the start of frequency counting to allow the mux to settle +
|
||||
// 0x00000007 [2:0] FC0_DELAY (0x1)
|
||||
io_rw_32 delay;
|
||||
|
||||
_REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
|
||||
// The test interval is 0
|
||||
// 0x0000000f [3:0] FC0_INTERVAL (0x8)
|
||||
io_rw_32 interval;
|
||||
|
||||
_REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
|
||||
// Clock sent to frequency counter, set to 0 when not required +
|
||||
// 0x000000ff [7:0] FC0_SRC (0x00)
|
||||
io_rw_32 src;
|
||||
|
||||
_REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
|
||||
// Frequency counter status
|
||||
// 0x10000000 [28] DIED (0) Test clock stopped during test
|
||||
// 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1
|
||||
// 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1
|
||||
// 0x00010000 [16] FAIL (0) Test failed
|
||||
// 0x00001000 [12] WAITING (0) Waiting for test clock to start
|
||||
// 0x00000100 [8] RUNNING (0) Test running
|
||||
// 0x00000010 [4] DONE (0) Test complete
|
||||
// 0x00000001 [0] PASS (0) Test passed
|
||||
io_ro_32 status;
|
||||
|
||||
_REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
|
||||
// Result of frequency measurement, only valid when status_done=1
|
||||
// 0x3fffffe0 [29:5] KHZ (0x0000000)
|
||||
// 0x0000001f [4:0] FRAC (0x00)
|
||||
io_ro_32 result;
|
||||
} fc_hw_t;
|
||||
|
||||
typedef struct {
|
||||
clock_hw_t clk[10];
|
||||
|
||||
clock_resus_hw_t resus;
|
||||
|
||||
fc_hw_t fc0;
|
||||
|
||||
union {
|
||||
struct {
|
||||
_REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
|
||||
// enable clock in wake mode
|
||||
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
|
||||
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
|
||||
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
|
||||
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
|
||||
// 0x08000000 [27] CLK_SYS_SPI1 (1)
|
||||
// 0x04000000 [26] CLK_PERI_SPI1 (1)
|
||||
// 0x02000000 [25] CLK_SYS_SPI0 (1)
|
||||
// 0x01000000 [24] CLK_PERI_SPI0 (1)
|
||||
// 0x00800000 [23] CLK_SYS_SIOB (1)
|
||||
// 0x00400000 [22] CLK_SYS_RTC (1)
|
||||
// 0x00200000 [21] CLK_RTC_RTC (1)
|
||||
// 0x00100000 [20] CLK_SYS_ROSC (1)
|
||||
// 0x00080000 [19] CLK_SYS_ROM (1)
|
||||
// 0x00040000 [18] CLK_SYS_RESETS (1)
|
||||
// 0x00020000 [17] CLK_SYS_PWM (1)
|
||||
// 0x00010000 [16] CLK_SYS_POWER (1)
|
||||
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
|
||||
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
|
||||
// 0x00002000 [13] CLK_SYS_PIO1 (1)
|
||||
// 0x00001000 [12] CLK_SYS_PIO0 (1)
|
||||
// 0x00000800 [11] CLK_SYS_PADS (1)
|
||||
// 0x00000400 [10] CLK_SYS_LDO_POR (1)
|
||||
// 0x00000200 [9] CLK_SYS_JTAG (1)
|
||||
// 0x00000100 [8] CLK_SYS_IO (1)
|
||||
// 0x00000080 [7] CLK_SYS_I2C1 (1)
|
||||
// 0x00000040 [6] CLK_SYS_I2C0 (1)
|
||||
// 0x00000020 [5] CLK_SYS_DMA (1)
|
||||
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
|
||||
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
|
||||
// 0x00000004 [2] CLK_SYS_ADC0 (1)
|
||||
// 0x00000002 [1] CLK_ADC_ADC0 (1)
|
||||
// 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1)
|
||||
io_rw_32 wake_en0;
|
||||
|
||||
_REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
|
||||
// enable clock in wake mode
|
||||
// 0x00004000 [14] CLK_SYS_XOSC (1)
|
||||
// 0x00002000 [13] CLK_SYS_XIP (1)
|
||||
// 0x00001000 [12] CLK_SYS_WATCHDOG (1)
|
||||
// 0x00000800 [11] CLK_USB_USBCTRL (1)
|
||||
// 0x00000400 [10] CLK_SYS_USBCTRL (1)
|
||||
// 0x00000200 [9] CLK_SYS_UART1 (1)
|
||||
// 0x00000100 [8] CLK_PERI_UART1 (1)
|
||||
// 0x00000080 [7] CLK_SYS_UART0 (1)
|
||||
// 0x00000040 [6] CLK_PERI_UART0 (1)
|
||||
// 0x00000020 [5] CLK_SYS_TIMER (1)
|
||||
// 0x00000010 [4] CLK_SYS_TBMAN (1)
|
||||
// 0x00000008 [3] CLK_SYS_SYSINFO (1)
|
||||
// 0x00000004 [2] CLK_SYS_SYSCFG (1)
|
||||
// 0x00000002 [1] CLK_SYS_SRAM5 (1)
|
||||
// 0x00000001 [0] CLK_SYS_SRAM4 (1)
|
||||
io_rw_32 wake_en1;
|
||||
};
|
||||
// (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes)
|
||||
_REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
|
||||
// enable clock in wake mode
|
||||
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
|
||||
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
|
||||
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
|
||||
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
|
||||
// 0x08000000 [27] CLK_SYS_SPI1 (1)
|
||||
// 0x04000000 [26] CLK_PERI_SPI1 (1)
|
||||
// 0x02000000 [25] CLK_SYS_SPI0 (1)
|
||||
// 0x01000000 [24] CLK_PERI_SPI0 (1)
|
||||
// 0x00800000 [23] CLK_SYS_SIO (1)
|
||||
// 0x00400000 [22] CLK_SYS_RTC (1)
|
||||
// 0x00200000 [21] CLK_RTC_RTC (1)
|
||||
// 0x00100000 [20] CLK_SYS_ROSC (1)
|
||||
// 0x00080000 [19] CLK_SYS_ROM (1)
|
||||
// 0x00040000 [18] CLK_SYS_RESETS (1)
|
||||
// 0x00020000 [17] CLK_SYS_PWM (1)
|
||||
// 0x00010000 [16] CLK_SYS_PSM (1)
|
||||
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
|
||||
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
|
||||
// 0x00002000 [13] CLK_SYS_PIO1 (1)
|
||||
// 0x00001000 [12] CLK_SYS_PIO0 (1)
|
||||
// 0x00000800 [11] CLK_SYS_PADS (1)
|
||||
// 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1)
|
||||
// 0x00000200 [9] CLK_SYS_JTAG (1)
|
||||
// 0x00000100 [8] CLK_SYS_IO (1)
|
||||
// 0x00000080 [7] CLK_SYS_I2C1 (1)
|
||||
// 0x00000040 [6] CLK_SYS_I2C0 (1)
|
||||
// 0x00000020 [5] CLK_SYS_DMA (1)
|
||||
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
|
||||
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
|
||||
// 0x00000004 [2] CLK_SYS_ADC (1)
|
||||
// 0x00000002 [1] CLK_ADC_ADC (1)
|
||||
// 0x00000001 [0] CLK_SYS_CLOCKS (1)
|
||||
io_rw_32 wake_en[2];
|
||||
};
|
||||
|
||||
union {
|
||||
struct {
|
||||
_REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
|
||||
// enable clock in sleep mode
|
||||
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
|
||||
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
|
||||
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
|
||||
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
|
||||
// 0x08000000 [27] CLK_SYS_SPI1 (1)
|
||||
// 0x04000000 [26] CLK_PERI_SPI1 (1)
|
||||
// 0x02000000 [25] CLK_SYS_SPI0 (1)
|
||||
// 0x01000000 [24] CLK_PERI_SPI0 (1)
|
||||
// 0x00800000 [23] CLK_SYS_SIOB (1)
|
||||
// 0x00400000 [22] CLK_SYS_RTC (1)
|
||||
// 0x00200000 [21] CLK_RTC_RTC (1)
|
||||
// 0x00100000 [20] CLK_SYS_ROSC (1)
|
||||
// 0x00080000 [19] CLK_SYS_ROM (1)
|
||||
// 0x00040000 [18] CLK_SYS_RESETS (1)
|
||||
// 0x00020000 [17] CLK_SYS_PWM (1)
|
||||
// 0x00010000 [16] CLK_SYS_POWER (1)
|
||||
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
|
||||
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
|
||||
// 0x00002000 [13] CLK_SYS_PIO1 (1)
|
||||
// 0x00001000 [12] CLK_SYS_PIO0 (1)
|
||||
// 0x00000800 [11] CLK_SYS_PADS (1)
|
||||
// 0x00000400 [10] CLK_SYS_LDO_POR (1)
|
||||
// 0x00000200 [9] CLK_SYS_JTAG (1)
|
||||
// 0x00000100 [8] CLK_SYS_IO (1)
|
||||
// 0x00000080 [7] CLK_SYS_I2C1 (1)
|
||||
// 0x00000040 [6] CLK_SYS_I2C0 (1)
|
||||
// 0x00000020 [5] CLK_SYS_DMA (1)
|
||||
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
|
||||
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
|
||||
// 0x00000004 [2] CLK_SYS_ADC0 (1)
|
||||
// 0x00000002 [1] CLK_ADC_ADC0 (1)
|
||||
// 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1)
|
||||
io_rw_32 sleep_en0;
|
||||
|
||||
_REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
|
||||
// enable clock in sleep mode
|
||||
// 0x00004000 [14] CLK_SYS_XOSC (1)
|
||||
// 0x00002000 [13] CLK_SYS_XIP (1)
|
||||
// 0x00001000 [12] CLK_SYS_WATCHDOG (1)
|
||||
// 0x00000800 [11] CLK_USB_USBCTRL (1)
|
||||
// 0x00000400 [10] CLK_SYS_USBCTRL (1)
|
||||
// 0x00000200 [9] CLK_SYS_UART1 (1)
|
||||
// 0x00000100 [8] CLK_PERI_UART1 (1)
|
||||
// 0x00000080 [7] CLK_SYS_UART0 (1)
|
||||
// 0x00000040 [6] CLK_PERI_UART0 (1)
|
||||
// 0x00000020 [5] CLK_SYS_TIMER (1)
|
||||
// 0x00000010 [4] CLK_SYS_TBMAN (1)
|
||||
// 0x00000008 [3] CLK_SYS_SYSINFO (1)
|
||||
// 0x00000004 [2] CLK_SYS_SYSCFG (1)
|
||||
// 0x00000002 [1] CLK_SYS_SRAM5 (1)
|
||||
// 0x00000001 [0] CLK_SYS_SRAM4 (1)
|
||||
io_rw_32 sleep_en1;
|
||||
};
|
||||
// (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes)
|
||||
_REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
|
||||
// enable clock in sleep mode
|
||||
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
|
||||
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
|
||||
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
|
||||
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
|
||||
// 0x08000000 [27] CLK_SYS_SPI1 (1)
|
||||
// 0x04000000 [26] CLK_PERI_SPI1 (1)
|
||||
// 0x02000000 [25] CLK_SYS_SPI0 (1)
|
||||
// 0x01000000 [24] CLK_PERI_SPI0 (1)
|
||||
// 0x00800000 [23] CLK_SYS_SIO (1)
|
||||
// 0x00400000 [22] CLK_SYS_RTC (1)
|
||||
// 0x00200000 [21] CLK_RTC_RTC (1)
|
||||
// 0x00100000 [20] CLK_SYS_ROSC (1)
|
||||
// 0x00080000 [19] CLK_SYS_ROM (1)
|
||||
// 0x00040000 [18] CLK_SYS_RESETS (1)
|
||||
// 0x00020000 [17] CLK_SYS_PWM (1)
|
||||
// 0x00010000 [16] CLK_SYS_PSM (1)
|
||||
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
|
||||
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
|
||||
// 0x00002000 [13] CLK_SYS_PIO1 (1)
|
||||
// 0x00001000 [12] CLK_SYS_PIO0 (1)
|
||||
// 0x00000800 [11] CLK_SYS_PADS (1)
|
||||
// 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1)
|
||||
// 0x00000200 [9] CLK_SYS_JTAG (1)
|
||||
// 0x00000100 [8] CLK_SYS_IO (1)
|
||||
// 0x00000080 [7] CLK_SYS_I2C1 (1)
|
||||
// 0x00000040 [6] CLK_SYS_I2C0 (1)
|
||||
// 0x00000020 [5] CLK_SYS_DMA (1)
|
||||
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
|
||||
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
|
||||
// 0x00000004 [2] CLK_SYS_ADC (1)
|
||||
// 0x00000002 [1] CLK_ADC_ADC (1)
|
||||
// 0x00000001 [0] CLK_SYS_CLOCKS (1)
|
||||
io_rw_32 sleep_en[2];
|
||||
};
|
||||
|
||||
union {
|
||||
struct {
|
||||
_REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
|
||||
// indicates the state of the clock enable
|
||||
// 0x80000000 [31] CLK_SYS_SRAM3 (0)
|
||||
// 0x40000000 [30] CLK_SYS_SRAM2 (0)
|
||||
// 0x20000000 [29] CLK_SYS_SRAM1 (0)
|
||||
// 0x10000000 [28] CLK_SYS_SRAM0 (0)
|
||||
// 0x08000000 [27] CLK_SYS_SPI1 (0)
|
||||
// 0x04000000 [26] CLK_PERI_SPI1 (0)
|
||||
// 0x02000000 [25] CLK_SYS_SPI0 (0)
|
||||
// 0x01000000 [24] CLK_PERI_SPI0 (0)
|
||||
// 0x00800000 [23] CLK_SYS_SIOB (0)
|
||||
// 0x00400000 [22] CLK_SYS_RTC (0)
|
||||
// 0x00200000 [21] CLK_RTC_RTC (0)
|
||||
// 0x00100000 [20] CLK_SYS_ROSC (0)
|
||||
// 0x00080000 [19] CLK_SYS_ROM (0)
|
||||
// 0x00040000 [18] CLK_SYS_RESETS (0)
|
||||
// 0x00020000 [17] CLK_SYS_PWM (0)
|
||||
// 0x00010000 [16] CLK_SYS_POWER (0)
|
||||
// 0x00008000 [15] CLK_SYS_PLL_USB (0)
|
||||
// 0x00004000 [14] CLK_SYS_PLL_SYS (0)
|
||||
// 0x00002000 [13] CLK_SYS_PIO1 (0)
|
||||
// 0x00001000 [12] CLK_SYS_PIO0 (0)
|
||||
// 0x00000800 [11] CLK_SYS_PADS (0)
|
||||
// 0x00000400 [10] CLK_SYS_LDO_POR (0)
|
||||
// 0x00000200 [9] CLK_SYS_JTAG (0)
|
||||
// 0x00000100 [8] CLK_SYS_IO (0)
|
||||
// 0x00000080 [7] CLK_SYS_I2C1 (0)
|
||||
// 0x00000040 [6] CLK_SYS_I2C0 (0)
|
||||
// 0x00000020 [5] CLK_SYS_DMA (0)
|
||||
// 0x00000010 [4] CLK_SYS_BUSFABRIC (0)
|
||||
// 0x00000008 [3] CLK_SYS_BUSCTRL (0)
|
||||
// 0x00000004 [2] CLK_SYS_ADC0 (0)
|
||||
// 0x00000002 [1] CLK_ADC_ADC0 (0)
|
||||
// 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (0)
|
||||
io_ro_32 enabled0;
|
||||
|
||||
_REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
|
||||
// indicates the state of the clock enable
|
||||
// 0x00004000 [14] CLK_SYS_XOSC (0)
|
||||
// 0x00002000 [13] CLK_SYS_XIP (0)
|
||||
// 0x00001000 [12] CLK_SYS_WATCHDOG (0)
|
||||
// 0x00000800 [11] CLK_USB_USBCTRL (0)
|
||||
// 0x00000400 [10] CLK_SYS_USBCTRL (0)
|
||||
// 0x00000200 [9] CLK_SYS_UART1 (0)
|
||||
// 0x00000100 [8] CLK_PERI_UART1 (0)
|
||||
// 0x00000080 [7] CLK_SYS_UART0 (0)
|
||||
// 0x00000040 [6] CLK_PERI_UART0 (0)
|
||||
// 0x00000020 [5] CLK_SYS_TIMER (0)
|
||||
// 0x00000010 [4] CLK_SYS_TBMAN (0)
|
||||
// 0x00000008 [3] CLK_SYS_SYSINFO (0)
|
||||
// 0x00000004 [2] CLK_SYS_SYSCFG (0)
|
||||
// 0x00000002 [1] CLK_SYS_SRAM5 (0)
|
||||
// 0x00000001 [0] CLK_SYS_SRAM4 (0)
|
||||
io_ro_32 enabled1;
|
||||
};
|
||||
// (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes)
|
||||
_REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
|
||||
// indicates the state of the clock enable
|
||||
// 0x80000000 [31] CLK_SYS_SRAM3 (0)
|
||||
// 0x40000000 [30] CLK_SYS_SRAM2 (0)
|
||||
// 0x20000000 [29] CLK_SYS_SRAM1 (0)
|
||||
// 0x10000000 [28] CLK_SYS_SRAM0 (0)
|
||||
// 0x08000000 [27] CLK_SYS_SPI1 (0)
|
||||
// 0x04000000 [26] CLK_PERI_SPI1 (0)
|
||||
// 0x02000000 [25] CLK_SYS_SPI0 (0)
|
||||
// 0x01000000 [24] CLK_PERI_SPI0 (0)
|
||||
// 0x00800000 [23] CLK_SYS_SIO (0)
|
||||
// 0x00400000 [22] CLK_SYS_RTC (0)
|
||||
// 0x00200000 [21] CLK_RTC_RTC (0)
|
||||
// 0x00100000 [20] CLK_SYS_ROSC (0)
|
||||
// 0x00080000 [19] CLK_SYS_ROM (0)
|
||||
// 0x00040000 [18] CLK_SYS_RESETS (0)
|
||||
// 0x00020000 [17] CLK_SYS_PWM (0)
|
||||
// 0x00010000 [16] CLK_SYS_PSM (0)
|
||||
// 0x00008000 [15] CLK_SYS_PLL_USB (0)
|
||||
// 0x00004000 [14] CLK_SYS_PLL_SYS (0)
|
||||
// 0x00002000 [13] CLK_SYS_PIO1 (0)
|
||||
// 0x00001000 [12] CLK_SYS_PIO0 (0)
|
||||
// 0x00000800 [11] CLK_SYS_PADS (0)
|
||||
// 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (0)
|
||||
// 0x00000200 [9] CLK_SYS_JTAG (0)
|
||||
// 0x00000100 [8] CLK_SYS_IO (0)
|
||||
// 0x00000080 [7] CLK_SYS_I2C1 (0)
|
||||
// 0x00000040 [6] CLK_SYS_I2C0 (0)
|
||||
// 0x00000020 [5] CLK_SYS_DMA (0)
|
||||
// 0x00000010 [4] CLK_SYS_BUSFABRIC (0)
|
||||
// 0x00000008 [3] CLK_SYS_BUSCTRL (0)
|
||||
// 0x00000004 [2] CLK_SYS_ADC (0)
|
||||
// 0x00000002 [1] CLK_ADC_ADC (0)
|
||||
// 0x00000001 [0] CLK_SYS_CLOCKS (0)
|
||||
io_ro_32 enabled[2];
|
||||
};
|
||||
|
||||
_REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
|
||||
// Raw Interrupts
|
||||
// 0x00000001 [0] CLK_SYS_RESUS (0)
|
||||
io_ro_32 intr;
|
||||
|
||||
_REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
|
||||
// Interrupt Enable
|
||||
// 0x00000001 [0] CLK_SYS_RESUS (0)
|
||||
io_rw_32 inte;
|
||||
|
||||
_REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
|
||||
// Interrupt Force
|
||||
// 0x00000001 [0] CLK_SYS_RESUS (0)
|
||||
io_rw_32 intf;
|
||||
|
||||
_REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
|
||||
// Interrupt status after masking & forcing
|
||||
// 0x00000001 [0] CLK_SYS_RESUS (0)
|
||||
io_ro_32 ints;
|
||||
} clocks_hw_t;
|
||||
|
||||
#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE)
|
||||
static_assert(sizeof (clocks_hw_t) == 0x00c8, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_CLOCKS_H
|
||||
|
||||
|
|
@ -0,0 +1,239 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_DMA_H
|
||||
#define _HARDWARE_STRUCTS_DMA_H
|
||||
|
||||
/**
|
||||
* \file rp2040/dma.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/dma.h"
|
||||
#include "hardware/structs/dma_debug.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR
|
||||
// DMA Channel 0 Read Address pointer
|
||||
// 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes
|
||||
io_rw_32 read_addr;
|
||||
|
||||
_REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR
|
||||
// DMA Channel 0 Write Address pointer
|
||||
// 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes
|
||||
io_rw_32 write_addr;
|
||||
|
||||
_REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT
|
||||
// DMA Channel 0 Transfer Count
|
||||
// 0xffffffff [31:0] CH0_TRANS_COUNT (0x00000000) Program the number of bus transfers a channel will...
|
||||
io_rw_32 transfer_count;
|
||||
|
||||
_REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG
|
||||
// DMA Channel 0 Control and Status
|
||||
// 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags
|
||||
// 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error
|
||||
// 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error
|
||||
// 0x01000000 [24] BUSY (0) This flag goes high when the channel starts a new...
|
||||
// 0x00800000 [23] SNIFF_EN (0) If 1, this channel's data transfers are visible to the...
|
||||
// 0x00400000 [22] BSWAP (0) Apply byte-swap transformation to DMA data
|
||||
// 0x00200000 [21] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the...
|
||||
// 0x001f8000 [20:15] TREQ_SEL (0x00) Select a Transfer Request signal
|
||||
// 0x00007800 [14:11] CHAIN_TO (0x0) When this channel completes, it will trigger the channel...
|
||||
// 0x00000400 [10] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses
|
||||
// 0x000003c0 [9:6] RING_SIZE (0x0) Size of address wrap region
|
||||
// 0x00000020 [5] INCR_WRITE (0) If 1, the write address increments with each transfer
|
||||
// 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer
|
||||
// 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word)
|
||||
// 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in...
|
||||
// 0x00000001 [0] EN (0) DMA Channel Enable
|
||||
io_rw_32 ctrl_trig;
|
||||
|
||||
_REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL
|
||||
// Alias for channel 0 CTRL register
|
||||
// 0xffffffff [31:0] CH0_AL1_CTRL (-)
|
||||
io_rw_32 al1_ctrl;
|
||||
|
||||
_REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR
|
||||
// Alias for channel 0 READ_ADDR register
|
||||
// 0xffffffff [31:0] CH0_AL1_READ_ADDR (-)
|
||||
io_rw_32 al1_read_addr;
|
||||
|
||||
_REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR
|
||||
// Alias for channel 0 WRITE_ADDR register
|
||||
// 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-)
|
||||
io_rw_32 al1_write_addr;
|
||||
|
||||
_REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG
|
||||
// Alias for channel 0 TRANS_COUNT register +
|
||||
// 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-)
|
||||
io_rw_32 al1_transfer_count_trig;
|
||||
|
||||
_REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL
|
||||
// Alias for channel 0 CTRL register
|
||||
// 0xffffffff [31:0] CH0_AL2_CTRL (-)
|
||||
io_rw_32 al2_ctrl;
|
||||
|
||||
_REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT
|
||||
// Alias for channel 0 TRANS_COUNT register
|
||||
// 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-)
|
||||
io_rw_32 al2_transfer_count;
|
||||
|
||||
_REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR
|
||||
// Alias for channel 0 READ_ADDR register
|
||||
// 0xffffffff [31:0] CH0_AL2_READ_ADDR (-)
|
||||
io_rw_32 al2_read_addr;
|
||||
|
||||
_REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG
|
||||
// Alias for channel 0 WRITE_ADDR register +
|
||||
// 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-)
|
||||
io_rw_32 al2_write_addr_trig;
|
||||
|
||||
_REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL
|
||||
// Alias for channel 0 CTRL register
|
||||
// 0xffffffff [31:0] CH0_AL3_CTRL (-)
|
||||
io_rw_32 al3_ctrl;
|
||||
|
||||
_REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR
|
||||
// Alias for channel 0 WRITE_ADDR register
|
||||
// 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-)
|
||||
io_rw_32 al3_write_addr;
|
||||
|
||||
_REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT
|
||||
// Alias for channel 0 TRANS_COUNT register
|
||||
// 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-)
|
||||
io_rw_32 al3_transfer_count;
|
||||
|
||||
_REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG
|
||||
// Alias for channel 0 READ_ADDR register +
|
||||
// 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-)
|
||||
io_rw_32 al3_read_addr_trig;
|
||||
} dma_channel_hw_t;
|
||||
|
||||
typedef struct {
|
||||
_REG_(DMA_INTR_OFFSET) // DMA_INTR
|
||||
// Interrupt Status (raw)
|
||||
// 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0
|
||||
io_rw_32 intr;
|
||||
|
||||
_REG_(DMA_INTE0_OFFSET) // DMA_INTE0
|
||||
// Interrupt Enables for IRQ 0
|
||||
// 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0
|
||||
io_rw_32 inte;
|
||||
|
||||
_REG_(DMA_INTF0_OFFSET) // DMA_INTF0
|
||||
// Force Interrupts
|
||||
// 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0
|
||||
io_rw_32 intf;
|
||||
|
||||
_REG_(DMA_INTS0_OFFSET) // DMA_INTS0
|
||||
// Interrupt Status for IRQ 0
|
||||
// 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are...
|
||||
io_rw_32 ints;
|
||||
} dma_irq_ctrl_hw_t;
|
||||
|
||||
typedef struct {
|
||||
dma_channel_hw_t ch[12];
|
||||
|
||||
uint32_t _pad0[64];
|
||||
|
||||
union {
|
||||
struct {
|
||||
_REG_(DMA_INTR_OFFSET) // DMA_INTR
|
||||
// Interrupt Status (raw)
|
||||
// 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0
|
||||
io_rw_32 intr;
|
||||
|
||||
_REG_(DMA_INTE0_OFFSET) // DMA_INTE0
|
||||
// Interrupt Enables for IRQ 0
|
||||
// 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0
|
||||
io_rw_32 inte0;
|
||||
|
||||
_REG_(DMA_INTF0_OFFSET) // DMA_INTF0
|
||||
// Force Interrupts
|
||||
// 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0
|
||||
io_rw_32 intf0;
|
||||
|
||||
_REG_(DMA_INTS0_OFFSET) // DMA_INTS0
|
||||
// Interrupt Status for IRQ 0
|
||||
// 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are...
|
||||
io_rw_32 ints0;
|
||||
|
||||
uint32_t __pad0;
|
||||
|
||||
_REG_(DMA_INTE1_OFFSET) // DMA_INTE1
|
||||
// Interrupt Enables for IRQ 1
|
||||
// 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1
|
||||
io_rw_32 inte1;
|
||||
|
||||
_REG_(DMA_INTF1_OFFSET) // DMA_INTF1
|
||||
// Force Interrupts for IRQ 1
|
||||
// 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1
|
||||
io_rw_32 intf1;
|
||||
|
||||
_REG_(DMA_INTS1_OFFSET) // DMA_INTS1
|
||||
// Interrupt Status (masked) for IRQ 1
|
||||
// 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are...
|
||||
io_rw_32 ints1;
|
||||
};
|
||||
dma_irq_ctrl_hw_t irq_ctrl[2];
|
||||
};
|
||||
|
||||
// (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
|
||||
_REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
|
||||
// Pacing (X/Y) Fractional Timer +
|
||||
// 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend
|
||||
// 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor
|
||||
io_rw_32 timer[4];
|
||||
|
||||
_REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
|
||||
// Trigger one or more channels simultaneously
|
||||
// 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel
|
||||
io_wo_32 multi_channel_trigger;
|
||||
|
||||
_REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL
|
||||
// Sniffer Control
|
||||
// 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)...
|
||||
// 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read
|
||||
// 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,...
|
||||
// 0x000001e0 [8:5] CALC (0x0)
|
||||
// 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe
|
||||
// 0x00000001 [0] EN (0) Enable sniffer
|
||||
io_rw_32 sniff_ctrl;
|
||||
|
||||
_REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA
|
||||
// Data accumulator for sniff hardware
|
||||
// 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA...
|
||||
io_rw_32 sniff_data;
|
||||
|
||||
uint32_t _pad1;
|
||||
|
||||
_REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS
|
||||
// Debug RAF, WAF, TDF levels
|
||||
// 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level
|
||||
// 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level
|
||||
// 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level
|
||||
io_ro_32 fifo_levels;
|
||||
|
||||
_REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT
|
||||
// Abort an in-progress transfer sequence on one or more channels
|
||||
// 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel
|
||||
io_wo_32 abort;
|
||||
} dma_hw_t;
|
||||
|
||||
#define dma_hw ((dma_hw_t *)DMA_BASE)
|
||||
static_assert(sizeof (dma_hw_t) == 0x0448, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_DMA_H
|
||||
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_DMA_DEBUG_H
|
||||
#define _HARDWARE_STRUCTS_DMA_DEBUG_H
|
||||
|
||||
/**
|
||||
* \file rp2040/dma_debug.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/dma.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(DMA_CH0_DBG_CTDREQ_OFFSET) // DMA_CH0_DBG_CTDREQ
|
||||
// Read: get channel DREQ counter (i
|
||||
// 0x0000003f [5:0] CH0_DBG_CTDREQ (0x00)
|
||||
io_rw_32 dbg_ctdreq;
|
||||
|
||||
_REG_(DMA_CH0_DBG_TCR_OFFSET) // DMA_CH0_DBG_TCR
|
||||
// Read to get channel TRANS_COUNT reload value, i
|
||||
// 0xffffffff [31:0] CH0_DBG_TCR (0x00000000)
|
||||
io_ro_32 dbg_tcr;
|
||||
|
||||
uint32_t _pad0[14];
|
||||
} dma_debug_channel_hw_t;
|
||||
|
||||
typedef struct {
|
||||
dma_debug_channel_hw_t ch[12];
|
||||
} dma_debug_hw_t;
|
||||
|
||||
#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_DMA_DEBUG_H
|
||||
|
||||
|
|
@ -0,0 +1,338 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_I2C_H
|
||||
#define _HARDWARE_STRUCTS_I2C_H
|
||||
|
||||
/**
|
||||
* \file rp2040/i2c.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/i2c.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON
|
||||
// I2C Control Register
|
||||
// 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of...
|
||||
// 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus...
|
||||
// 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY...
|
||||
// 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt...
|
||||
// 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,...
|
||||
// 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when...
|
||||
// 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in...
|
||||
// 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the...
|
||||
// 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c...
|
||||
// 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled
|
||||
io_rw_32 con;
|
||||
|
||||
_REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR
|
||||
// I2C Target Address Register
|
||||
// 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID...
|
||||
// 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is...
|
||||
// 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction
|
||||
io_rw_32 tar;
|
||||
|
||||
_REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR
|
||||
// I2C Slave Address Register
|
||||
// 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is...
|
||||
io_rw_32 sar;
|
||||
|
||||
uint32_t _pad0;
|
||||
|
||||
_REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD
|
||||
// I2C Rx/Tx Data Buffer and Command Register
|
||||
// 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address...
|
||||
// 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the...
|
||||
// 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the...
|
||||
// 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed
|
||||
// 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or...
|
||||
io_rw_32 data_cmd;
|
||||
|
||||
_REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT
|
||||
// Standard Speed I2C Clock SCL High Count Register
|
||||
// 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction...
|
||||
io_rw_32 ss_scl_hcnt;
|
||||
|
||||
_REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT
|
||||
// Standard Speed I2C Clock SCL Low Count Register
|
||||
// 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction...
|
||||
io_rw_32 ss_scl_lcnt;
|
||||
|
||||
_REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT
|
||||
// Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
|
||||
// 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction...
|
||||
io_rw_32 fs_scl_hcnt;
|
||||
|
||||
_REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT
|
||||
// Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
|
||||
// 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction...
|
||||
io_rw_32 fs_scl_lcnt;
|
||||
|
||||
uint32_t _pad1[2];
|
||||
|
||||
_REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT
|
||||
// I2C Interrupt Status Register
|
||||
// 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of...
|
||||
// 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit
|
||||
// 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of...
|
||||
// 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit
|
||||
// 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit
|
||||
// 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit
|
||||
// 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit
|
||||
// 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit
|
||||
// 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit
|
||||
// 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit
|
||||
// 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit
|
||||
// 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit
|
||||
// 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit
|
||||
io_ro_32 intr_stat;
|
||||
|
||||
_REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK
|
||||
// I2C Interrupt Mask Register
|
||||
// 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in...
|
||||
// 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register
|
||||
// 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register
|
||||
// 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register
|
||||
// 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register
|
||||
// 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register
|
||||
// 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register
|
||||
// 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register
|
||||
// 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register
|
||||
// 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register
|
||||
// 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register
|
||||
// 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register
|
||||
// 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register
|
||||
io_rw_32 intr_mask;
|
||||
|
||||
_REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT
|
||||
// I2C Raw Interrupt Status Register
|
||||
// 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on...
|
||||
// 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it...
|
||||
// 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has...
|
||||
// 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the...
|
||||
// 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set...
|
||||
// 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,...
|
||||
// 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,...
|
||||
// 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a...
|
||||
// 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs...
|
||||
// 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to...
|
||||
// 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the...
|
||||
// 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to...
|
||||
// 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer...
|
||||
io_ro_32 raw_intr_stat;
|
||||
|
||||
_REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL
|
||||
// I2C Receive FIFO Threshold Register
|
||||
// 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level
|
||||
io_rw_32 rx_tl;
|
||||
|
||||
_REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL
|
||||
// I2C Transmit FIFO Threshold Register
|
||||
// 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level
|
||||
io_rw_32 tx_tl;
|
||||
|
||||
_REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR
|
||||
// Clear Combined and Individual Interrupt Register
|
||||
// 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all...
|
||||
io_ro_32 clr_intr;
|
||||
|
||||
_REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER
|
||||
// Clear RX_UNDER Interrupt Register
|
||||
// 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit...
|
||||
io_ro_32 clr_rx_under;
|
||||
|
||||
_REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER
|
||||
// Clear RX_OVER Interrupt Register
|
||||
// 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit...
|
||||
io_ro_32 clr_rx_over;
|
||||
|
||||
_REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER
|
||||
// Clear TX_OVER Interrupt Register
|
||||
// 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit...
|
||||
io_ro_32 clr_tx_over;
|
||||
|
||||
_REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ
|
||||
// Clear RD_REQ Interrupt Register
|
||||
// 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)...
|
||||
io_ro_32 clr_rd_req;
|
||||
|
||||
_REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT
|
||||
// Clear TX_ABRT Interrupt Register
|
||||
// 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit...
|
||||
io_ro_32 clr_tx_abrt;
|
||||
|
||||
_REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE
|
||||
// Clear RX_DONE Interrupt Register
|
||||
// 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit...
|
||||
io_ro_32 clr_rx_done;
|
||||
|
||||
_REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY
|
||||
// Clear ACTIVITY Interrupt Register
|
||||
// 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if...
|
||||
io_ro_32 clr_activity;
|
||||
|
||||
_REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET
|
||||
// Clear STOP_DET Interrupt Register
|
||||
// 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit...
|
||||
io_ro_32 clr_stop_det;
|
||||
|
||||
_REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET
|
||||
// Clear START_DET Interrupt Register
|
||||
// 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit...
|
||||
io_ro_32 clr_start_det;
|
||||
|
||||
_REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL
|
||||
// Clear GEN_CALL Interrupt Register
|
||||
// 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit...
|
||||
io_ro_32 clr_gen_call;
|
||||
|
||||
_REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE
|
||||
// I2C ENABLE Register
|
||||
// 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data...
|
||||
// 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort
|
||||
// 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled
|
||||
io_rw_32 enable;
|
||||
|
||||
_REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS
|
||||
// I2C STATUS Register
|
||||
// 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status
|
||||
// 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status
|
||||
// 0x00000010 [4] RFF (0) Receive FIFO Completely Full
|
||||
// 0x00000008 [3] RFNE (0) Receive FIFO Not Empty
|
||||
// 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty
|
||||
// 0x00000002 [1] TFNF (1) Transmit FIFO Not Full
|
||||
// 0x00000001 [0] ACTIVITY (0) I2C Activity Status
|
||||
io_ro_32 status;
|
||||
|
||||
_REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR
|
||||
// I2C Transmit FIFO Level Register
|
||||
// 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level
|
||||
io_ro_32 txflr;
|
||||
|
||||
_REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR
|
||||
// I2C Receive FIFO Level Register
|
||||
// 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level
|
||||
io_ro_32 rxflr;
|
||||
|
||||
_REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD
|
||||
// I2C SDA Hold Time Length Register
|
||||
// 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk...
|
||||
// 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk...
|
||||
io_rw_32 sda_hold;
|
||||
|
||||
_REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE
|
||||
// I2C Transmit Abort Source Register
|
||||
// 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands...
|
||||
// 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit
|
||||
// 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode...
|
||||
// 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while...
|
||||
// 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read...
|
||||
// 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost...
|
||||
// 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a...
|
||||
// 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled...
|
||||
// 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT...
|
||||
// 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled...
|
||||
// 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START...
|
||||
// 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed...
|
||||
// 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode...
|
||||
// 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has...
|
||||
// 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit
|
||||
// 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit...
|
||||
// 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit...
|
||||
// 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit...
|
||||
io_ro_32 tx_abrt_source;
|
||||
|
||||
_REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY
|
||||
// Generate Slave Data NACK Register
|
||||
// 0x00000001 [0] NACK (0) Generate NACK
|
||||
io_rw_32 slv_data_nack_only;
|
||||
|
||||
_REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR
|
||||
// DMA Control Register
|
||||
// 0x00000002 [1] TDMAE (0) Transmit DMA Enable
|
||||
// 0x00000001 [0] RDMAE (0) Receive DMA Enable
|
||||
io_rw_32 dma_cr;
|
||||
|
||||
_REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR
|
||||
// DMA Transmit Data Level Register
|
||||
// 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level
|
||||
io_rw_32 dma_tdlr;
|
||||
|
||||
_REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR
|
||||
// DMA Transmit Data Level Register
|
||||
// 0x0000000f [3:0] DMARDL (0x0) Receive Data Level
|
||||
io_rw_32 dma_rdlr;
|
||||
|
||||
_REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP
|
||||
// I2C SDA Setup Register
|
||||
// 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup
|
||||
io_rw_32 sda_setup;
|
||||
|
||||
_REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL
|
||||
// I2C ACK General Call Register
|
||||
// 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call
|
||||
io_rw_32 ack_general_call;
|
||||
|
||||
_REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS
|
||||
// I2C Enable Status Register
|
||||
// 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost
|
||||
// 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive)
|
||||
// 0x00000001 [0] IC_EN (0) ic_en Status
|
||||
io_ro_32 enable_status;
|
||||
|
||||
_REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN
|
||||
// I2C SS, FS or FM+ spike suppression limit
|
||||
// 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction...
|
||||
io_rw_32 fs_spklen;
|
||||
|
||||
uint32_t _pad2;
|
||||
|
||||
_REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET
|
||||
// Clear RESTART_DET Interrupt Register
|
||||
// 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt...
|
||||
io_ro_32 clr_restart_det;
|
||||
|
||||
uint32_t _pad3[18];
|
||||
|
||||
_REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1
|
||||
// Component Parameter Register 1
|
||||
// 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16
|
||||
// 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16
|
||||
// 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible
|
||||
// 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled
|
||||
// 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs
|
||||
// 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode
|
||||
// 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE
|
||||
// 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits
|
||||
io_ro_32 comp_param_1;
|
||||
|
||||
_REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION
|
||||
// I2C Component Version Register
|
||||
// 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a)
|
||||
io_ro_32 comp_version;
|
||||
|
||||
_REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE
|
||||
// I2C Component Type Register
|
||||
// 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40
|
||||
io_ro_32 comp_type;
|
||||
} i2c_hw_t;
|
||||
|
||||
#define i2c0_hw ((i2c_hw_t *)I2C0_BASE)
|
||||
#define i2c1_hw ((i2c_hw_t *)I2C1_BASE)
|
||||
static_assert(sizeof (i2c_hw_t) == 0x0100, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_I2C_H
|
||||
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_INTERP_H
|
||||
#define _HARDWARE_STRUCTS_INTERP_H
|
||||
|
||||
/**
|
||||
* \file rp2040/interp.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/sio.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)
|
||||
_REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0
|
||||
// Read/write access to accumulator 0
|
||||
// 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000)
|
||||
io_rw_32 accum[2];
|
||||
|
||||
// (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)
|
||||
_REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0
|
||||
// Read/write access to BASE0 register
|
||||
// 0xffffffff [31:0] INTERP0_BASE0 (0x00000000)
|
||||
io_rw_32 base[3];
|
||||
|
||||
// (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)
|
||||
_REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0
|
||||
// Read LANE0 result, and simultaneously write lane results to both accumulators (POP)
|
||||
// 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000)
|
||||
io_ro_32 pop[3];
|
||||
|
||||
// (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)
|
||||
_REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0
|
||||
// Read LANE0 result, without altering any internal state (PEEK)
|
||||
// 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000)
|
||||
io_ro_32 peek[3];
|
||||
|
||||
// (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)
|
||||
_REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0
|
||||
// Control register for lane 0
|
||||
// 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set
|
||||
// 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set
|
||||
// 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set
|
||||
// 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core
|
||||
// 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the...
|
||||
// 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result
|
||||
// 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's...
|
||||
// 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this...
|
||||
// 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator...
|
||||
// 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask...
|
||||
// 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive)
|
||||
// 0x0000001f [4:0] SHIFT (0x00) Logical right-shift applied to accumulator before masking
|
||||
io_rw_32 ctrl[2];
|
||||
|
||||
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)
|
||||
_REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD
|
||||
// Values written here are atomically added to ACCUM0
|
||||
// 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000)
|
||||
io_rw_32 add_raw[2];
|
||||
|
||||
_REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0
|
||||
// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
|
||||
// 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000)
|
||||
io_wo_32 base01;
|
||||
} interp_hw_t;
|
||||
|
||||
#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET))
|
||||
static_assert(sizeof (interp_hw_t) == 0x0040, "");
|
||||
#define interp0_hw (&interp_hw_array[0])
|
||||
#define interp1_hw (&interp_hw_array[1])
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_INTERP_H
|
||||
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_IO_BANK0_H
|
||||
#define _HARDWARE_STRUCTS_IO_BANK0_H
|
||||
|
||||
/**
|
||||
* \file rp2040/io_bank0.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/io_bank0.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
/**
|
||||
* \brief GPIO pin function selectors on RP2040 (used as typedef \ref gpio_function_t)
|
||||
* \ingroup hardware_gpio
|
||||
*/
|
||||
typedef enum gpio_function_rp2040 {
|
||||
GPIO_FUNC_XIP = 0, ///< Select XIP as GPIO pin function
|
||||
GPIO_FUNC_SPI = 1, ///< Select SPI as GPIO pin function
|
||||
GPIO_FUNC_UART = 2, ///< Select UART as GPIO pin function
|
||||
GPIO_FUNC_I2C = 3, ///< Select I2C as GPIO pin function
|
||||
GPIO_FUNC_PWM = 4, ///< Select PWM as GPIO pin function
|
||||
GPIO_FUNC_SIO = 5, ///< Select SIO as GPIO pin function
|
||||
GPIO_FUNC_PIO0 = 6, ///< Select PIO0 as GPIO pin function
|
||||
GPIO_FUNC_PIO1 = 7, ///< Select PIO1 as GPIO pin function
|
||||
GPIO_FUNC_GPCK = 8, ///< Select GPCK as GPIO pin function
|
||||
GPIO_FUNC_USB = 9, ///< Select USB as GPIO pin function
|
||||
GPIO_FUNC_NULL = 0x1f, ///< Select NULL as GPIO pin function
|
||||
} gpio_function_t;
|
||||
|
||||
typedef struct {
|
||||
_REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS
|
||||
// GPIO status
|
||||
// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
|
||||
// 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied
|
||||
// 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied
|
||||
// 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied
|
||||
// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
|
||||
// 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register...
|
||||
// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
|
||||
// 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register...
|
||||
io_ro_32 status;
|
||||
|
||||
_REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL
|
||||
// GPIO control including function select and overrides
|
||||
// 0x30000000 [29:28] IRQOVER (0x0)
|
||||
// 0x00030000 [17:16] INOVER (0x0)
|
||||
// 0x00003000 [13:12] OEOVER (0x0)
|
||||
// 0x00000300 [9:8] OUTOVER (0x0)
|
||||
// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
|
||||
io_rw_32 ctrl;
|
||||
} io_bank0_status_ctrl_hw_t;
|
||||
|
||||
typedef struct {
|
||||
// (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
|
||||
_REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
|
||||
// Interrupt Enable for proc0
|
||||
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
|
||||
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
|
||||
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
|
||||
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
|
||||
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
|
||||
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
|
||||
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
|
||||
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
|
||||
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
|
||||
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
|
||||
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
|
||||
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
|
||||
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
|
||||
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
|
||||
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
|
||||
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
|
||||
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
|
||||
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
|
||||
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
|
||||
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
|
||||
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
|
||||
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
|
||||
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
|
||||
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
|
||||
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
|
||||
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
|
||||
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
|
||||
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
|
||||
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
|
||||
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
|
||||
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
|
||||
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
|
||||
io_rw_32 inte[4];
|
||||
|
||||
// (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
|
||||
_REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
|
||||
// Interrupt Force for proc0
|
||||
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
|
||||
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
|
||||
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
|
||||
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
|
||||
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
|
||||
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
|
||||
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
|
||||
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
|
||||
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
|
||||
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
|
||||
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
|
||||
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
|
||||
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
|
||||
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
|
||||
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
|
||||
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
|
||||
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
|
||||
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
|
||||
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
|
||||
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
|
||||
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
|
||||
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
|
||||
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
|
||||
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
|
||||
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
|
||||
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
|
||||
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
|
||||
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
|
||||
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
|
||||
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
|
||||
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
|
||||
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
|
||||
io_rw_32 intf[4];
|
||||
|
||||
// (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
|
||||
_REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
|
||||
// Interrupt status after masking & forcing for proc0
|
||||
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
|
||||
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
|
||||
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
|
||||
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
|
||||
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
|
||||
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
|
||||
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
|
||||
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
|
||||
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
|
||||
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
|
||||
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
|
||||
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
|
||||
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
|
||||
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
|
||||
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
|
||||
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
|
||||
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
|
||||
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
|
||||
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
|
||||
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
|
||||
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
|
||||
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
|
||||
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
|
||||
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
|
||||
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
|
||||
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
|
||||
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
|
||||
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
|
||||
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
|
||||
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
|
||||
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
|
||||
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
|
||||
io_ro_32 ints[4];
|
||||
} io_bank0_irq_ctrl_hw_t;
|
||||
|
||||
/// \tag::io_bank0_hw[]
|
||||
typedef struct {
|
||||
io_bank0_status_ctrl_hw_t io[30];
|
||||
|
||||
// (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
|
||||
_REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
|
||||
// Raw Interrupts
|
||||
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
|
||||
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
|
||||
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
|
||||
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
|
||||
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
|
||||
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
|
||||
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
|
||||
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
|
||||
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
|
||||
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
|
||||
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
|
||||
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
|
||||
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
|
||||
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
|
||||
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
|
||||
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
|
||||
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
|
||||
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
|
||||
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
|
||||
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
|
||||
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
|
||||
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
|
||||
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
|
||||
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
|
||||
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
|
||||
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
|
||||
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
|
||||
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
|
||||
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
|
||||
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
|
||||
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
|
||||
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
|
||||
io_rw_32 intr[4];
|
||||
|
||||
union {
|
||||
struct {
|
||||
io_bank0_irq_ctrl_hw_t proc0_irq_ctrl;
|
||||
io_bank0_irq_ctrl_hw_t proc1_irq_ctrl;
|
||||
io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl;
|
||||
};
|
||||
io_bank0_irq_ctrl_hw_t irq_ctrl[3];
|
||||
};
|
||||
} io_bank0_hw_t;
|
||||
/// \end::io_bank0_hw[]
|
||||
|
||||
#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE)
|
||||
static_assert(sizeof (io_bank0_hw_t) == 0x0190, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_IO_BANK0_H
|
||||
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_IO_QSPI_H
|
||||
#define _HARDWARE_STRUCTS_IO_QSPI_H
|
||||
|
||||
/**
|
||||
* \file rp2040/io_qspi.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/io_qspi.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
/**
|
||||
* \brief QSPI pin function selectors on RP2040 (used as typedef \ref gpio_function1_t)
|
||||
*/
|
||||
typedef enum gpio_function1_rp2040 {
|
||||
GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function
|
||||
GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function
|
||||
GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function
|
||||
} gpio_function1_t;
|
||||
|
||||
typedef struct {
|
||||
_REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
|
||||
// GPIO status
|
||||
// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
|
||||
// 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied
|
||||
// 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied
|
||||
// 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied
|
||||
// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
|
||||
// 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register...
|
||||
// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
|
||||
// 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register...
|
||||
io_ro_32 status;
|
||||
|
||||
_REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
|
||||
// GPIO control including function select and overrides
|
||||
// 0x30000000 [29:28] IRQOVER (0x0)
|
||||
// 0x00030000 [17:16] INOVER (0x0)
|
||||
// 0x00003000 [13:12] OEOVER (0x0)
|
||||
// 0x00000300 [9:8] OUTOVER (0x0)
|
||||
// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
|
||||
io_rw_32 ctrl;
|
||||
} io_qspi_status_ctrl_hw_t;
|
||||
|
||||
typedef struct {
|
||||
_REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
|
||||
// Interrupt Enable for proc0
|
||||
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
|
||||
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
|
||||
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
|
||||
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
|
||||
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
|
||||
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
|
||||
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
|
||||
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
|
||||
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
|
||||
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
|
||||
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
|
||||
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
|
||||
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
|
||||
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
|
||||
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
|
||||
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
|
||||
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
|
||||
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
|
||||
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
|
||||
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
|
||||
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
|
||||
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
|
||||
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
|
||||
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
|
||||
io_rw_32 inte;
|
||||
|
||||
_REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
|
||||
// Interrupt Force for proc0
|
||||
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
|
||||
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
|
||||
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
|
||||
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
|
||||
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
|
||||
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
|
||||
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
|
||||
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
|
||||
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
|
||||
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
|
||||
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
|
||||
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
|
||||
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
|
||||
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
|
||||
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
|
||||
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
|
||||
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
|
||||
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
|
||||
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
|
||||
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
|
||||
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
|
||||
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
|
||||
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
|
||||
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
|
||||
io_rw_32 intf;
|
||||
|
||||
_REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
|
||||
// Interrupt status after masking & forcing for proc0
|
||||
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
|
||||
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
|
||||
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
|
||||
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
|
||||
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
|
||||
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
|
||||
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
|
||||
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
|
||||
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
|
||||
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
|
||||
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
|
||||
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
|
||||
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
|
||||
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
|
||||
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
|
||||
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
|
||||
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
|
||||
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
|
||||
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
|
||||
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
|
||||
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
|
||||
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
|
||||
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
|
||||
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
|
||||
io_ro_32 ints;
|
||||
} io_qspi_irq_ctrl_hw_t;
|
||||
|
||||
typedef struct {
|
||||
io_qspi_status_ctrl_hw_t io[6];
|
||||
|
||||
_REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
|
||||
// Raw Interrupts
|
||||
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
|
||||
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
|
||||
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
|
||||
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
|
||||
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
|
||||
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
|
||||
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
|
||||
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
|
||||
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
|
||||
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
|
||||
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
|
||||
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
|
||||
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
|
||||
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
|
||||
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
|
||||
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
|
||||
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
|
||||
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
|
||||
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
|
||||
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
|
||||
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
|
||||
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
|
||||
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
|
||||
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
|
||||
io_rw_32 intr;
|
||||
|
||||
union {
|
||||
struct {
|
||||
io_qspi_irq_ctrl_hw_t proc0_irq_ctrl;
|
||||
io_qspi_irq_ctrl_hw_t proc1_irq_ctrl;
|
||||
io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl;
|
||||
};
|
||||
io_qspi_irq_ctrl_hw_t irq_ctrl[3];
|
||||
};
|
||||
} io_qspi_hw_t;
|
||||
|
||||
#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE)
|
||||
static_assert(sizeof (io_qspi_hw_t) == 0x0058, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_IO_QSPI_H
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
// Support old header for compatibility (and if included, support old variable name)
|
||||
#include "hardware/structs/io_bank0.h"
|
||||
#define iobank0_hw io_bank0_hw
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
// Support old header for compatibility (and if included, support old variable name)
|
||||
#include "hardware/structs/io_qspi.h"
|
||||
#define ioqspi_hw io_qspi_hw
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_M0PLUS_H
|
||||
#define _HARDWARE_STRUCTS_M0PLUS_H
|
||||
|
||||
/**
|
||||
* \file rp2040/m0plus.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/m0plus.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
uint32_t _pad0[14340];
|
||||
|
||||
_REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR
|
||||
// SysTick Control and Status Register
|
||||
// 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read
|
||||
// 0x00000004 [2] CLKSOURCE (0) SysTick clock source
|
||||
// 0x00000002 [1] TICKINT (0) Enables SysTick exception request: +
|
||||
// 0x00000001 [0] ENABLE (0) Enable SysTick counter: +
|
||||
io_rw_32 syst_csr;
|
||||
|
||||
_REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR
|
||||
// SysTick Reload Value Register
|
||||
// 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register...
|
||||
io_rw_32 syst_rvr;
|
||||
|
||||
_REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR
|
||||
// SysTick Current Value Register
|
||||
// 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter
|
||||
io_rw_32 syst_cvr;
|
||||
|
||||
_REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB
|
||||
// SysTick Calibration Value Register
|
||||
// 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the...
|
||||
// 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact...
|
||||
// 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)...
|
||||
io_ro_32 syst_calib;
|
||||
|
||||
uint32_t _pad1[56];
|
||||
|
||||
_REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER
|
||||
// Interrupt Set-Enable Register
|
||||
// 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits
|
||||
io_rw_32 nvic_iser;
|
||||
|
||||
uint32_t _pad2[31];
|
||||
|
||||
_REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER
|
||||
// Interrupt Clear-Enable Register
|
||||
// 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits
|
||||
io_rw_32 nvic_icer;
|
||||
|
||||
uint32_t _pad3[31];
|
||||
|
||||
_REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR
|
||||
// Interrupt Set-Pending Register
|
||||
// 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits
|
||||
io_rw_32 nvic_ispr;
|
||||
|
||||
uint32_t _pad4[31];
|
||||
|
||||
_REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR
|
||||
// Interrupt Clear-Pending Register
|
||||
// 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits
|
||||
io_rw_32 nvic_icpr;
|
||||
|
||||
uint32_t _pad5[95];
|
||||
|
||||
// (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes)
|
||||
_REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0
|
||||
// Interrupt Priority Register 0
|
||||
// 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3
|
||||
// 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2
|
||||
// 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1
|
||||
// 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0
|
||||
io_rw_32 nvic_ipr[8];
|
||||
|
||||
uint32_t _pad6[568];
|
||||
|
||||
_REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
|
||||
// CPUID Base Register
|
||||
// 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM
|
||||
// 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: +
|
||||
// 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: +
|
||||
// 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+
|
||||
// 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: +
|
||||
io_ro_32 cpuid;
|
||||
|
||||
_REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
|
||||
// Interrupt Control and State Register
|
||||
// 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI
|
||||
// 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit
|
||||
// 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit
|
||||
// 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit
|
||||
// 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit
|
||||
// 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted
|
||||
// 0x00400000 [22] ISRPENDING (0) External interrupt pending flag
|
||||
// 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority...
|
||||
// 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field
|
||||
io_rw_32 icsr;
|
||||
|
||||
_REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
|
||||
// Vector Table Offset Register
|
||||
// 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address
|
||||
io_rw_32 vtor;
|
||||
|
||||
_REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
|
||||
// Application Interrupt and Reset Control Register
|
||||
// 0xffff0000 [31:16] VECTKEY (0x0000) Register key: +
|
||||
// 0x00008000 [15] ENDIANESS (0) Data endianness implemented: +
|
||||
// 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to...
|
||||
// 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and...
|
||||
io_rw_32 aircr;
|
||||
|
||||
_REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
|
||||
// System Control Register
|
||||
// 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: +
|
||||
// 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep...
|
||||
// 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode...
|
||||
io_rw_32 scr;
|
||||
|
||||
_REG_(M0PLUS_CCR_OFFSET) // M0PLUS_CCR
|
||||
// Configuration and Control Register
|
||||
// 0x00000200 [9] STKALIGN (0) Always reads as one, indicates 8-byte stack alignment on...
|
||||
// 0x00000008 [3] UNALIGN_TRP (0) Always reads as one, indicates that all unaligned...
|
||||
io_ro_32 ccr;
|
||||
|
||||
uint32_t _pad7;
|
||||
|
||||
// (Description copied from array index 0 register M0PLUS_SHPR2 applies similarly to other array indexes)
|
||||
_REG_(M0PLUS_SHPR2_OFFSET) // M0PLUS_SHPR2
|
||||
// System Handler Priority Register 2
|
||||
// 0xc0000000 [31:30] PRI_11 (0x0) Priority of system handler 11, SVCall
|
||||
io_rw_32 shpr[2];
|
||||
|
||||
_REG_(M0PLUS_SHCSR_OFFSET) // M0PLUS_SHCSR
|
||||
// System Handler Control and State Register
|
||||
// 0x00008000 [15] SVCALLPENDED (0) Reads as 1 if SVCall is Pending
|
||||
io_rw_32 shcsr;
|
||||
|
||||
uint32_t _pad8[26];
|
||||
|
||||
_REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
|
||||
// MPU Type Register
|
||||
// 0x00ff0000 [23:16] IREGION (0x00) Instruction region
|
||||
// 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
|
||||
// 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps
|
||||
io_ro_32 mpu_type;
|
||||
|
||||
_REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
|
||||
// MPU Control Register
|
||||
// 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a...
|
||||
// 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs
|
||||
// 0x00000001 [0] ENABLE (0) Enables the MPU
|
||||
io_rw_32 mpu_ctrl;
|
||||
|
||||
_REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
|
||||
// MPU Region Number Register
|
||||
// 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and...
|
||||
io_rw_32 mpu_rnr;
|
||||
|
||||
_REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
|
||||
// MPU Region Base Address Register
|
||||
// 0xffffff00 [31:8] ADDR (0x000000) Base address of the region
|
||||
// 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the...
|
||||
// 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base...
|
||||
io_rw_32 mpu_rbar;
|
||||
|
||||
_REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
|
||||
// MPU Region Attribute and Size Register
|
||||
// 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field
|
||||
// 0x0000ff00 [15:8] SRD (0x00) Subregion Disable
|
||||
// 0x0000003e [5:1] SIZE (0x00) Indicates the region size
|
||||
// 0x00000001 [0] ENABLE (0) Enables the region
|
||||
io_rw_32 mpu_rasr;
|
||||
} m0plus_hw_t;
|
||||
|
||||
#define ppb_hw ((m0plus_hw_t *)PPB_BASE)
|
||||
static_assert(sizeof (m0plus_hw_t) == 0xeda4, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_M0PLUS_H
|
||||
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_MPU_H
|
||||
#define _HARDWARE_STRUCTS_MPU_H
|
||||
|
||||
/**
|
||||
* \file rp2040/mpu.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/m0plus.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
|
||||
// MPU Type Register
|
||||
// 0x00ff0000 [23:16] IREGION (0x00) Instruction region
|
||||
// 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
|
||||
// 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps
|
||||
io_ro_32 type;
|
||||
|
||||
_REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
|
||||
// MPU Control Register
|
||||
// 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a...
|
||||
// 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs
|
||||
// 0x00000001 [0] ENABLE (0) Enables the MPU
|
||||
io_rw_32 ctrl;
|
||||
|
||||
_REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
|
||||
// MPU Region Number Register
|
||||
// 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and...
|
||||
io_rw_32 rnr;
|
||||
|
||||
_REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
|
||||
// MPU Region Base Address Register
|
||||
// 0xffffff00 [31:8] ADDR (0x000000) Base address of the region
|
||||
// 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the...
|
||||
// 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base...
|
||||
io_rw_32 rbar;
|
||||
|
||||
_REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
|
||||
// MPU Region Attribute and Size Register
|
||||
// 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field
|
||||
// 0x0000ff00 [15:8] SRD (0x00) Subregion Disable
|
||||
// 0x0000003e [5:1] SIZE (0x00) Indicates the region size
|
||||
// 0x00000001 [0] ENABLE (0) Enables the region
|
||||
io_rw_32 rasr;
|
||||
} mpu_hw_t;
|
||||
|
||||
#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
|
||||
static_assert(sizeof (mpu_hw_t) == 0x0014, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_MPU_H
|
||||
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_NVIC_H
|
||||
#define _HARDWARE_STRUCTS_NVIC_H
|
||||
|
||||
/**
|
||||
* \file rp2040/nvic.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/m0plus.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER
|
||||
// Interrupt Set-Enable Register
|
||||
// 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits
|
||||
io_rw_32 iser;
|
||||
|
||||
uint32_t _pad0[31];
|
||||
|
||||
_REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER
|
||||
// Interrupt Clear-Enable Register
|
||||
// 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits
|
||||
io_rw_32 icer;
|
||||
|
||||
uint32_t _pad1[31];
|
||||
|
||||
_REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR
|
||||
// Interrupt Set-Pending Register
|
||||
// 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits
|
||||
io_rw_32 ispr;
|
||||
|
||||
uint32_t _pad2[31];
|
||||
|
||||
_REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR
|
||||
// Interrupt Clear-Pending Register
|
||||
// 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits
|
||||
io_rw_32 icpr;
|
||||
|
||||
uint32_t _pad3[95];
|
||||
|
||||
// (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes)
|
||||
_REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0
|
||||
// Interrupt Priority Register 0
|
||||
// 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3
|
||||
// 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2
|
||||
// 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1
|
||||
// 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0
|
||||
io_rw_32 ipr[8];
|
||||
} nvic_hw_t;
|
||||
|
||||
#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))
|
||||
static_assert(sizeof (nvic_hw_t) == 0x0320, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_NVIC_H
|
||||
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_PADS_BANK0_H
|
||||
#define _HARDWARE_STRUCTS_PADS_BANK0_H
|
||||
|
||||
/**
|
||||
* \file rp2040/pads_bank0.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/pads_bank0.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT
|
||||
// Voltage select
|
||||
// 0x00000001 [0] VOLTAGE_SELECT (0)
|
||||
io_rw_32 voltage_select;
|
||||
|
||||
// (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes)
|
||||
_REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0
|
||||
// Pad control register
|
||||
// 0x00000080 [7] OD (0) Output disable
|
||||
// 0x00000040 [6] IE (1) Input enable
|
||||
// 0x00000030 [5:4] DRIVE (0x1) Drive strength
|
||||
// 0x00000008 [3] PUE (0) Pull up enable
|
||||
// 0x00000004 [2] PDE (1) Pull down enable
|
||||
// 0x00000002 [1] SCHMITT (1) Enable schmitt trigger
|
||||
// 0x00000001 [0] SLEWFAST (0) Slew rate control
|
||||
io_rw_32 io[30];
|
||||
} pads_bank0_hw_t;
|
||||
|
||||
#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE)
|
||||
static_assert(sizeof (pads_bank0_hw_t) == 0x007c, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_PADS_BANK0_H
|
||||
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H
|
||||
#define _HARDWARE_STRUCTS_PADS_QSPI_H
|
||||
|
||||
/**
|
||||
* \file rp2040/pads_qspi.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/pads_qspi.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT
|
||||
// Voltage select
|
||||
// 0x00000001 [0] VOLTAGE_SELECT (0)
|
||||
io_rw_32 voltage_select;
|
||||
|
||||
// (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes)
|
||||
_REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK
|
||||
// Pad control register
|
||||
// 0x00000080 [7] OD (0) Output disable
|
||||
// 0x00000040 [6] IE (1) Input enable
|
||||
// 0x00000030 [5:4] DRIVE (0x1) Drive strength
|
||||
// 0x00000008 [3] PUE (0) Pull up enable
|
||||
// 0x00000004 [2] PDE (1) Pull down enable
|
||||
// 0x00000002 [1] SCHMITT (1) Enable schmitt trigger
|
||||
// 0x00000001 [0] SLEWFAST (0) Slew rate control
|
||||
io_rw_32 io[6];
|
||||
} pads_qspi_hw_t;
|
||||
|
||||
#define pads_qspi_hw ((pads_qspi_hw_t *)PADS_QSPI_BASE)
|
||||
static_assert(sizeof (pads_qspi_hw_t) == 0x001c, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_PADS_QSPI_H
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
// Support old header for compatibility (and if included, support old variable name)
|
||||
#include "hardware/structs/pads_bank0.h"
|
||||
#define padsbank0_hw pads_bank0_hw
|
||||
|
|
@ -0,0 +1,343 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_PIO_H
|
||||
#define _HARDWARE_STRUCTS_PIO_H
|
||||
|
||||
/**
|
||||
* \file rp2040/pio.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/pio.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/pio.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV
|
||||
// Clock divisor register for state machine 0 +
|
||||
// 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256)
|
||||
// 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor
|
||||
io_rw_32 clkdiv;
|
||||
|
||||
_REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL
|
||||
// Execution/behavioural settings for state machine 0
|
||||
// 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,...
|
||||
// 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is...
|
||||
// 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,...
|
||||
// 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN
|
||||
// 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable
|
||||
// 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable +
|
||||
// 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins
|
||||
// 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom
|
||||
// 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address
|
||||
// 0x00000010 [4] STATUS_SEL (0) Comparison used for the MOV x, STATUS instruction
|
||||
// 0x0000000f [3:0] STATUS_N (0x0) Comparison level for the MOV x, STATUS instruction
|
||||
io_rw_32 execctrl;
|
||||
|
||||
_REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL
|
||||
// Control behaviour of the input/output shift registers for state machine 0
|
||||
// 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and...
|
||||
// 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and...
|
||||
// 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or...
|
||||
// 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or...
|
||||
// 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right
|
||||
// 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left)
|
||||
// 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i
|
||||
// 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i
|
||||
io_rw_32 shiftctrl;
|
||||
|
||||
_REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR
|
||||
// Current instruction address of state machine 0
|
||||
// 0x0000001f [4:0] SM0_ADDR (0x00)
|
||||
io_ro_32 addr;
|
||||
|
||||
_REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR
|
||||
// Read to see the instruction currently addressed by state machine 0's program counter +
|
||||
// 0x0000ffff [15:0] SM0_INSTR (-)
|
||||
io_rw_32 instr;
|
||||
|
||||
_REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL
|
||||
// State machine pin control
|
||||
// 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction...
|
||||
// 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET
|
||||
// 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS...
|
||||
// 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of...
|
||||
// 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a...
|
||||
// 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET...
|
||||
// 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT...
|
||||
io_rw_32 pinctrl;
|
||||
} pio_sm_hw_t;
|
||||
|
||||
typedef struct {
|
||||
_REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
|
||||
// Interrupt Enable for irq0
|
||||
// 0x00000800 [11] SM3 (0)
|
||||
// 0x00000400 [10] SM2 (0)
|
||||
// 0x00000200 [9] SM1 (0)
|
||||
// 0x00000100 [8] SM0 (0)
|
||||
// 0x00000080 [7] SM3_TXNFULL (0)
|
||||
// 0x00000040 [6] SM2_TXNFULL (0)
|
||||
// 0x00000020 [5] SM1_TXNFULL (0)
|
||||
// 0x00000010 [4] SM0_TXNFULL (0)
|
||||
// 0x00000008 [3] SM3_RXNEMPTY (0)
|
||||
// 0x00000004 [2] SM2_RXNEMPTY (0)
|
||||
// 0x00000002 [1] SM1_RXNEMPTY (0)
|
||||
// 0x00000001 [0] SM0_RXNEMPTY (0)
|
||||
io_rw_32 inte;
|
||||
|
||||
_REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
|
||||
// Interrupt Force for irq0
|
||||
// 0x00000800 [11] SM3 (0)
|
||||
// 0x00000400 [10] SM2 (0)
|
||||
// 0x00000200 [9] SM1 (0)
|
||||
// 0x00000100 [8] SM0 (0)
|
||||
// 0x00000080 [7] SM3_TXNFULL (0)
|
||||
// 0x00000040 [6] SM2_TXNFULL (0)
|
||||
// 0x00000020 [5] SM1_TXNFULL (0)
|
||||
// 0x00000010 [4] SM0_TXNFULL (0)
|
||||
// 0x00000008 [3] SM3_RXNEMPTY (0)
|
||||
// 0x00000004 [2] SM2_RXNEMPTY (0)
|
||||
// 0x00000002 [1] SM1_RXNEMPTY (0)
|
||||
// 0x00000001 [0] SM0_RXNEMPTY (0)
|
||||
io_rw_32 intf;
|
||||
|
||||
_REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
|
||||
// Interrupt status after masking & forcing for irq0
|
||||
// 0x00000800 [11] SM3 (0)
|
||||
// 0x00000400 [10] SM2 (0)
|
||||
// 0x00000200 [9] SM1 (0)
|
||||
// 0x00000100 [8] SM0 (0)
|
||||
// 0x00000080 [7] SM3_TXNFULL (0)
|
||||
// 0x00000040 [6] SM2_TXNFULL (0)
|
||||
// 0x00000020 [5] SM1_TXNFULL (0)
|
||||
// 0x00000010 [4] SM0_TXNFULL (0)
|
||||
// 0x00000008 [3] SM3_RXNEMPTY (0)
|
||||
// 0x00000004 [2] SM2_RXNEMPTY (0)
|
||||
// 0x00000002 [1] SM1_RXNEMPTY (0)
|
||||
// 0x00000001 [0] SM0_RXNEMPTY (0)
|
||||
io_ro_32 ints;
|
||||
} pio_irq_ctrl_hw_t;
|
||||
|
||||
typedef struct {
|
||||
_REG_(PIO_CTRL_OFFSET) // PIO_CTRL
|
||||
// PIO control register
|
||||
// 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial...
|
||||
// 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may...
|
||||
// 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by...
|
||||
io_rw_32 ctrl;
|
||||
|
||||
_REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT
|
||||
// FIFO status register
|
||||
// 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty
|
||||
// 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full
|
||||
// 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty
|
||||
// 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full
|
||||
io_ro_32 fstat;
|
||||
|
||||
_REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG
|
||||
// FIFO debug register
|
||||
// 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a...
|
||||
// 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i
|
||||
// 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i
|
||||
// 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a...
|
||||
io_rw_32 fdebug;
|
||||
|
||||
_REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL
|
||||
// FIFO levels
|
||||
// 0xf0000000 [31:28] RX3 (0x0)
|
||||
// 0x0f000000 [27:24] TX3 (0x0)
|
||||
// 0x00f00000 [23:20] RX2 (0x0)
|
||||
// 0x000f0000 [19:16] TX2 (0x0)
|
||||
// 0x0000f000 [15:12] RX1 (0x0)
|
||||
// 0x00000f00 [11:8] TX1 (0x0)
|
||||
// 0x000000f0 [7:4] RX0 (0x0)
|
||||
// 0x0000000f [3:0] TX0 (0x0)
|
||||
io_ro_32 flevel;
|
||||
|
||||
// (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes)
|
||||
_REG_(PIO_TXF0_OFFSET) // PIO_TXF0
|
||||
// Direct write access to the TX FIFO for this state machine
|
||||
// 0xffffffff [31:0] TXF0 (0x00000000)
|
||||
io_wo_32 txf[4];
|
||||
|
||||
// (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes)
|
||||
_REG_(PIO_RXF0_OFFSET) // PIO_RXF0
|
||||
// Direct read access to the RX FIFO for this state machine
|
||||
// 0xffffffff [31:0] RXF0 (-)
|
||||
io_ro_32 rxf[4];
|
||||
|
||||
_REG_(PIO_IRQ_OFFSET) // PIO_IRQ
|
||||
// State machine IRQ flags register
|
||||
// 0x000000ff [7:0] IRQ (0x00)
|
||||
io_rw_32 irq;
|
||||
|
||||
_REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE
|
||||
// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ
|
||||
// 0x000000ff [7:0] IRQ_FORCE (0x00)
|
||||
io_wo_32 irq_force;
|
||||
|
||||
_REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS
|
||||
// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities
|
||||
// 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000)
|
||||
io_rw_32 input_sync_bypass;
|
||||
|
||||
_REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT
|
||||
// Read to sample the pad output values PIO is currently driving to the GPIOs
|
||||
// 0xffffffff [31:0] DBG_PADOUT (0x00000000)
|
||||
io_ro_32 dbg_padout;
|
||||
|
||||
_REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE
|
||||
// Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs
|
||||
// 0xffffffff [31:0] DBG_PADOE (0x00000000)
|
||||
io_ro_32 dbg_padoe;
|
||||
|
||||
_REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO
|
||||
// The PIO hardware has some free parameters that may vary between chip products
|
||||
// 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of...
|
||||
// 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with
|
||||
// 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words
|
||||
io_ro_32 dbg_cfginfo;
|
||||
|
||||
// (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes)
|
||||
_REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0
|
||||
// Write-only access to instruction memory location 0
|
||||
// 0x0000ffff [15:0] INSTR_MEM0 (0x0000)
|
||||
io_wo_32 instr_mem[32];
|
||||
|
||||
pio_sm_hw_t sm[4];
|
||||
|
||||
_REG_(PIO_INTR_OFFSET) // PIO_INTR
|
||||
// Raw Interrupts
|
||||
// 0x00000800 [11] SM3 (0)
|
||||
// 0x00000400 [10] SM2 (0)
|
||||
// 0x00000200 [9] SM1 (0)
|
||||
// 0x00000100 [8] SM0 (0)
|
||||
// 0x00000080 [7] SM3_TXNFULL (0)
|
||||
// 0x00000040 [6] SM2_TXNFULL (0)
|
||||
// 0x00000020 [5] SM1_TXNFULL (0)
|
||||
// 0x00000010 [4] SM0_TXNFULL (0)
|
||||
// 0x00000008 [3] SM3_RXNEMPTY (0)
|
||||
// 0x00000004 [2] SM2_RXNEMPTY (0)
|
||||
// 0x00000002 [1] SM1_RXNEMPTY (0)
|
||||
// 0x00000001 [0] SM0_RXNEMPTY (0)
|
||||
io_ro_32 intr;
|
||||
|
||||
union {
|
||||
struct {
|
||||
_REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
|
||||
// Interrupt Enable for irq0
|
||||
// 0x00000800 [11] SM3 (0)
|
||||
// 0x00000400 [10] SM2 (0)
|
||||
// 0x00000200 [9] SM1 (0)
|
||||
// 0x00000100 [8] SM0 (0)
|
||||
// 0x00000080 [7] SM3_TXNFULL (0)
|
||||
// 0x00000040 [6] SM2_TXNFULL (0)
|
||||
// 0x00000020 [5] SM1_TXNFULL (0)
|
||||
// 0x00000010 [4] SM0_TXNFULL (0)
|
||||
// 0x00000008 [3] SM3_RXNEMPTY (0)
|
||||
// 0x00000004 [2] SM2_RXNEMPTY (0)
|
||||
// 0x00000002 [1] SM1_RXNEMPTY (0)
|
||||
// 0x00000001 [0] SM0_RXNEMPTY (0)
|
||||
io_rw_32 inte0;
|
||||
|
||||
_REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
|
||||
// Interrupt Force for irq0
|
||||
// 0x00000800 [11] SM3 (0)
|
||||
// 0x00000400 [10] SM2 (0)
|
||||
// 0x00000200 [9] SM1 (0)
|
||||
// 0x00000100 [8] SM0 (0)
|
||||
// 0x00000080 [7] SM3_TXNFULL (0)
|
||||
// 0x00000040 [6] SM2_TXNFULL (0)
|
||||
// 0x00000020 [5] SM1_TXNFULL (0)
|
||||
// 0x00000010 [4] SM0_TXNFULL (0)
|
||||
// 0x00000008 [3] SM3_RXNEMPTY (0)
|
||||
// 0x00000004 [2] SM2_RXNEMPTY (0)
|
||||
// 0x00000002 [1] SM1_RXNEMPTY (0)
|
||||
// 0x00000001 [0] SM0_RXNEMPTY (0)
|
||||
io_rw_32 intf0;
|
||||
|
||||
_REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
|
||||
// Interrupt status after masking & forcing for irq0
|
||||
// 0x00000800 [11] SM3 (0)
|
||||
// 0x00000400 [10] SM2 (0)
|
||||
// 0x00000200 [9] SM1 (0)
|
||||
// 0x00000100 [8] SM0 (0)
|
||||
// 0x00000080 [7] SM3_TXNFULL (0)
|
||||
// 0x00000040 [6] SM2_TXNFULL (0)
|
||||
// 0x00000020 [5] SM1_TXNFULL (0)
|
||||
// 0x00000010 [4] SM0_TXNFULL (0)
|
||||
// 0x00000008 [3] SM3_RXNEMPTY (0)
|
||||
// 0x00000004 [2] SM2_RXNEMPTY (0)
|
||||
// 0x00000002 [1] SM1_RXNEMPTY (0)
|
||||
// 0x00000001 [0] SM0_RXNEMPTY (0)
|
||||
io_ro_32 ints0;
|
||||
|
||||
_REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE
|
||||
// Interrupt Enable for irq1
|
||||
// 0x00000800 [11] SM3 (0)
|
||||
// 0x00000400 [10] SM2 (0)
|
||||
// 0x00000200 [9] SM1 (0)
|
||||
// 0x00000100 [8] SM0 (0)
|
||||
// 0x00000080 [7] SM3_TXNFULL (0)
|
||||
// 0x00000040 [6] SM2_TXNFULL (0)
|
||||
// 0x00000020 [5] SM1_TXNFULL (0)
|
||||
// 0x00000010 [4] SM0_TXNFULL (0)
|
||||
// 0x00000008 [3] SM3_RXNEMPTY (0)
|
||||
// 0x00000004 [2] SM2_RXNEMPTY (0)
|
||||
// 0x00000002 [1] SM1_RXNEMPTY (0)
|
||||
// 0x00000001 [0] SM0_RXNEMPTY (0)
|
||||
io_rw_32 inte1;
|
||||
|
||||
_REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF
|
||||
// Interrupt Force for irq1
|
||||
// 0x00000800 [11] SM3 (0)
|
||||
// 0x00000400 [10] SM2 (0)
|
||||
// 0x00000200 [9] SM1 (0)
|
||||
// 0x00000100 [8] SM0 (0)
|
||||
// 0x00000080 [7] SM3_TXNFULL (0)
|
||||
// 0x00000040 [6] SM2_TXNFULL (0)
|
||||
// 0x00000020 [5] SM1_TXNFULL (0)
|
||||
// 0x00000010 [4] SM0_TXNFULL (0)
|
||||
// 0x00000008 [3] SM3_RXNEMPTY (0)
|
||||
// 0x00000004 [2] SM2_RXNEMPTY (0)
|
||||
// 0x00000002 [1] SM1_RXNEMPTY (0)
|
||||
// 0x00000001 [0] SM0_RXNEMPTY (0)
|
||||
io_rw_32 intf1;
|
||||
|
||||
_REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS
|
||||
// Interrupt status after masking & forcing for irq1
|
||||
// 0x00000800 [11] SM3 (0)
|
||||
// 0x00000400 [10] SM2 (0)
|
||||
// 0x00000200 [9] SM1 (0)
|
||||
// 0x00000100 [8] SM0 (0)
|
||||
// 0x00000080 [7] SM3_TXNFULL (0)
|
||||
// 0x00000040 [6] SM2_TXNFULL (0)
|
||||
// 0x00000020 [5] SM1_TXNFULL (0)
|
||||
// 0x00000010 [4] SM0_TXNFULL (0)
|
||||
// 0x00000008 [3] SM3_RXNEMPTY (0)
|
||||
// 0x00000004 [2] SM2_RXNEMPTY (0)
|
||||
// 0x00000002 [1] SM1_RXNEMPTY (0)
|
||||
// 0x00000001 [0] SM0_RXNEMPTY (0)
|
||||
io_ro_32 ints1;
|
||||
};
|
||||
pio_irq_ctrl_hw_t irq_ctrl[2];
|
||||
};
|
||||
} pio_hw_t;
|
||||
|
||||
#define pio0_hw ((pio_hw_t *)PIO0_BASE)
|
||||
#define pio1_hw ((pio_hw_t *)PIO1_BASE)
|
||||
static_assert(sizeof (pio_hw_t) == 0x0144, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_PIO_H
|
||||
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_PLL_H
|
||||
#define _HARDWARE_STRUCTS_PLL_H
|
||||
|
||||
/**
|
||||
* \file rp2040/pll.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/pll.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/pll.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
/// \tag::pll_hw[]
|
||||
typedef struct {
|
||||
_REG_(PLL_CS_OFFSET) // PLL_CS
|
||||
// Control and Status
|
||||
// 0x80000000 [31] LOCK (0) PLL is locked
|
||||
// 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the...
|
||||
// 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock
|
||||
io_rw_32 cs;
|
||||
|
||||
_REG_(PLL_PWR_OFFSET) // PLL_PWR
|
||||
// Controls the PLL power modes
|
||||
// 0x00000020 [5] VCOPD (1) PLL VCO powerdown +
|
||||
// 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown +
|
||||
// 0x00000004 [2] DSMPD (1) PLL DSM powerdown +
|
||||
// 0x00000001 [0] PD (1) PLL powerdown +
|
||||
io_rw_32 pwr;
|
||||
|
||||
_REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT
|
||||
// Feedback divisor
|
||||
// 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints
|
||||
io_rw_32 fbdiv_int;
|
||||
|
||||
_REG_(PLL_PRIM_OFFSET) // PLL_PRIM
|
||||
// Controls the PLL post dividers for the primary output
|
||||
// 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7
|
||||
// 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7
|
||||
io_rw_32 prim;
|
||||
} pll_hw_t;
|
||||
/// \end::pll_hw[]
|
||||
|
||||
#define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE)
|
||||
#define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE)
|
||||
static_assert(sizeof (pll_hw_t) == 0x0010, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_PLL_H
|
||||
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_PSM_H
|
||||
#define _HARDWARE_STRUCTS_PSM_H
|
||||
|
||||
/**
|
||||
* \file rp2040/psm.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/psm.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_psm
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/psm.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON
|
||||
// Force block out of reset (i
|
||||
// 0x00010000 [16] PROC1 (0)
|
||||
// 0x00008000 [15] PROC0 (0)
|
||||
// 0x00004000 [14] SIO (0)
|
||||
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
|
||||
// 0x00001000 [12] XIP (0)
|
||||
// 0x00000800 [11] SRAM5 (0)
|
||||
// 0x00000400 [10] SRAM4 (0)
|
||||
// 0x00000200 [9] SRAM3 (0)
|
||||
// 0x00000100 [8] SRAM2 (0)
|
||||
// 0x00000080 [7] SRAM1 (0)
|
||||
// 0x00000040 [6] SRAM0 (0)
|
||||
// 0x00000020 [5] ROM (0)
|
||||
// 0x00000010 [4] BUSFABRIC (0)
|
||||
// 0x00000008 [3] RESETS (0)
|
||||
// 0x00000004 [2] CLOCKS (0)
|
||||
// 0x00000002 [1] XOSC (0)
|
||||
// 0x00000001 [0] ROSC (0)
|
||||
io_rw_32 frce_on;
|
||||
|
||||
_REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF
|
||||
// Force into reset (i
|
||||
// 0x00010000 [16] PROC1 (0)
|
||||
// 0x00008000 [15] PROC0 (0)
|
||||
// 0x00004000 [14] SIO (0)
|
||||
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
|
||||
// 0x00001000 [12] XIP (0)
|
||||
// 0x00000800 [11] SRAM5 (0)
|
||||
// 0x00000400 [10] SRAM4 (0)
|
||||
// 0x00000200 [9] SRAM3 (0)
|
||||
// 0x00000100 [8] SRAM2 (0)
|
||||
// 0x00000080 [7] SRAM1 (0)
|
||||
// 0x00000040 [6] SRAM0 (0)
|
||||
// 0x00000020 [5] ROM (0)
|
||||
// 0x00000010 [4] BUSFABRIC (0)
|
||||
// 0x00000008 [3] RESETS (0)
|
||||
// 0x00000004 [2] CLOCKS (0)
|
||||
// 0x00000002 [1] XOSC (0)
|
||||
// 0x00000001 [0] ROSC (0)
|
||||
io_rw_32 frce_off;
|
||||
|
||||
_REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL
|
||||
// Set to 1 if this peripheral should be reset when the watchdog fires
|
||||
// 0x00010000 [16] PROC1 (0)
|
||||
// 0x00008000 [15] PROC0 (0)
|
||||
// 0x00004000 [14] SIO (0)
|
||||
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
|
||||
// 0x00001000 [12] XIP (0)
|
||||
// 0x00000800 [11] SRAM5 (0)
|
||||
// 0x00000400 [10] SRAM4 (0)
|
||||
// 0x00000200 [9] SRAM3 (0)
|
||||
// 0x00000100 [8] SRAM2 (0)
|
||||
// 0x00000080 [7] SRAM1 (0)
|
||||
// 0x00000040 [6] SRAM0 (0)
|
||||
// 0x00000020 [5] ROM (0)
|
||||
// 0x00000010 [4] BUSFABRIC (0)
|
||||
// 0x00000008 [3] RESETS (0)
|
||||
// 0x00000004 [2] CLOCKS (0)
|
||||
// 0x00000002 [1] XOSC (0)
|
||||
// 0x00000001 [0] ROSC (0)
|
||||
io_rw_32 wdsel;
|
||||
|
||||
_REG_(PSM_DONE_OFFSET) // PSM_DONE
|
||||
// Indicates the peripheral's registers are ready to access
|
||||
// 0x00010000 [16] PROC1 (0)
|
||||
// 0x00008000 [15] PROC0 (0)
|
||||
// 0x00004000 [14] SIO (0)
|
||||
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
|
||||
// 0x00001000 [12] XIP (0)
|
||||
// 0x00000800 [11] SRAM5 (0)
|
||||
// 0x00000400 [10] SRAM4 (0)
|
||||
// 0x00000200 [9] SRAM3 (0)
|
||||
// 0x00000100 [8] SRAM2 (0)
|
||||
// 0x00000080 [7] SRAM1 (0)
|
||||
// 0x00000040 [6] SRAM0 (0)
|
||||
// 0x00000020 [5] ROM (0)
|
||||
// 0x00000010 [4] BUSFABRIC (0)
|
||||
// 0x00000008 [3] RESETS (0)
|
||||
// 0x00000004 [2] CLOCKS (0)
|
||||
// 0x00000002 [1] XOSC (0)
|
||||
// 0x00000001 [0] ROSC (0)
|
||||
io_ro_32 done;
|
||||
} psm_hw_t;
|
||||
|
||||
#define psm_hw ((psm_hw_t *)PSM_BASE)
|
||||
static_assert(sizeof (psm_hw_t) == 0x0010, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_PSM_H
|
||||
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_PWM_H
|
||||
#define _HARDWARE_STRUCTS_PWM_H
|
||||
|
||||
/**
|
||||
* \file rp2040/pwm.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/pwm.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR
|
||||
// Control and status register
|
||||
// 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running
|
||||
// 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running
|
||||
// 0x00000030 [5:4] DIVMODE (0x0)
|
||||
// 0x00000008 [3] B_INV (0) Invert output B
|
||||
// 0x00000004 [2] A_INV (0) Invert output A
|
||||
// 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation
|
||||
// 0x00000001 [0] EN (0) Enable the PWM channel
|
||||
io_rw_32 csr;
|
||||
|
||||
_REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV
|
||||
// INT and FRAC form a fixed-point fractional number
|
||||
// 0x00000ff0 [11:4] INT (0x01)
|
||||
// 0x0000000f [3:0] FRAC (0x0)
|
||||
io_rw_32 div;
|
||||
|
||||
_REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR
|
||||
// Direct access to the PWM counter
|
||||
// 0x0000ffff [15:0] CH0_CTR (0x0000)
|
||||
io_rw_32 ctr;
|
||||
|
||||
_REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC
|
||||
// Counter compare values
|
||||
// 0xffff0000 [31:16] B (0x0000)
|
||||
// 0x0000ffff [15:0] A (0x0000)
|
||||
io_rw_32 cc;
|
||||
|
||||
_REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP
|
||||
// Counter wrap value
|
||||
// 0x0000ffff [15:0] CH0_TOP (0xffff)
|
||||
io_rw_32 top;
|
||||
} pwm_slice_hw_t;
|
||||
|
||||
typedef struct {
|
||||
_REG_(PWM_INTE_OFFSET) // PWM_INTE
|
||||
// Interrupt Enable
|
||||
// 0x00000080 [7] CH7 (0)
|
||||
// 0x00000040 [6] CH6 (0)
|
||||
// 0x00000020 [5] CH5 (0)
|
||||
// 0x00000010 [4] CH4 (0)
|
||||
// 0x00000008 [3] CH3 (0)
|
||||
// 0x00000004 [2] CH2 (0)
|
||||
// 0x00000002 [1] CH1 (0)
|
||||
// 0x00000001 [0] CH0 (0)
|
||||
io_rw_32 inte;
|
||||
|
||||
_REG_(PWM_INTF_OFFSET) // PWM_INTF
|
||||
// Interrupt Force
|
||||
// 0x00000080 [7] CH7 (0)
|
||||
// 0x00000040 [6] CH6 (0)
|
||||
// 0x00000020 [5] CH5 (0)
|
||||
// 0x00000010 [4] CH4 (0)
|
||||
// 0x00000008 [3] CH3 (0)
|
||||
// 0x00000004 [2] CH2 (0)
|
||||
// 0x00000002 [1] CH1 (0)
|
||||
// 0x00000001 [0] CH0 (0)
|
||||
io_rw_32 intf;
|
||||
|
||||
_REG_(PWM_INTS_OFFSET) // PWM_INTS
|
||||
// Interrupt status after masking & forcing
|
||||
// 0x00000080 [7] CH7 (0)
|
||||
// 0x00000040 [6] CH6 (0)
|
||||
// 0x00000020 [5] CH5 (0)
|
||||
// 0x00000010 [4] CH4 (0)
|
||||
// 0x00000008 [3] CH3 (0)
|
||||
// 0x00000004 [2] CH2 (0)
|
||||
// 0x00000002 [1] CH1 (0)
|
||||
// 0x00000001 [0] CH0 (0)
|
||||
io_ro_32 ints;
|
||||
} pwm_irq_ctrl_hw_t;
|
||||
|
||||
typedef struct {
|
||||
pwm_slice_hw_t slice[8];
|
||||
|
||||
_REG_(PWM_EN_OFFSET) // PWM_EN
|
||||
// This register aliases the CSR_EN bits for all channels
|
||||
// 0x00000080 [7] CH7 (0)
|
||||
// 0x00000040 [6] CH6 (0)
|
||||
// 0x00000020 [5] CH5 (0)
|
||||
// 0x00000010 [4] CH4 (0)
|
||||
// 0x00000008 [3] CH3 (0)
|
||||
// 0x00000004 [2] CH2 (0)
|
||||
// 0x00000002 [1] CH1 (0)
|
||||
// 0x00000001 [0] CH0 (0)
|
||||
io_rw_32 en;
|
||||
|
||||
_REG_(PWM_INTR_OFFSET) // PWM_INTR
|
||||
// Raw Interrupts
|
||||
// 0x00000080 [7] CH7 (0)
|
||||
// 0x00000040 [6] CH6 (0)
|
||||
// 0x00000020 [5] CH5 (0)
|
||||
// 0x00000010 [4] CH4 (0)
|
||||
// 0x00000008 [3] CH3 (0)
|
||||
// 0x00000004 [2] CH2 (0)
|
||||
// 0x00000002 [1] CH1 (0)
|
||||
// 0x00000001 [0] CH0 (0)
|
||||
io_rw_32 intr;
|
||||
|
||||
union {
|
||||
struct {
|
||||
_REG_(PWM_INTE_OFFSET) // PWM_INTE
|
||||
// Interrupt Enable
|
||||
// 0x00000080 [7] CH7 (0)
|
||||
// 0x00000040 [6] CH6 (0)
|
||||
// 0x00000020 [5] CH5 (0)
|
||||
// 0x00000010 [4] CH4 (0)
|
||||
// 0x00000008 [3] CH3 (0)
|
||||
// 0x00000004 [2] CH2 (0)
|
||||
// 0x00000002 [1] CH1 (0)
|
||||
// 0x00000001 [0] CH0 (0)
|
||||
io_rw_32 inte;
|
||||
|
||||
_REG_(PWM_INTF_OFFSET) // PWM_INTF
|
||||
// Interrupt Force
|
||||
// 0x00000080 [7] CH7 (0)
|
||||
// 0x00000040 [6] CH6 (0)
|
||||
// 0x00000020 [5] CH5 (0)
|
||||
// 0x00000010 [4] CH4 (0)
|
||||
// 0x00000008 [3] CH3 (0)
|
||||
// 0x00000004 [2] CH2 (0)
|
||||
// 0x00000002 [1] CH1 (0)
|
||||
// 0x00000001 [0] CH0 (0)
|
||||
io_rw_32 intf;
|
||||
|
||||
_REG_(PWM_INTS_OFFSET) // PWM_INTS
|
||||
// Interrupt status after masking & forcing
|
||||
// 0x00000080 [7] CH7 (0)
|
||||
// 0x00000040 [6] CH6 (0)
|
||||
// 0x00000020 [5] CH5 (0)
|
||||
// 0x00000010 [4] CH4 (0)
|
||||
// 0x00000008 [3] CH3 (0)
|
||||
// 0x00000004 [2] CH2 (0)
|
||||
// 0x00000002 [1] CH1 (0)
|
||||
// 0x00000001 [0] CH0 (0)
|
||||
io_rw_32 ints;
|
||||
};
|
||||
pwm_irq_ctrl_hw_t irq_ctrl[1];
|
||||
};
|
||||
} pwm_hw_t;
|
||||
|
||||
#define pwm_hw ((pwm_hw_t *)PWM_BASE)
|
||||
static_assert(sizeof (pwm_hw_t) == 0x00b4, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_PWM_H
|
||||
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_RESETS_H
|
||||
#define _HARDWARE_STRUCTS_RESETS_H
|
||||
|
||||
/**
|
||||
* \file rp2040/resets.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/resets.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/resets.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
/** \brief Resettable component numbers on RP2040 (used as typedef \ref reset_num_t)
|
||||
* \ingroup hardware_resets
|
||||
*/
|
||||
typedef enum reset_num_rp2040 {
|
||||
RESET_ADC = 0, ///< Select ADC to be reset
|
||||
RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset
|
||||
RESET_DMA = 2, ///< Select DMA to be reset
|
||||
RESET_I2C0 = 3, ///< Select I2C0 to be reset
|
||||
RESET_I2C1 = 4, ///< Select I2C1 to be reset
|
||||
RESET_IO_BANK0 = 5, ///< Select IO_BANK0 to be reset
|
||||
RESET_IO_QSPI = 6, ///< Select IO_QSPI to be reset
|
||||
RESET_JTAG = 7, ///< Select JTAG to be reset
|
||||
RESET_PADS_BANK0 = 8, ///< Select PADS_BANK0 to be reset
|
||||
RESET_PADS_QSPI = 9, ///< Select PADS_QSPI to be reset
|
||||
RESET_PIO0 = 10, ///< Select PIO0 to be reset
|
||||
RESET_PIO1 = 11, ///< Select PIO1 to be reset
|
||||
RESET_PLL_SYS = 12, ///< Select PLL_SYS to be reset
|
||||
RESET_PLL_USB = 13, ///< Select PLL_USB to be reset
|
||||
RESET_PWM = 14, ///< Select PWM to be reset
|
||||
RESET_RTC = 15, ///< Select RTC to be reset
|
||||
RESET_SPI0 = 16, ///< Select SPI0 to be reset
|
||||
RESET_SPI1 = 17, ///< Select SPI1 to be reset
|
||||
RESET_SYSCFG = 18, ///< Select SYSCFG to be reset
|
||||
RESET_SYSINFO = 19, ///< Select SYSINFO to be reset
|
||||
RESET_TBMAN = 20, ///< Select TBMAN to be reset
|
||||
RESET_TIMER = 21, ///< Select TIMER to be reset
|
||||
RESET_UART0 = 22, ///< Select UART0 to be reset
|
||||
RESET_UART1 = 23, ///< Select UART1 to be reset
|
||||
RESET_USBCTRL = 24, ///< Select USBCTRL to be reset
|
||||
RESET_COUNT
|
||||
} reset_num_t;
|
||||
|
||||
/// \tag::resets_hw[]
|
||||
typedef struct {
|
||||
_REG_(RESETS_RESET_OFFSET) // RESETS_RESET
|
||||
// Reset control.
|
||||
// 0x01000000 [24] USBCTRL (1)
|
||||
// 0x00800000 [23] UART1 (1)
|
||||
// 0x00400000 [22] UART0 (1)
|
||||
// 0x00200000 [21] TIMER (1)
|
||||
// 0x00100000 [20] TBMAN (1)
|
||||
// 0x00080000 [19] SYSINFO (1)
|
||||
// 0x00040000 [18] SYSCFG (1)
|
||||
// 0x00020000 [17] SPI1 (1)
|
||||
// 0x00010000 [16] SPI0 (1)
|
||||
// 0x00008000 [15] RTC (1)
|
||||
// 0x00004000 [14] PWM (1)
|
||||
// 0x00002000 [13] PLL_USB (1)
|
||||
// 0x00001000 [12] PLL_SYS (1)
|
||||
// 0x00000800 [11] PIO1 (1)
|
||||
// 0x00000400 [10] PIO0 (1)
|
||||
// 0x00000200 [9] PADS_QSPI (1)
|
||||
// 0x00000100 [8] PADS_BANK0 (1)
|
||||
// 0x00000080 [7] JTAG (1)
|
||||
// 0x00000040 [6] IO_QSPI (1)
|
||||
// 0x00000020 [5] IO_BANK0 (1)
|
||||
// 0x00000010 [4] I2C1 (1)
|
||||
// 0x00000008 [3] I2C0 (1)
|
||||
// 0x00000004 [2] DMA (1)
|
||||
// 0x00000002 [1] BUSCTRL (1)
|
||||
// 0x00000001 [0] ADC (1)
|
||||
io_rw_32 reset;
|
||||
|
||||
_REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL
|
||||
// Watchdog select.
|
||||
// 0x01000000 [24] USBCTRL (0)
|
||||
// 0x00800000 [23] UART1 (0)
|
||||
// 0x00400000 [22] UART0 (0)
|
||||
// 0x00200000 [21] TIMER (0)
|
||||
// 0x00100000 [20] TBMAN (0)
|
||||
// 0x00080000 [19] SYSINFO (0)
|
||||
// 0x00040000 [18] SYSCFG (0)
|
||||
// 0x00020000 [17] SPI1 (0)
|
||||
// 0x00010000 [16] SPI0 (0)
|
||||
// 0x00008000 [15] RTC (0)
|
||||
// 0x00004000 [14] PWM (0)
|
||||
// 0x00002000 [13] PLL_USB (0)
|
||||
// 0x00001000 [12] PLL_SYS (0)
|
||||
// 0x00000800 [11] PIO1 (0)
|
||||
// 0x00000400 [10] PIO0 (0)
|
||||
// 0x00000200 [9] PADS_QSPI (0)
|
||||
// 0x00000100 [8] PADS_BANK0 (0)
|
||||
// 0x00000080 [7] JTAG (0)
|
||||
// 0x00000040 [6] IO_QSPI (0)
|
||||
// 0x00000020 [5] IO_BANK0 (0)
|
||||
// 0x00000010 [4] I2C1 (0)
|
||||
// 0x00000008 [3] I2C0 (0)
|
||||
// 0x00000004 [2] DMA (0)
|
||||
// 0x00000002 [1] BUSCTRL (0)
|
||||
// 0x00000001 [0] ADC (0)
|
||||
io_rw_32 wdsel;
|
||||
|
||||
_REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE
|
||||
// Reset done.
|
||||
// 0x01000000 [24] USBCTRL (0)
|
||||
// 0x00800000 [23] UART1 (0)
|
||||
// 0x00400000 [22] UART0 (0)
|
||||
// 0x00200000 [21] TIMER (0)
|
||||
// 0x00100000 [20] TBMAN (0)
|
||||
// 0x00080000 [19] SYSINFO (0)
|
||||
// 0x00040000 [18] SYSCFG (0)
|
||||
// 0x00020000 [17] SPI1 (0)
|
||||
// 0x00010000 [16] SPI0 (0)
|
||||
// 0x00008000 [15] RTC (0)
|
||||
// 0x00004000 [14] PWM (0)
|
||||
// 0x00002000 [13] PLL_USB (0)
|
||||
// 0x00001000 [12] PLL_SYS (0)
|
||||
// 0x00000800 [11] PIO1 (0)
|
||||
// 0x00000400 [10] PIO0 (0)
|
||||
// 0x00000200 [9] PADS_QSPI (0)
|
||||
// 0x00000100 [8] PADS_BANK0 (0)
|
||||
// 0x00000080 [7] JTAG (0)
|
||||
// 0x00000040 [6] IO_QSPI (0)
|
||||
// 0x00000020 [5] IO_BANK0 (0)
|
||||
// 0x00000010 [4] I2C1 (0)
|
||||
// 0x00000008 [3] I2C0 (0)
|
||||
// 0x00000004 [2] DMA (0)
|
||||
// 0x00000002 [1] BUSCTRL (0)
|
||||
// 0x00000001 [0] ADC (0)
|
||||
io_ro_32 reset_done;
|
||||
} resets_hw_t;
|
||||
/// \end::resets_hw[]
|
||||
|
||||
#define resets_hw ((resets_hw_t *)RESETS_BASE)
|
||||
static_assert(sizeof (resets_hw_t) == 0x000c, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_RESETS_H
|
||||
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_ROSC_H
|
||||
#define _HARDWARE_STRUCTS_ROSC_H
|
||||
|
||||
/**
|
||||
* \file rp2040/rosc.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/rosc.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
|
||||
// Ring Oscillator control
|
||||
// 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE +
|
||||
// 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring +
|
||||
io_rw_32 ctrl;
|
||||
|
||||
_REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
|
||||
// Ring Oscillator frequency control A
|
||||
// 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
|
||||
// 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength
|
||||
// 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength
|
||||
// 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength
|
||||
// 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength
|
||||
io_rw_32 freqa;
|
||||
|
||||
_REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
|
||||
// Ring Oscillator frequency control B
|
||||
// 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
|
||||
// 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength
|
||||
// 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength
|
||||
// 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength
|
||||
// 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength
|
||||
io_rw_32 freqb;
|
||||
|
||||
_REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
|
||||
// Ring Oscillator pause control
|
||||
// 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC +
|
||||
io_rw_32 dormant;
|
||||
|
||||
_REG_(ROSC_DIV_OFFSET) // ROSC_DIV
|
||||
// Controls the output divider
|
||||
// 0x00000fff [11:0] DIV (-) set to 0xaa0 + div where +
|
||||
io_rw_32 div;
|
||||
|
||||
_REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
|
||||
// Controls the phase shifted output
|
||||
// 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa +
|
||||
// 0x00000008 [3] ENABLE (1) enable the phase-shifted output +
|
||||
// 0x00000004 [2] FLIP (0) invert the phase-shifted output +
|
||||
// 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks +
|
||||
io_rw_32 phase;
|
||||
|
||||
_REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
|
||||
// Ring Oscillator Status
|
||||
// 0x80000000 [31] STABLE (0) Oscillator is running and stable
|
||||
// 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or...
|
||||
// 0x00010000 [16] DIV_RUNNING (-) post-divider is running +
|
||||
// 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable +
|
||||
io_rw_32 status;
|
||||
|
||||
_REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
|
||||
// Returns a 1 bit random value
|
||||
// 0x00000001 [0] RANDOMBIT (1)
|
||||
io_ro_32 randombit;
|
||||
|
||||
_REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
|
||||
// A down counter running at the ROSC frequency which counts to zero and stops.
|
||||
// 0x000000ff [7:0] COUNT (0x00)
|
||||
io_rw_32 count;
|
||||
} rosc_hw_t;
|
||||
|
||||
#define rosc_hw ((rosc_hw_t *)ROSC_BASE)
|
||||
static_assert(sizeof (rosc_hw_t) == 0x0024, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_ROSC_H
|
||||
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_RTC_H
|
||||
#define _HARDWARE_STRUCTS_RTC_H
|
||||
|
||||
/**
|
||||
* \file rp2040/rtc.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/rtc.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/rtc.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1
|
||||
// Divider minus 1 for the 1 second counter
|
||||
// 0x0000ffff [15:0] CLKDIV_M1 (0x0000)
|
||||
io_rw_32 clkdiv_m1;
|
||||
|
||||
_REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0
|
||||
// RTC setup register 0
|
||||
// 0x00fff000 [23:12] YEAR (0x000) Year
|
||||
// 0x00000f00 [11:8] MONTH (0x0) Month (1
|
||||
// 0x0000001f [4:0] DAY (0x00) Day of the month (1
|
||||
io_rw_32 setup_0;
|
||||
|
||||
_REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1
|
||||
// RTC setup register 1
|
||||
// 0x07000000 [26:24] DOTW (0x0) Day of the week: 1-Monday
|
||||
// 0x001f0000 [20:16] HOUR (0x00) Hours
|
||||
// 0x00003f00 [13:8] MIN (0x00) Minutes
|
||||
// 0x0000003f [5:0] SEC (0x00) Seconds
|
||||
io_rw_32 setup_1;
|
||||
|
||||
_REG_(RTC_CTRL_OFFSET) // RTC_CTRL
|
||||
// RTC Control and status
|
||||
// 0x00000100 [8] FORCE_NOTLEAPYEAR (0) If set, leapyear is forced off
|
||||
// 0x00000010 [4] LOAD (0) Load RTC
|
||||
// 0x00000002 [1] RTC_ACTIVE (-) RTC enabled (running)
|
||||
// 0x00000001 [0] RTC_ENABLE (0) Enable RTC
|
||||
io_rw_32 ctrl;
|
||||
|
||||
_REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0
|
||||
// Interrupt setup register 0
|
||||
// 0x20000000 [29] MATCH_ACTIVE (-)
|
||||
// 0x10000000 [28] MATCH_ENA (0) Global match enable
|
||||
// 0x04000000 [26] YEAR_ENA (0) Enable year matching
|
||||
// 0x02000000 [25] MONTH_ENA (0) Enable month matching
|
||||
// 0x01000000 [24] DAY_ENA (0) Enable day matching
|
||||
// 0x00fff000 [23:12] YEAR (0x000) Year
|
||||
// 0x00000f00 [11:8] MONTH (0x0) Month (1
|
||||
// 0x0000001f [4:0] DAY (0x00) Day of the month (1
|
||||
io_rw_32 irq_setup_0;
|
||||
|
||||
_REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1
|
||||
// Interrupt setup register 1
|
||||
// 0x80000000 [31] DOTW_ENA (0) Enable day of the week matching
|
||||
// 0x40000000 [30] HOUR_ENA (0) Enable hour matching
|
||||
// 0x20000000 [29] MIN_ENA (0) Enable minute matching
|
||||
// 0x10000000 [28] SEC_ENA (0) Enable second matching
|
||||
// 0x07000000 [26:24] DOTW (0x0) Day of the week
|
||||
// 0x001f0000 [20:16] HOUR (0x00) Hours
|
||||
// 0x00003f00 [13:8] MIN (0x00) Minutes
|
||||
// 0x0000003f [5:0] SEC (0x00) Seconds
|
||||
io_rw_32 irq_setup_1;
|
||||
|
||||
_REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1
|
||||
// RTC register 1
|
||||
// 0x00fff000 [23:12] YEAR (-) Year
|
||||
// 0x00000f00 [11:8] MONTH (-) Month (1
|
||||
// 0x0000001f [4:0] DAY (-) Day of the month (1
|
||||
io_ro_32 rtc_1;
|
||||
|
||||
_REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0
|
||||
// RTC register 0 +
|
||||
// 0x07000000 [26:24] DOTW (-) Day of the week
|
||||
// 0x001f0000 [20:16] HOUR (-) Hours
|
||||
// 0x00003f00 [13:8] MIN (-) Minutes
|
||||
// 0x0000003f [5:0] SEC (-) Seconds
|
||||
io_ro_32 rtc_0;
|
||||
|
||||
_REG_(RTC_INTR_OFFSET) // RTC_INTR
|
||||
// Raw Interrupts
|
||||
// 0x00000001 [0] RTC (0)
|
||||
io_ro_32 intr;
|
||||
|
||||
_REG_(RTC_INTE_OFFSET) // RTC_INTE
|
||||
// Interrupt Enable
|
||||
// 0x00000001 [0] RTC (0)
|
||||
io_rw_32 inte;
|
||||
|
||||
_REG_(RTC_INTF_OFFSET) // RTC_INTF
|
||||
// Interrupt Force
|
||||
// 0x00000001 [0] RTC (0)
|
||||
io_rw_32 intf;
|
||||
|
||||
_REG_(RTC_INTS_OFFSET) // RTC_INTS
|
||||
// Interrupt status after masking & forcing
|
||||
// 0x00000001 [0] RTC (0)
|
||||
io_ro_32 ints;
|
||||
} rtc_hw_t;
|
||||
|
||||
#define rtc_hw ((rtc_hw_t *)RTC_BASE)
|
||||
static_assert(sizeof (rtc_hw_t) == 0x0030, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_RTC_H
|
||||
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_SCB_H
|
||||
#define _HARDWARE_STRUCTS_SCB_H
|
||||
|
||||
/**
|
||||
* \file rp2040/scb.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/m0plus.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
|
||||
// CPUID Base Register
|
||||
// 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM
|
||||
// 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: +
|
||||
// 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: +
|
||||
// 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+
|
||||
// 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: +
|
||||
io_ro_32 cpuid;
|
||||
|
||||
_REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
|
||||
// Interrupt Control and State Register
|
||||
// 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI
|
||||
// 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit
|
||||
// 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit
|
||||
// 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit
|
||||
// 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit
|
||||
// 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted
|
||||
// 0x00400000 [22] ISRPENDING (0) External interrupt pending flag
|
||||
// 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority...
|
||||
// 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field
|
||||
io_rw_32 icsr;
|
||||
|
||||
_REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
|
||||
// Vector Table Offset Register
|
||||
// 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address
|
||||
io_rw_32 vtor;
|
||||
|
||||
_REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
|
||||
// Application Interrupt and Reset Control Register
|
||||
// 0xffff0000 [31:16] VECTKEY (0x0000) Register key: +
|
||||
// 0x00008000 [15] ENDIANESS (0) Data endianness implemented: +
|
||||
// 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to...
|
||||
// 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and...
|
||||
io_rw_32 aircr;
|
||||
|
||||
_REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
|
||||
// System Control Register
|
||||
// 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: +
|
||||
// 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep...
|
||||
// 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode...
|
||||
io_rw_32 scr;
|
||||
} armv6m_scb_hw_t;
|
||||
|
||||
#define scb_hw ((armv6m_scb_hw_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET))
|
||||
static_assert(sizeof (armv6m_scb_hw_t) == 0x0014, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_SCB_H
|
||||
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_SIO_H
|
||||
#define _HARDWARE_STRUCTS_SIO_H
|
||||
|
||||
/**
|
||||
* \file rp2040/sio.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/sio.h"
|
||||
#include "hardware/structs/interp.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
|
||||
typedef struct {
|
||||
_REG_(SIO_CPUID_OFFSET) // SIO_CPUID
|
||||
// Processor core identifier
|
||||
// 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when...
|
||||
io_ro_32 cpuid;
|
||||
|
||||
_REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN
|
||||
// Input value for GPIO pins
|
||||
// 0x3fffffff [29:0] GPIO_IN (0x00000000) Input value for GPIO0
|
||||
io_ro_32 gpio_in;
|
||||
|
||||
_REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN
|
||||
// Input value for QSPI pins
|
||||
// 0x0000003f [5:0] GPIO_HI_IN (0x00) Input value on QSPI IO in order 0
|
||||
io_ro_32 gpio_hi_in;
|
||||
|
||||
uint32_t _pad0;
|
||||
|
||||
_REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT
|
||||
// GPIO output value
|
||||
// 0x3fffffff [29:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0
|
||||
io_rw_32 gpio_out;
|
||||
|
||||
_REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET
|
||||
// GPIO output value set
|
||||
// 0x3fffffff [29:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i
|
||||
io_wo_32 gpio_set;
|
||||
|
||||
_REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR
|
||||
// GPIO output value clear
|
||||
// 0x3fffffff [29:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i
|
||||
io_wo_32 gpio_clr;
|
||||
|
||||
_REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR
|
||||
// GPIO output value XOR
|
||||
// 0x3fffffff [29:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i
|
||||
io_wo_32 gpio_togl;
|
||||
|
||||
_REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE
|
||||
// GPIO output enable
|
||||
// 0x3fffffff [29:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0
|
||||
io_rw_32 gpio_oe;
|
||||
|
||||
_REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET
|
||||
// GPIO output enable set
|
||||
// 0x3fffffff [29:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i
|
||||
io_wo_32 gpio_oe_set;
|
||||
|
||||
_REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR
|
||||
// GPIO output enable clear
|
||||
// 0x3fffffff [29:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i
|
||||
io_wo_32 gpio_oe_clr;
|
||||
|
||||
_REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR
|
||||
// GPIO output enable XOR
|
||||
// 0x3fffffff [29:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i
|
||||
io_wo_32 gpio_oe_togl;
|
||||
|
||||
_REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT
|
||||
// QSPI output value
|
||||
// 0x0000003f [5:0] GPIO_HI_OUT (0x00) Set output level (1/0 -> high/low) for QSPI IO0
|
||||
io_rw_32 gpio_hi_out;
|
||||
|
||||
_REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET
|
||||
// QSPI output value set
|
||||
// 0x0000003f [5:0] GPIO_HI_OUT_SET (0x00) Perform an atomic bit-set on GPIO_HI_OUT, i
|
||||
io_wo_32 gpio_hi_set;
|
||||
|
||||
_REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR
|
||||
// QSPI output value clear
|
||||
// 0x0000003f [5:0] GPIO_HI_OUT_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OUT, i
|
||||
io_wo_32 gpio_hi_clr;
|
||||
|
||||
_REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR
|
||||
// QSPI output value XOR
|
||||
// 0x0000003f [5:0] GPIO_HI_OUT_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OUT, i
|
||||
io_wo_32 gpio_hi_togl;
|
||||
|
||||
_REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE
|
||||
// QSPI output enable
|
||||
// 0x0000003f [5:0] GPIO_HI_OE (0x00) Set output enable (1/0 -> output/input) for QSPI IO0
|
||||
io_rw_32 gpio_hi_oe;
|
||||
|
||||
_REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET
|
||||
// QSPI output enable set
|
||||
// 0x0000003f [5:0] GPIO_HI_OE_SET (0x00) Perform an atomic bit-set on GPIO_HI_OE, i
|
||||
io_wo_32 gpio_hi_oe_set;
|
||||
|
||||
_REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR
|
||||
// QSPI output enable clear
|
||||
// 0x0000003f [5:0] GPIO_HI_OE_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OE, i
|
||||
io_wo_32 gpio_hi_oe_clr;
|
||||
|
||||
_REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR
|
||||
// QSPI output enable XOR
|
||||
// 0x0000003f [5:0] GPIO_HI_OE_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OE, i
|
||||
io_wo_32 gpio_hi_oe_togl;
|
||||
|
||||
_REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST
|
||||
// Status register for inter-core FIFOs (mailboxes).
|
||||
// 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty
|
||||
// 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full
|
||||
// 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i
|
||||
// 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i
|
||||
io_rw_32 fifo_st;
|
||||
|
||||
_REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR
|
||||
// Write access to this core's TX FIFO
|
||||
// 0xffffffff [31:0] FIFO_WR (0x00000000)
|
||||
io_wo_32 fifo_wr;
|
||||
|
||||
_REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD
|
||||
// Read access to this core's RX FIFO
|
||||
// 0xffffffff [31:0] FIFO_RD (-)
|
||||
io_ro_32 fifo_rd;
|
||||
|
||||
_REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST
|
||||
// Spinlock state
|
||||
// 0xffffffff [31:0] SPINLOCK_ST (0x00000000)
|
||||
io_ro_32 spinlock_st;
|
||||
|
||||
_REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND
|
||||
// Divider unsigned dividend
|
||||
// 0xffffffff [31:0] DIV_UDIVIDEND (0x00000000)
|
||||
io_rw_32 div_udividend;
|
||||
|
||||
_REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR
|
||||
// Divider unsigned divisor
|
||||
// 0xffffffff [31:0] DIV_UDIVISOR (0x00000000)
|
||||
io_rw_32 div_udivisor;
|
||||
|
||||
_REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND
|
||||
// Divider signed dividend
|
||||
// 0xffffffff [31:0] DIV_SDIVIDEND (0x00000000)
|
||||
io_rw_32 div_sdividend;
|
||||
|
||||
_REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR
|
||||
// Divider signed divisor
|
||||
// 0xffffffff [31:0] DIV_SDIVISOR (0x00000000)
|
||||
io_rw_32 div_sdivisor;
|
||||
|
||||
_REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT
|
||||
// Divider result quotient
|
||||
// 0xffffffff [31:0] DIV_QUOTIENT (0x00000000)
|
||||
io_rw_32 div_quotient;
|
||||
|
||||
_REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER
|
||||
// Divider result remainder
|
||||
// 0xffffffff [31:0] DIV_REMAINDER (0x00000000)
|
||||
io_rw_32 div_remainder;
|
||||
|
||||
_REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR
|
||||
// Control and status register for divider
|
||||
// 0x00000002 [1] DIRTY (0) Changes to 1 when any register is written, and back to 0...
|
||||
// 0x00000001 [0] READY (1) Reads as 0 when a calculation is in progress, 1 otherwise
|
||||
io_ro_32 div_csr;
|
||||
|
||||
uint32_t _pad1;
|
||||
|
||||
interp_hw_t interp[2];
|
||||
|
||||
// (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes)
|
||||
_REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0
|
||||
// Spinlock register 0
|
||||
// 0xffffffff [31:0] SPINLOCK0 (0x00000000)
|
||||
io_rw_32 spinlock[32];
|
||||
} sio_hw_t;
|
||||
|
||||
#define sio_hw ((sio_hw_t *)SIO_BASE)
|
||||
static_assert(sizeof (sio_hw_t) == 0x0180, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_SIO_H
|
||||
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_SPI_H
|
||||
#define _HARDWARE_STRUCTS_SPI_H
|
||||
|
||||
/**
|
||||
* \file rp2040/spi.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/spi.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/spi.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0
|
||||
// Control register 0, SSPCR0 on page 3-4
|
||||
// 0x0000ff00 [15:8] SCR (0x00) Serial clock rate
|
||||
// 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only
|
||||
// 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only
|
||||
// 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format
|
||||
// 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation
|
||||
io_rw_32 cr0;
|
||||
|
||||
_REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1
|
||||
// Control register 1, SSPCR1 on page 3-5
|
||||
// 0x00000008 [3] SOD (0) Slave-mode output disable
|
||||
// 0x00000004 [2] MS (0) Master or slave mode select
|
||||
// 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled
|
||||
// 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled
|
||||
io_rw_32 cr1;
|
||||
|
||||
_REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR
|
||||
// Data register, SSPDR on page 3-6
|
||||
// 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO
|
||||
io_rw_32 dr;
|
||||
|
||||
_REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR
|
||||
// Status register, SSPSR on page 3-7
|
||||
// 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle
|
||||
// 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full
|
||||
// 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty
|
||||
// 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full
|
||||
// 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty
|
||||
io_ro_32 sr;
|
||||
|
||||
_REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR
|
||||
// Clock prescale register, SSPCPSR on page 3-8
|
||||
// 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor
|
||||
io_rw_32 cpsr;
|
||||
|
||||
_REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC
|
||||
// Interrupt mask set or clear register, SSPIMSC on page 3-9
|
||||
// 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty...
|
||||
// 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or...
|
||||
// 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty...
|
||||
// 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written...
|
||||
io_rw_32 imsc;
|
||||
|
||||
_REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS
|
||||
// Raw interrupt status register, SSPRIS on page 3-10
|
||||
// 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the...
|
||||
// 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the...
|
||||
// 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the...
|
||||
// 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the...
|
||||
io_ro_32 ris;
|
||||
|
||||
_REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS
|
||||
// Masked interrupt status register, SSPMIS on page 3-11
|
||||
// 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after...
|
||||
// 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after...
|
||||
// 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after...
|
||||
// 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,...
|
||||
io_ro_32 mis;
|
||||
|
||||
_REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR
|
||||
// Interrupt clear register, SSPICR on page 3-11
|
||||
// 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt
|
||||
// 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt
|
||||
io_rw_32 icr;
|
||||
|
||||
_REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR
|
||||
// DMA control register, SSPDMACR on page 3-12
|
||||
// 0x00000002 [1] TXDMAE (0) Transmit DMA Enable
|
||||
// 0x00000001 [0] RXDMAE (0) Receive DMA Enable
|
||||
io_rw_32 dmacr;
|
||||
} spi_hw_t;
|
||||
|
||||
#define spi0_hw ((spi_hw_t *)SPI0_BASE)
|
||||
#define spi1_hw ((spi_hw_t *)SPI1_BASE)
|
||||
static_assert(sizeof (spi_hw_t) == 0x0028, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_SPI_H
|
||||
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_SSI_H
|
||||
#define _HARDWARE_STRUCTS_SSI_H
|
||||
|
||||
/**
|
||||
* \file rp2040/ssi.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/ssi.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/ssi.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0
|
||||
// Control register 0
|
||||
// 0x01000000 [24] SSTE (0) Slave select toggle enable
|
||||
// 0x00600000 [22:21] SPI_FRF (0x0) SPI frame format
|
||||
// 0x001f0000 [20:16] DFS_32 (0x00) Data frame size in 32b transfer mode +
|
||||
// 0x0000f000 [15:12] CFS (0x0) Control frame size +
|
||||
// 0x00000800 [11] SRL (0) Shift register loop (test mode)
|
||||
// 0x00000400 [10] SLV_OE (0) Slave output enable
|
||||
// 0x00000300 [9:8] TMOD (0x0) Transfer mode
|
||||
// 0x00000080 [7] SCPOL (0) Serial clock polarity
|
||||
// 0x00000040 [6] SCPH (0) Serial clock phase
|
||||
// 0x00000030 [5:4] FRF (0x0) Frame format
|
||||
// 0x0000000f [3:0] DFS (0x0) Data frame size
|
||||
io_rw_32 ctrlr0;
|
||||
|
||||
_REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1
|
||||
// Master Control register 1
|
||||
// 0x0000ffff [15:0] NDF (0x0000) Number of data frames
|
||||
io_rw_32 ctrlr1;
|
||||
|
||||
_REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR
|
||||
// SSI Enable
|
||||
// 0x00000001 [0] SSI_EN (0) SSI enable
|
||||
io_rw_32 ssienr;
|
||||
|
||||
_REG_(SSI_MWCR_OFFSET) // SSI_MWCR
|
||||
// Microwire Control
|
||||
// 0x00000004 [2] MHS (0) Microwire handshaking
|
||||
// 0x00000002 [1] MDD (0) Microwire control
|
||||
// 0x00000001 [0] MWMOD (0) Microwire transfer mode
|
||||
io_rw_32 mwcr;
|
||||
|
||||
_REG_(SSI_SER_OFFSET) // SSI_SER
|
||||
// Slave enable
|
||||
// 0x00000001 [0] SER (0) For each bit: +
|
||||
io_rw_32 ser;
|
||||
|
||||
_REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR
|
||||
// Baud rate
|
||||
// 0x0000ffff [15:0] SCKDV (0x0000) SSI clock divider
|
||||
io_rw_32 baudr;
|
||||
|
||||
_REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR
|
||||
// TX FIFO threshold level
|
||||
// 0x000000ff [7:0] TFT (0x00) Transmit FIFO threshold
|
||||
io_rw_32 txftlr;
|
||||
|
||||
_REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR
|
||||
// RX FIFO threshold level
|
||||
// 0x000000ff [7:0] RFT (0x00) Receive FIFO threshold
|
||||
io_rw_32 rxftlr;
|
||||
|
||||
_REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR
|
||||
// TX FIFO level
|
||||
// 0x000000ff [7:0] TFTFL (0x00) Transmit FIFO level
|
||||
io_ro_32 txflr;
|
||||
|
||||
_REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR
|
||||
// RX FIFO level
|
||||
// 0x000000ff [7:0] RXTFL (0x00) Receive FIFO level
|
||||
io_ro_32 rxflr;
|
||||
|
||||
_REG_(SSI_SR_OFFSET) // SSI_SR
|
||||
// Status register
|
||||
// 0x00000040 [6] DCOL (0) Data collision error
|
||||
// 0x00000020 [5] TXE (0) Transmission error
|
||||
// 0x00000010 [4] RFF (0) Receive FIFO full
|
||||
// 0x00000008 [3] RFNE (0) Receive FIFO not empty
|
||||
// 0x00000004 [2] TFE (0) Transmit FIFO empty
|
||||
// 0x00000002 [1] TFNF (0) Transmit FIFO not full
|
||||
// 0x00000001 [0] BUSY (0) SSI busy flag
|
||||
io_ro_32 sr;
|
||||
|
||||
_REG_(SSI_IMR_OFFSET) // SSI_IMR
|
||||
// Interrupt mask
|
||||
// 0x00000020 [5] MSTIM (0) Multi-master contention interrupt mask
|
||||
// 0x00000010 [4] RXFIM (0) Receive FIFO full interrupt mask
|
||||
// 0x00000008 [3] RXOIM (0) Receive FIFO overflow interrupt mask
|
||||
// 0x00000004 [2] RXUIM (0) Receive FIFO underflow interrupt mask
|
||||
// 0x00000002 [1] TXOIM (0) Transmit FIFO overflow interrupt mask
|
||||
// 0x00000001 [0] TXEIM (0) Transmit FIFO empty interrupt mask
|
||||
io_rw_32 imr;
|
||||
|
||||
_REG_(SSI_ISR_OFFSET) // SSI_ISR
|
||||
// Interrupt status
|
||||
// 0x00000020 [5] MSTIS (0) Multi-master contention interrupt status
|
||||
// 0x00000010 [4] RXFIS (0) Receive FIFO full interrupt status
|
||||
// 0x00000008 [3] RXOIS (0) Receive FIFO overflow interrupt status
|
||||
// 0x00000004 [2] RXUIS (0) Receive FIFO underflow interrupt status
|
||||
// 0x00000002 [1] TXOIS (0) Transmit FIFO overflow interrupt status
|
||||
// 0x00000001 [0] TXEIS (0) Transmit FIFO empty interrupt status
|
||||
io_ro_32 isr;
|
||||
|
||||
_REG_(SSI_RISR_OFFSET) // SSI_RISR
|
||||
// Raw interrupt status
|
||||
// 0x00000020 [5] MSTIR (0) Multi-master contention raw interrupt status
|
||||
// 0x00000010 [4] RXFIR (0) Receive FIFO full raw interrupt status
|
||||
// 0x00000008 [3] RXOIR (0) Receive FIFO overflow raw interrupt status
|
||||
// 0x00000004 [2] RXUIR (0) Receive FIFO underflow raw interrupt status
|
||||
// 0x00000002 [1] TXOIR (0) Transmit FIFO overflow raw interrupt status
|
||||
// 0x00000001 [0] TXEIR (0) Transmit FIFO empty raw interrupt status
|
||||
io_ro_32 risr;
|
||||
|
||||
_REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR
|
||||
// TX FIFO overflow interrupt clear
|
||||
// 0x00000001 [0] TXOICR (0) Clear-on-read transmit FIFO overflow interrupt
|
||||
io_ro_32 txoicr;
|
||||
|
||||
_REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR
|
||||
// RX FIFO overflow interrupt clear
|
||||
// 0x00000001 [0] RXOICR (0) Clear-on-read receive FIFO overflow interrupt
|
||||
io_ro_32 rxoicr;
|
||||
|
||||
_REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR
|
||||
// RX FIFO underflow interrupt clear
|
||||
// 0x00000001 [0] RXUICR (0) Clear-on-read receive FIFO underflow interrupt
|
||||
io_ro_32 rxuicr;
|
||||
|
||||
_REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR
|
||||
// Multi-master interrupt clear
|
||||
// 0x00000001 [0] MSTICR (0) Clear-on-read multi-master contention interrupt
|
||||
io_ro_32 msticr;
|
||||
|
||||
_REG_(SSI_ICR_OFFSET) // SSI_ICR
|
||||
// Interrupt clear
|
||||
// 0x00000001 [0] ICR (0) Clear-on-read all active interrupts
|
||||
io_ro_32 icr;
|
||||
|
||||
_REG_(SSI_DMACR_OFFSET) // SSI_DMACR
|
||||
// DMA control
|
||||
// 0x00000002 [1] TDMAE (0) Transmit DMA enable
|
||||
// 0x00000001 [0] RDMAE (0) Receive DMA enable
|
||||
io_rw_32 dmacr;
|
||||
|
||||
_REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR
|
||||
// DMA TX data level
|
||||
// 0x000000ff [7:0] DMATDL (0x00) Transmit data watermark level
|
||||
io_rw_32 dmatdlr;
|
||||
|
||||
_REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR
|
||||
// DMA RX data level
|
||||
// 0x000000ff [7:0] DMARDL (0x00) Receive data watermark level (DMARDLR+1)
|
||||
io_rw_32 dmardlr;
|
||||
|
||||
_REG_(SSI_IDR_OFFSET) // SSI_IDR
|
||||
// Identification register
|
||||
// 0xffffffff [31:0] IDCODE (0x51535049) Peripheral dentification code
|
||||
io_ro_32 idr;
|
||||
|
||||
_REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID
|
||||
// Version ID
|
||||
// 0xffffffff [31:0] SSI_COMP_VERSION (0x3430312a) SNPS component version (format X
|
||||
io_ro_32 ssi_version_id;
|
||||
|
||||
_REG_(SSI_DR0_OFFSET) // SSI_DR0
|
||||
// Data Register 0 (of 36)
|
||||
// 0xffffffff [31:0] DR (0x00000000) First data register of 36
|
||||
io_rw_32 dr0;
|
||||
|
||||
uint32_t _pad0[35];
|
||||
|
||||
_REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY
|
||||
// RX sample delay
|
||||
// 0x000000ff [7:0] RSD (0x00) RXD sample delay (in SCLK cycles)
|
||||
io_rw_32 rx_sample_dly;
|
||||
|
||||
_REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0
|
||||
// SPI control
|
||||
// 0xff000000 [31:24] XIP_CMD (0x03) SPI Command to send in XIP mode (INST_L = 8-bit) or to...
|
||||
// 0x00040000 [18] SPI_RXDS_EN (0) Read data strobe enable
|
||||
// 0x00020000 [17] INST_DDR_EN (0) Instruction DDR transfer enable
|
||||
// 0x00010000 [16] SPI_DDR_EN (0) SPI DDR transfer enable
|
||||
// 0x0000f800 [15:11] WAIT_CYCLES (0x00) Wait cycles between control frame transmit and data...
|
||||
// 0x00000300 [9:8] INST_L (0x0) Instruction length (0/4/8/16b)
|
||||
// 0x0000003c [5:2] ADDR_L (0x0) Address length (0b-60b in 4b increments)
|
||||
// 0x00000003 [1:0] TRANS_TYPE (0x0) Address and instruction transfer format
|
||||
io_rw_32 spi_ctrlr0;
|
||||
|
||||
_REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE
|
||||
// TX drive edge
|
||||
// 0x000000ff [7:0] TDE (0x00) TXD drive edge
|
||||
io_rw_32 txd_drive_edge;
|
||||
} ssi_hw_t;
|
||||
|
||||
#define ssi_hw ((ssi_hw_t *)XIP_SSI_BASE)
|
||||
static_assert(sizeof (ssi_hw_t) == 0x00fc, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_SSI_H
|
||||
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_SYSCFG_H
|
||||
#define _HARDWARE_STRUCTS_SYSCFG_H
|
||||
|
||||
/**
|
||||
* \file rp2040/syscfg.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/syscfg.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_syscfg
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK
|
||||
// Processor core 0 NMI source mask
|
||||
// 0xffffffff [31:0] PROC0_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ
|
||||
io_rw_32 proc0_nmi_mask;
|
||||
|
||||
_REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK
|
||||
// Processor core 1 NMI source mask
|
||||
// 0xffffffff [31:0] PROC1_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ
|
||||
io_rw_32 proc1_nmi_mask;
|
||||
|
||||
_REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG
|
||||
// Configuration for processors
|
||||
// 0xf0000000 [31:28] PROC1_DAP_INSTID (0x1) Configure proc1 DAP instance ID
|
||||
// 0x0f000000 [27:24] PROC0_DAP_INSTID (0x0) Configure proc0 DAP instance ID
|
||||
// 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted
|
||||
// 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted
|
||||
io_rw_32 proc_config;
|
||||
|
||||
_REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS
|
||||
// For each bit, if 1, bypass the input synchronizer between that GPIO +
|
||||
// 0x3fffffff [29:0] PROC_IN_SYNC_BYPASS (0x00000000)
|
||||
io_rw_32 proc_in_sync_bypass;
|
||||
|
||||
_REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI
|
||||
// For each bit, if 1, bypass the input synchronizer between that GPIO +
|
||||
// 0x0000003f [5:0] PROC_IN_SYNC_BYPASS_HI (0x00)
|
||||
io_rw_32 proc_in_sync_bypass_hi;
|
||||
|
||||
_REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE
|
||||
// Directly control the SWD debug port of either processor
|
||||
// 0x00000080 [7] PROC1_ATTACH (0) Attach processor 1 debug port to syscfg controls, and...
|
||||
// 0x00000040 [6] PROC1_SWCLK (1) Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
|
||||
// 0x00000020 [5] PROC1_SWDI (1) Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
|
||||
// 0x00000010 [4] PROC1_SWDO (-) Observe the value of processor 1 SWDIO output
|
||||
// 0x00000008 [3] PROC0_ATTACH (0) Attach processor 0 debug port to syscfg controls, and...
|
||||
// 0x00000004 [2] PROC0_SWCLK (1) Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
|
||||
// 0x00000002 [1] PROC0_SWDI (1) Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
|
||||
// 0x00000001 [0] PROC0_SWDO (-) Observe the value of processor 0 SWDIO output
|
||||
io_rw_32 dbgforce;
|
||||
|
||||
_REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN
|
||||
// Control power downs to memories
|
||||
// 0x00000080 [7] ROM (0)
|
||||
// 0x00000040 [6] USB (0)
|
||||
// 0x00000020 [5] SRAM5 (0)
|
||||
// 0x00000010 [4] SRAM4 (0)
|
||||
// 0x00000008 [3] SRAM3 (0)
|
||||
// 0x00000004 [2] SRAM2 (0)
|
||||
// 0x00000002 [1] SRAM1 (0)
|
||||
// 0x00000001 [0] SRAM0 (0)
|
||||
io_rw_32 mempowerdown;
|
||||
} syscfg_hw_t;
|
||||
|
||||
#define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE)
|
||||
static_assert(sizeof (syscfg_hw_t) == 0x001c, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_SYSCFG_H
|
||||
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_SYSINFO_H
|
||||
#define _HARDWARE_STRUCTS_SYSINFO_H
|
||||
|
||||
/**
|
||||
* \file rp2040/sysinfo.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/sysinfo.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sysinfo
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/sysinfo.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID
|
||||
// JEDEC JEP-106 compliant chip identifier
|
||||
// 0xf0000000 [31:28] REVISION (-)
|
||||
// 0x0ffff000 [27:12] PART (-)
|
||||
// 0x00000fff [11:0] MANUFACTURER (-)
|
||||
io_ro_32 chip_id;
|
||||
|
||||
_REG_(SYSINFO_PLATFORM_OFFSET) // SYSINFO_PLATFORM
|
||||
// Platform register
|
||||
// 0x00000002 [1] ASIC (0)
|
||||
// 0x00000001 [0] FPGA (0)
|
||||
io_ro_32 platform;
|
||||
|
||||
uint32_t _pad0[2];
|
||||
|
||||
_REG_(SYSINFO_GITREF_RP2040_OFFSET) // SYSINFO_GITREF_RP2040
|
||||
// Git hash of the chip source
|
||||
// 0xffffffff [31:0] GITREF_RP2040 (-)
|
||||
io_ro_32 gitref_rp2040;
|
||||
} sysinfo_hw_t;
|
||||
|
||||
#define sysinfo_hw ((sysinfo_hw_t *)SYSINFO_BASE)
|
||||
static_assert(sizeof (sysinfo_hw_t) == 0x0014, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_SYSINFO_H
|
||||
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_SYSTICK_H
|
||||
#define _HARDWARE_STRUCTS_SYSTICK_H
|
||||
|
||||
/**
|
||||
* \file rp2040/systick.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/m0plus.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR
|
||||
// SysTick Control and Status Register
|
||||
// 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read
|
||||
// 0x00000004 [2] CLKSOURCE (0) SysTick clock source
|
||||
// 0x00000002 [1] TICKINT (0) Enables SysTick exception request: +
|
||||
// 0x00000001 [0] ENABLE (0) Enable SysTick counter: +
|
||||
io_rw_32 csr;
|
||||
|
||||
_REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR
|
||||
// SysTick Reload Value Register
|
||||
// 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register...
|
||||
io_rw_32 rvr;
|
||||
|
||||
_REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR
|
||||
// SysTick Current Value Register
|
||||
// 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter
|
||||
io_rw_32 cvr;
|
||||
|
||||
_REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB
|
||||
// SysTick Calibration Value Register
|
||||
// 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the...
|
||||
// 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact...
|
||||
// 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)...
|
||||
io_ro_32 calib;
|
||||
} systick_hw_t;
|
||||
|
||||
#define systick_hw ((systick_hw_t *)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET))
|
||||
static_assert(sizeof (systick_hw_t) == 0x0010, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_SYSTICK_H
|
||||
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_TBMAN_H
|
||||
#define _HARDWARE_STRUCTS_TBMAN_H
|
||||
|
||||
/**
|
||||
* \file rp2040/tbman.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/tbman.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_tbman
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/tbman.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(TBMAN_PLATFORM_OFFSET) // TBMAN_PLATFORM
|
||||
// Indicates the type of platform in use
|
||||
// 0x00000002 [1] FPGA (0) Indicates the platform is an FPGA
|
||||
// 0x00000001 [0] ASIC (1) Indicates the platform is an ASIC
|
||||
io_ro_32 platform;
|
||||
} tbman_hw_t;
|
||||
|
||||
#define tbman_hw ((tbman_hw_t *)TBMAN_BASE)
|
||||
static_assert(sizeof (tbman_hw_t) == 0x0004, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_TBMAN_H
|
||||
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_TIMER_H
|
||||
#define _HARDWARE_STRUCTS_TIMER_H
|
||||
|
||||
/**
|
||||
* \file rp2040/timer.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/timer.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/timer.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW
|
||||
// Write to bits 63:32 of time +
|
||||
// 0xffffffff [31:0] TIMEHW (0x00000000)
|
||||
io_wo_32 timehw;
|
||||
|
||||
_REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW
|
||||
// Write to bits 31:0 of time +
|
||||
// 0xffffffff [31:0] TIMELW (0x00000000)
|
||||
io_wo_32 timelw;
|
||||
|
||||
_REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR
|
||||
// Read from bits 63:32 of time +
|
||||
// 0xffffffff [31:0] TIMEHR (0x00000000)
|
||||
io_ro_32 timehr;
|
||||
|
||||
_REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR
|
||||
// Read from bits 31:0 of time
|
||||
// 0xffffffff [31:0] TIMELR (0x00000000)
|
||||
io_ro_32 timelr;
|
||||
|
||||
// (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes)
|
||||
_REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0
|
||||
// Arm alarm 0, and configure the time it will fire
|
||||
// 0xffffffff [31:0] ALARM0 (0x00000000)
|
||||
io_rw_32 alarm[4];
|
||||
|
||||
_REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED
|
||||
// Indicates the armed/disarmed status of each alarm
|
||||
// 0x0000000f [3:0] ARMED (0x0)
|
||||
io_rw_32 armed;
|
||||
|
||||
_REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH
|
||||
// Raw read from bits 63:32 of time (no side effects)
|
||||
// 0xffffffff [31:0] TIMERAWH (0x00000000)
|
||||
io_ro_32 timerawh;
|
||||
|
||||
_REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL
|
||||
// Raw read from bits 31:0 of time (no side effects)
|
||||
// 0xffffffff [31:0] TIMERAWL (0x00000000)
|
||||
io_ro_32 timerawl;
|
||||
|
||||
_REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE
|
||||
// Set bits high to enable pause when the corresponding debug ports are active
|
||||
// 0x00000004 [2] DBG1 (1) Pause when processor 1 is in debug mode
|
||||
// 0x00000002 [1] DBG0 (1) Pause when processor 0 is in debug mode
|
||||
io_rw_32 dbgpause;
|
||||
|
||||
_REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE
|
||||
// Set high to pause the timer
|
||||
// 0x00000001 [0] PAUSE (0)
|
||||
io_rw_32 pause;
|
||||
|
||||
_REG_(TIMER_INTR_OFFSET) // TIMER_INTR
|
||||
// Raw Interrupts
|
||||
// 0x00000008 [3] ALARM_3 (0)
|
||||
// 0x00000004 [2] ALARM_2 (0)
|
||||
// 0x00000002 [1] ALARM_1 (0)
|
||||
// 0x00000001 [0] ALARM_0 (0)
|
||||
io_rw_32 intr;
|
||||
|
||||
_REG_(TIMER_INTE_OFFSET) // TIMER_INTE
|
||||
// Interrupt Enable
|
||||
// 0x00000008 [3] ALARM_3 (0)
|
||||
// 0x00000004 [2] ALARM_2 (0)
|
||||
// 0x00000002 [1] ALARM_1 (0)
|
||||
// 0x00000001 [0] ALARM_0 (0)
|
||||
io_rw_32 inte;
|
||||
|
||||
_REG_(TIMER_INTF_OFFSET) // TIMER_INTF
|
||||
// Interrupt Force
|
||||
// 0x00000008 [3] ALARM_3 (0)
|
||||
// 0x00000004 [2] ALARM_2 (0)
|
||||
// 0x00000002 [1] ALARM_1 (0)
|
||||
// 0x00000001 [0] ALARM_0 (0)
|
||||
io_rw_32 intf;
|
||||
|
||||
_REG_(TIMER_INTS_OFFSET) // TIMER_INTS
|
||||
// Interrupt status after masking & forcing
|
||||
// 0x00000008 [3] ALARM_3 (0)
|
||||
// 0x00000004 [2] ALARM_2 (0)
|
||||
// 0x00000002 [1] ALARM_1 (0)
|
||||
// 0x00000001 [0] ALARM_0 (0)
|
||||
io_ro_32 ints;
|
||||
} timer_hw_t;
|
||||
|
||||
#define timer_hw ((timer_hw_t *)TIMER_BASE)
|
||||
static_assert(sizeof (timer_hw_t) == 0x0044, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_TIMER_H
|
||||
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_UART_H
|
||||
#define _HARDWARE_STRUCTS_UART_H
|
||||
|
||||
/**
|
||||
* \file rp2040/uart.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/uart.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/uart.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(UART_UARTDR_OFFSET) // UART_UARTDR
|
||||
// Data Register, UARTDR
|
||||
// 0x00000800 [11] OE (-) Overrun error
|
||||
// 0x00000400 [10] BE (-) Break error
|
||||
// 0x00000200 [9] PE (-) Parity error
|
||||
// 0x00000100 [8] FE (-) Framing error
|
||||
// 0x000000ff [7:0] DATA (-) Receive (read) data character
|
||||
io_rw_32 dr;
|
||||
|
||||
_REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR
|
||||
// Receive Status Register/Error Clear Register, UARTRSR/UARTECR
|
||||
// 0x00000008 [3] OE (0) Overrun error
|
||||
// 0x00000004 [2] BE (0) Break error
|
||||
// 0x00000002 [1] PE (0) Parity error
|
||||
// 0x00000001 [0] FE (0) Framing error
|
||||
io_rw_32 rsr;
|
||||
|
||||
uint32_t _pad0[4];
|
||||
|
||||
_REG_(UART_UARTFR_OFFSET) // UART_UARTFR
|
||||
// Flag Register, UARTFR
|
||||
// 0x00000100 [8] RI (-) Ring indicator
|
||||
// 0x00000080 [7] TXFE (1) Transmit FIFO empty
|
||||
// 0x00000040 [6] RXFF (0) Receive FIFO full
|
||||
// 0x00000020 [5] TXFF (0) Transmit FIFO full
|
||||
// 0x00000010 [4] RXFE (1) Receive FIFO empty
|
||||
// 0x00000008 [3] BUSY (0) UART busy
|
||||
// 0x00000004 [2] DCD (-) Data carrier detect
|
||||
// 0x00000002 [1] DSR (-) Data set ready
|
||||
// 0x00000001 [0] CTS (-) Clear to send
|
||||
io_ro_32 fr;
|
||||
|
||||
uint32_t _pad1;
|
||||
|
||||
_REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR
|
||||
// IrDA Low-Power Counter Register, UARTILPR
|
||||
// 0x000000ff [7:0] ILPDVSR (0x00) 8-bit low-power divisor value
|
||||
io_rw_32 ilpr;
|
||||
|
||||
_REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD
|
||||
// Integer Baud Rate Register, UARTIBRD
|
||||
// 0x0000ffff [15:0] BAUD_DIVINT (0x0000) The integer baud rate divisor
|
||||
io_rw_32 ibrd;
|
||||
|
||||
_REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD
|
||||
// Fractional Baud Rate Register, UARTFBRD
|
||||
// 0x0000003f [5:0] BAUD_DIVFRAC (0x00) The fractional baud rate divisor
|
||||
io_rw_32 fbrd;
|
||||
|
||||
_REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H
|
||||
// Line Control Register, UARTLCR_H
|
||||
// 0x00000080 [7] SPS (0) Stick parity select
|
||||
// 0x00000060 [6:5] WLEN (0x0) Word length
|
||||
// 0x00000010 [4] FEN (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)...
|
||||
// 0x00000008 [3] STP2 (0) Two stop bits select
|
||||
// 0x00000004 [2] EPS (0) Even parity select
|
||||
// 0x00000002 [1] PEN (0) Parity enable: 0 = parity is disabled and no parity bit...
|
||||
// 0x00000001 [0] BRK (0) Send break
|
||||
io_rw_32 lcr_h;
|
||||
|
||||
_REG_(UART_UARTCR_OFFSET) // UART_UARTCR
|
||||
// Control Register, UARTCR
|
||||
// 0x00008000 [15] CTSEN (0) CTS hardware flow control enable
|
||||
// 0x00004000 [14] RTSEN (0) RTS hardware flow control enable
|
||||
// 0x00002000 [13] OUT2 (0) This bit is the complement of the UART Out2 (nUARTOut2)...
|
||||
// 0x00001000 [12] OUT1 (0) This bit is the complement of the UART Out1 (nUARTOut1)...
|
||||
// 0x00000800 [11] RTS (0) Request to send
|
||||
// 0x00000400 [10] DTR (0) Data transmit ready
|
||||
// 0x00000200 [9] RXE (1) Receive enable
|
||||
// 0x00000100 [8] TXE (1) Transmit enable
|
||||
// 0x00000080 [7] LBE (0) Loopback enable
|
||||
// 0x00000004 [2] SIRLP (0) SIR low-power IrDA mode
|
||||
// 0x00000002 [1] SIREN (0) SIR enable: 0 = IrDA SIR ENDEC is disabled
|
||||
// 0x00000001 [0] UARTEN (0) UART enable: 0 = UART is disabled
|
||||
io_rw_32 cr;
|
||||
|
||||
_REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS
|
||||
// Interrupt FIFO Level Select Register, UARTIFLS
|
||||
// 0x00000038 [5:3] RXIFLSEL (0x2) Receive interrupt FIFO level select
|
||||
// 0x00000007 [2:0] TXIFLSEL (0x2) Transmit interrupt FIFO level select
|
||||
io_rw_32 ifls;
|
||||
|
||||
_REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC
|
||||
// Interrupt Mask Set/Clear Register, UARTIMSC
|
||||
// 0x00000400 [10] OEIM (0) Overrun error interrupt mask
|
||||
// 0x00000200 [9] BEIM (0) Break error interrupt mask
|
||||
// 0x00000100 [8] PEIM (0) Parity error interrupt mask
|
||||
// 0x00000080 [7] FEIM (0) Framing error interrupt mask
|
||||
// 0x00000040 [6] RTIM (0) Receive timeout interrupt mask
|
||||
// 0x00000020 [5] TXIM (0) Transmit interrupt mask
|
||||
// 0x00000010 [4] RXIM (0) Receive interrupt mask
|
||||
// 0x00000008 [3] DSRMIM (0) nUARTDSR modem interrupt mask
|
||||
// 0x00000004 [2] DCDMIM (0) nUARTDCD modem interrupt mask
|
||||
// 0x00000002 [1] CTSMIM (0) nUARTCTS modem interrupt mask
|
||||
// 0x00000001 [0] RIMIM (0) nUARTRI modem interrupt mask
|
||||
io_rw_32 imsc;
|
||||
|
||||
_REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS
|
||||
// Raw Interrupt Status Register, UARTRIS
|
||||
// 0x00000400 [10] OERIS (0) Overrun error interrupt status
|
||||
// 0x00000200 [9] BERIS (0) Break error interrupt status
|
||||
// 0x00000100 [8] PERIS (0) Parity error interrupt status
|
||||
// 0x00000080 [7] FERIS (0) Framing error interrupt status
|
||||
// 0x00000040 [6] RTRIS (0) Receive timeout interrupt status
|
||||
// 0x00000020 [5] TXRIS (0) Transmit interrupt status
|
||||
// 0x00000010 [4] RXRIS (0) Receive interrupt status
|
||||
// 0x00000008 [3] DSRRMIS (-) nUARTDSR modem interrupt status
|
||||
// 0x00000004 [2] DCDRMIS (-) nUARTDCD modem interrupt status
|
||||
// 0x00000002 [1] CTSRMIS (-) nUARTCTS modem interrupt status
|
||||
// 0x00000001 [0] RIRMIS (-) nUARTRI modem interrupt status
|
||||
io_ro_32 ris;
|
||||
|
||||
_REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS
|
||||
// Masked Interrupt Status Register, UARTMIS
|
||||
// 0x00000400 [10] OEMIS (0) Overrun error masked interrupt status
|
||||
// 0x00000200 [9] BEMIS (0) Break error masked interrupt status
|
||||
// 0x00000100 [8] PEMIS (0) Parity error masked interrupt status
|
||||
// 0x00000080 [7] FEMIS (0) Framing error masked interrupt status
|
||||
// 0x00000040 [6] RTMIS (0) Receive timeout masked interrupt status
|
||||
// 0x00000020 [5] TXMIS (0) Transmit masked interrupt status
|
||||
// 0x00000010 [4] RXMIS (0) Receive masked interrupt status
|
||||
// 0x00000008 [3] DSRMMIS (-) nUARTDSR modem masked interrupt status
|
||||
// 0x00000004 [2] DCDMMIS (-) nUARTDCD modem masked interrupt status
|
||||
// 0x00000002 [1] CTSMMIS (-) nUARTCTS modem masked interrupt status
|
||||
// 0x00000001 [0] RIMMIS (-) nUARTRI modem masked interrupt status
|
||||
io_ro_32 mis;
|
||||
|
||||
_REG_(UART_UARTICR_OFFSET) // UART_UARTICR
|
||||
// Interrupt Clear Register, UARTICR
|
||||
// 0x00000400 [10] OEIC (-) Overrun error interrupt clear
|
||||
// 0x00000200 [9] BEIC (-) Break error interrupt clear
|
||||
// 0x00000100 [8] PEIC (-) Parity error interrupt clear
|
||||
// 0x00000080 [7] FEIC (-) Framing error interrupt clear
|
||||
// 0x00000040 [6] RTIC (-) Receive timeout interrupt clear
|
||||
// 0x00000020 [5] TXIC (-) Transmit interrupt clear
|
||||
// 0x00000010 [4] RXIC (-) Receive interrupt clear
|
||||
// 0x00000008 [3] DSRMIC (-) nUARTDSR modem interrupt clear
|
||||
// 0x00000004 [2] DCDMIC (-) nUARTDCD modem interrupt clear
|
||||
// 0x00000002 [1] CTSMIC (-) nUARTCTS modem interrupt clear
|
||||
// 0x00000001 [0] RIMIC (-) nUARTRI modem interrupt clear
|
||||
io_rw_32 icr;
|
||||
|
||||
_REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR
|
||||
// DMA Control Register, UARTDMACR
|
||||
// 0x00000004 [2] DMAONERR (0) DMA on error
|
||||
// 0x00000002 [1] TXDMAE (0) Transmit DMA enable
|
||||
// 0x00000001 [0] RXDMAE (0) Receive DMA enable
|
||||
io_rw_32 dmacr;
|
||||
} uart_hw_t;
|
||||
|
||||
#define uart0_hw ((uart_hw_t *)UART0_BASE)
|
||||
#define uart1_hw ((uart_hw_t *)UART1_BASE)
|
||||
static_assert(sizeof (uart_hw_t) == 0x004c, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_UART_H
|
||||
|
||||
|
|
@ -0,0 +1,476 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_USB_H
|
||||
#define _HARDWARE_STRUCTS_USB_H
|
||||
|
||||
/**
|
||||
* \file rp2040/usb.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/usb.h"
|
||||
#include "hardware/structs/usb_dpram.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/usb.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP
|
||||
// Device address and endpoint control
|
||||
// 0x000f0000 [19:16] ENDPOINT (0x0) Device endpoint to send data to
|
||||
// 0x0000007f [6:0] ADDRESS (0x00) In device mode, the address that the device should respond to
|
||||
io_rw_32 dev_addr_ctrl;
|
||||
|
||||
// (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes)
|
||||
_REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1
|
||||
// Interrupt endpoint 1
|
||||
// 0x04000000 [26] INTEP_PREAMBLE (0) Interrupt EP requires preamble (is a low speed device on...
|
||||
// 0x02000000 [25] INTEP_DIR (0) Direction of the interrupt endpoint
|
||||
// 0x000f0000 [19:16] ENDPOINT (0x0) Endpoint number of the interrupt endpoint
|
||||
// 0x0000007f [6:0] ADDRESS (0x00) Device address
|
||||
io_rw_32 int_ep_addr_ctrl[15];
|
||||
|
||||
_REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL
|
||||
// Main control register
|
||||
// 0x80000000 [31] SIM_TIMING (0) Reduced timings for simulation
|
||||
// 0x00000002 [1] HOST_NDEVICE (0) Device mode = 0, Host mode = 1
|
||||
// 0x00000001 [0] CONTROLLER_EN (0) Enable controller
|
||||
io_rw_32 main_ctrl;
|
||||
|
||||
_REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR
|
||||
// Set the SOF (Start of Frame) frame number in the host controller
|
||||
// 0x000007ff [10:0] COUNT (0x000)
|
||||
io_wo_32 sof_wr;
|
||||
|
||||
_REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD
|
||||
// Read the last SOF (Start of Frame) frame number seen
|
||||
// 0x000007ff [10:0] COUNT (0x000)
|
||||
io_ro_32 sof_rd;
|
||||
|
||||
_REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL
|
||||
// SIE control register
|
||||
// 0x80000000 [31] EP0_INT_STALL (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
|
||||
// 0x40000000 [30] EP0_DOUBLE_BUF (0) Device: EP0 single buffered = 0, double buffered = 1
|
||||
// 0x20000000 [29] EP0_INT_1BUF (0) Device: Set bit in BUFF_STATUS for every buffer completed on EP0
|
||||
// 0x10000000 [28] EP0_INT_2BUF (0) Device: Set bit in BUFF_STATUS for every 2 buffers...
|
||||
// 0x08000000 [27] EP0_INT_NAK (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
|
||||
// 0x04000000 [26] DIRECT_EN (0) Direct bus drive enable
|
||||
// 0x02000000 [25] DIRECT_DP (0) Direct control of DP
|
||||
// 0x01000000 [24] DIRECT_DM (0) Direct control of DM
|
||||
// 0x00040000 [18] TRANSCEIVER_PD (0) Power down bus transceiver
|
||||
// 0x00020000 [17] RPU_OPT (0) Device: Pull-up strength (0=1K2, 1=2k3)
|
||||
// 0x00010000 [16] PULLUP_EN (0) Device: Enable pull up resistor
|
||||
// 0x00008000 [15] PULLDOWN_EN (0) Host: Enable pull down resistors
|
||||
// 0x00002000 [13] RESET_BUS (0) Host: Reset bus
|
||||
// 0x00001000 [12] RESUME (0) Device: Remote wakeup
|
||||
// 0x00000800 [11] VBUS_EN (0) Host: Enable VBUS
|
||||
// 0x00000400 [10] KEEP_ALIVE_EN (0) Host: Enable keep alive packet (for low speed bus)
|
||||
// 0x00000200 [9] SOF_EN (0) Host: Enable SOF generation (for full speed bus)
|
||||
// 0x00000100 [8] SOF_SYNC (0) Host: Delay packet(s) until after SOF
|
||||
// 0x00000040 [6] PREAMBLE_EN (0) Host: Preable enable for LS device on FS hub
|
||||
// 0x00000010 [4] STOP_TRANS (0) Host: Stop transaction
|
||||
// 0x00000008 [3] RECEIVE_DATA (0) Host: Receive transaction (IN to host)
|
||||
// 0x00000004 [2] SEND_DATA (0) Host: Send transaction (OUT from host)
|
||||
// 0x00000002 [1] SEND_SETUP (0) Host: Send Setup packet
|
||||
// 0x00000001 [0] START_TRANS (0) Host: Start transaction
|
||||
io_rw_32 sie_ctrl;
|
||||
|
||||
_REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS
|
||||
// SIE status register
|
||||
// 0x80000000 [31] DATA_SEQ_ERROR (0) Data Sequence Error
|
||||
// 0x40000000 [30] ACK_REC (0) ACK received
|
||||
// 0x20000000 [29] STALL_REC (0) Host: STALL received
|
||||
// 0x10000000 [28] NAK_REC (0) Host: NAK received
|
||||
// 0x08000000 [27] RX_TIMEOUT (0) RX timeout is raised by both the host and device if an...
|
||||
// 0x04000000 [26] RX_OVERFLOW (0) RX overflow is raised by the Serial RX engine if the...
|
||||
// 0x02000000 [25] BIT_STUFF_ERROR (0) Bit Stuff Error
|
||||
// 0x01000000 [24] CRC_ERROR (0) CRC Error
|
||||
// 0x00080000 [19] BUS_RESET (0) Device: bus reset received
|
||||
// 0x00040000 [18] TRANS_COMPLETE (0) Transaction complete
|
||||
// 0x00020000 [17] SETUP_REC (0) Device: Setup packet received
|
||||
// 0x00010000 [16] CONNECTED (0) Device: connected
|
||||
// 0x00000800 [11] RESUME (0) Host: Device has initiated a remote resume
|
||||
// 0x00000400 [10] VBUS_OVER_CURR (0) VBUS over current detected
|
||||
// 0x00000300 [9:8] SPEED (0x0) Host: device speed
|
||||
// 0x00000010 [4] SUSPENDED (0) Bus in suspended state
|
||||
// 0x0000000c [3:2] LINE_STATE (0x0) USB bus line state
|
||||
// 0x00000001 [0] VBUS_DETECTED (0) Device: VBUS Detected
|
||||
io_rw_32 sie_status;
|
||||
|
||||
_REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL
|
||||
// interrupt endpoint control register
|
||||
// 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 => 15
|
||||
io_rw_32 int_ep_ctrl;
|
||||
|
||||
_REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS
|
||||
// Buffer status register
|
||||
// 0x80000000 [31] EP15_OUT (0)
|
||||
// 0x40000000 [30] EP15_IN (0)
|
||||
// 0x20000000 [29] EP14_OUT (0)
|
||||
// 0x10000000 [28] EP14_IN (0)
|
||||
// 0x08000000 [27] EP13_OUT (0)
|
||||
// 0x04000000 [26] EP13_IN (0)
|
||||
// 0x02000000 [25] EP12_OUT (0)
|
||||
// 0x01000000 [24] EP12_IN (0)
|
||||
// 0x00800000 [23] EP11_OUT (0)
|
||||
// 0x00400000 [22] EP11_IN (0)
|
||||
// 0x00200000 [21] EP10_OUT (0)
|
||||
// 0x00100000 [20] EP10_IN (0)
|
||||
// 0x00080000 [19] EP9_OUT (0)
|
||||
// 0x00040000 [18] EP9_IN (0)
|
||||
// 0x00020000 [17] EP8_OUT (0)
|
||||
// 0x00010000 [16] EP8_IN (0)
|
||||
// 0x00008000 [15] EP7_OUT (0)
|
||||
// 0x00004000 [14] EP7_IN (0)
|
||||
// 0x00002000 [13] EP6_OUT (0)
|
||||
// 0x00001000 [12] EP6_IN (0)
|
||||
// 0x00000800 [11] EP5_OUT (0)
|
||||
// 0x00000400 [10] EP5_IN (0)
|
||||
// 0x00000200 [9] EP4_OUT (0)
|
||||
// 0x00000100 [8] EP4_IN (0)
|
||||
// 0x00000080 [7] EP3_OUT (0)
|
||||
// 0x00000040 [6] EP3_IN (0)
|
||||
// 0x00000020 [5] EP2_OUT (0)
|
||||
// 0x00000010 [4] EP2_IN (0)
|
||||
// 0x00000008 [3] EP1_OUT (0)
|
||||
// 0x00000004 [2] EP1_IN (0)
|
||||
// 0x00000002 [1] EP0_OUT (0)
|
||||
// 0x00000001 [0] EP0_IN (0)
|
||||
io_rw_32 buf_status;
|
||||
|
||||
_REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE
|
||||
// Which of the double buffers should be handled
|
||||
// 0x80000000 [31] EP15_OUT (0)
|
||||
// 0x40000000 [30] EP15_IN (0)
|
||||
// 0x20000000 [29] EP14_OUT (0)
|
||||
// 0x10000000 [28] EP14_IN (0)
|
||||
// 0x08000000 [27] EP13_OUT (0)
|
||||
// 0x04000000 [26] EP13_IN (0)
|
||||
// 0x02000000 [25] EP12_OUT (0)
|
||||
// 0x01000000 [24] EP12_IN (0)
|
||||
// 0x00800000 [23] EP11_OUT (0)
|
||||
// 0x00400000 [22] EP11_IN (0)
|
||||
// 0x00200000 [21] EP10_OUT (0)
|
||||
// 0x00100000 [20] EP10_IN (0)
|
||||
// 0x00080000 [19] EP9_OUT (0)
|
||||
// 0x00040000 [18] EP9_IN (0)
|
||||
// 0x00020000 [17] EP8_OUT (0)
|
||||
// 0x00010000 [16] EP8_IN (0)
|
||||
// 0x00008000 [15] EP7_OUT (0)
|
||||
// 0x00004000 [14] EP7_IN (0)
|
||||
// 0x00002000 [13] EP6_OUT (0)
|
||||
// 0x00001000 [12] EP6_IN (0)
|
||||
// 0x00000800 [11] EP5_OUT (0)
|
||||
// 0x00000400 [10] EP5_IN (0)
|
||||
// 0x00000200 [9] EP4_OUT (0)
|
||||
// 0x00000100 [8] EP4_IN (0)
|
||||
// 0x00000080 [7] EP3_OUT (0)
|
||||
// 0x00000040 [6] EP3_IN (0)
|
||||
// 0x00000020 [5] EP2_OUT (0)
|
||||
// 0x00000010 [4] EP2_IN (0)
|
||||
// 0x00000008 [3] EP1_OUT (0)
|
||||
// 0x00000004 [2] EP1_IN (0)
|
||||
// 0x00000002 [1] EP0_OUT (0)
|
||||
// 0x00000001 [0] EP0_IN (0)
|
||||
io_ro_32 buf_cpu_should_handle;
|
||||
|
||||
_REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT
|
||||
// Device only: Can be set to ignore the buffer control register for this endpoint in case you...
|
||||
// 0x80000000 [31] EP15_OUT (0)
|
||||
// 0x40000000 [30] EP15_IN (0)
|
||||
// 0x20000000 [29] EP14_OUT (0)
|
||||
// 0x10000000 [28] EP14_IN (0)
|
||||
// 0x08000000 [27] EP13_OUT (0)
|
||||
// 0x04000000 [26] EP13_IN (0)
|
||||
// 0x02000000 [25] EP12_OUT (0)
|
||||
// 0x01000000 [24] EP12_IN (0)
|
||||
// 0x00800000 [23] EP11_OUT (0)
|
||||
// 0x00400000 [22] EP11_IN (0)
|
||||
// 0x00200000 [21] EP10_OUT (0)
|
||||
// 0x00100000 [20] EP10_IN (0)
|
||||
// 0x00080000 [19] EP9_OUT (0)
|
||||
// 0x00040000 [18] EP9_IN (0)
|
||||
// 0x00020000 [17] EP8_OUT (0)
|
||||
// 0x00010000 [16] EP8_IN (0)
|
||||
// 0x00008000 [15] EP7_OUT (0)
|
||||
// 0x00004000 [14] EP7_IN (0)
|
||||
// 0x00002000 [13] EP6_OUT (0)
|
||||
// 0x00001000 [12] EP6_IN (0)
|
||||
// 0x00000800 [11] EP5_OUT (0)
|
||||
// 0x00000400 [10] EP5_IN (0)
|
||||
// 0x00000200 [9] EP4_OUT (0)
|
||||
// 0x00000100 [8] EP4_IN (0)
|
||||
// 0x00000080 [7] EP3_OUT (0)
|
||||
// 0x00000040 [6] EP3_IN (0)
|
||||
// 0x00000020 [5] EP2_OUT (0)
|
||||
// 0x00000010 [4] EP2_IN (0)
|
||||
// 0x00000008 [3] EP1_OUT (0)
|
||||
// 0x00000004 [2] EP1_IN (0)
|
||||
// 0x00000002 [1] EP0_OUT (0)
|
||||
// 0x00000001 [0] EP0_IN (0)
|
||||
io_rw_32 abort;
|
||||
|
||||
_REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE
|
||||
// Device only: Used in conjunction with `EP_ABORT`
|
||||
// 0x80000000 [31] EP15_OUT (0)
|
||||
// 0x40000000 [30] EP15_IN (0)
|
||||
// 0x20000000 [29] EP14_OUT (0)
|
||||
// 0x10000000 [28] EP14_IN (0)
|
||||
// 0x08000000 [27] EP13_OUT (0)
|
||||
// 0x04000000 [26] EP13_IN (0)
|
||||
// 0x02000000 [25] EP12_OUT (0)
|
||||
// 0x01000000 [24] EP12_IN (0)
|
||||
// 0x00800000 [23] EP11_OUT (0)
|
||||
// 0x00400000 [22] EP11_IN (0)
|
||||
// 0x00200000 [21] EP10_OUT (0)
|
||||
// 0x00100000 [20] EP10_IN (0)
|
||||
// 0x00080000 [19] EP9_OUT (0)
|
||||
// 0x00040000 [18] EP9_IN (0)
|
||||
// 0x00020000 [17] EP8_OUT (0)
|
||||
// 0x00010000 [16] EP8_IN (0)
|
||||
// 0x00008000 [15] EP7_OUT (0)
|
||||
// 0x00004000 [14] EP7_IN (0)
|
||||
// 0x00002000 [13] EP6_OUT (0)
|
||||
// 0x00001000 [12] EP6_IN (0)
|
||||
// 0x00000800 [11] EP5_OUT (0)
|
||||
// 0x00000400 [10] EP5_IN (0)
|
||||
// 0x00000200 [9] EP4_OUT (0)
|
||||
// 0x00000100 [8] EP4_IN (0)
|
||||
// 0x00000080 [7] EP3_OUT (0)
|
||||
// 0x00000040 [6] EP3_IN (0)
|
||||
// 0x00000020 [5] EP2_OUT (0)
|
||||
// 0x00000010 [4] EP2_IN (0)
|
||||
// 0x00000008 [3] EP1_OUT (0)
|
||||
// 0x00000004 [2] EP1_IN (0)
|
||||
// 0x00000002 [1] EP0_OUT (0)
|
||||
// 0x00000001 [0] EP0_IN (0)
|
||||
io_rw_32 abort_done;
|
||||
|
||||
_REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM
|
||||
// Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register...
|
||||
// 0x00000002 [1] EP0_OUT (0)
|
||||
// 0x00000001 [0] EP0_IN (0)
|
||||
io_rw_32 ep_stall_arm;
|
||||
|
||||
_REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL
|
||||
// Used by the host controller
|
||||
// 0x03ff0000 [25:16] DELAY_FS (0x010) NAK polling interval for a full speed device
|
||||
// 0x000003ff [9:0] DELAY_LS (0x010) NAK polling interval for a low speed device
|
||||
io_rw_32 nak_poll;
|
||||
|
||||
_REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK
|
||||
// Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set
|
||||
// 0x80000000 [31] EP15_OUT (0)
|
||||
// 0x40000000 [30] EP15_IN (0)
|
||||
// 0x20000000 [29] EP14_OUT (0)
|
||||
// 0x10000000 [28] EP14_IN (0)
|
||||
// 0x08000000 [27] EP13_OUT (0)
|
||||
// 0x04000000 [26] EP13_IN (0)
|
||||
// 0x02000000 [25] EP12_OUT (0)
|
||||
// 0x01000000 [24] EP12_IN (0)
|
||||
// 0x00800000 [23] EP11_OUT (0)
|
||||
// 0x00400000 [22] EP11_IN (0)
|
||||
// 0x00200000 [21] EP10_OUT (0)
|
||||
// 0x00100000 [20] EP10_IN (0)
|
||||
// 0x00080000 [19] EP9_OUT (0)
|
||||
// 0x00040000 [18] EP9_IN (0)
|
||||
// 0x00020000 [17] EP8_OUT (0)
|
||||
// 0x00010000 [16] EP8_IN (0)
|
||||
// 0x00008000 [15] EP7_OUT (0)
|
||||
// 0x00004000 [14] EP7_IN (0)
|
||||
// 0x00002000 [13] EP6_OUT (0)
|
||||
// 0x00001000 [12] EP6_IN (0)
|
||||
// 0x00000800 [11] EP5_OUT (0)
|
||||
// 0x00000400 [10] EP5_IN (0)
|
||||
// 0x00000200 [9] EP4_OUT (0)
|
||||
// 0x00000100 [8] EP4_IN (0)
|
||||
// 0x00000080 [7] EP3_OUT (0)
|
||||
// 0x00000040 [6] EP3_IN (0)
|
||||
// 0x00000020 [5] EP2_OUT (0)
|
||||
// 0x00000010 [4] EP2_IN (0)
|
||||
// 0x00000008 [3] EP1_OUT (0)
|
||||
// 0x00000004 [2] EP1_IN (0)
|
||||
// 0x00000002 [1] EP0_OUT (0)
|
||||
// 0x00000001 [0] EP0_IN (0)
|
||||
io_rw_32 ep_nak_stall_status;
|
||||
|
||||
_REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING
|
||||
// Where to connect the USB controller
|
||||
// 0x00000008 [3] SOFTCON (0)
|
||||
// 0x00000004 [2] TO_DIGITAL_PAD (0)
|
||||
// 0x00000002 [1] TO_EXTPHY (0)
|
||||
// 0x00000001 [0] TO_PHY (0)
|
||||
io_rw_32 muxing;
|
||||
|
||||
_REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR
|
||||
// Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO
|
||||
// 0x00000020 [5] OVERCURR_DETECT_EN (0)
|
||||
// 0x00000010 [4] OVERCURR_DETECT (0)
|
||||
// 0x00000008 [3] VBUS_DETECT_OVERRIDE_EN (0)
|
||||
// 0x00000004 [2] VBUS_DETECT (0)
|
||||
// 0x00000002 [1] VBUS_EN_OVERRIDE_EN (0)
|
||||
// 0x00000001 [0] VBUS_EN (0)
|
||||
io_rw_32 pwr;
|
||||
|
||||
_REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT
|
||||
// Note that most functions are driven directly from usb_fsls controller
|
||||
// 0x00400000 [22] DM_OVV (0) Status bit from USB PHY
|
||||
// 0x00200000 [21] DP_OVV (0) Status bit from USB PHY
|
||||
// 0x00100000 [20] DM_OVCN (0) Status bit from USB PHY
|
||||
// 0x00080000 [19] DP_OVCN (0) Status bit from USB PHY
|
||||
// 0x00040000 [18] RX_DM (0) Status bit from USB PHY +
|
||||
// 0x00020000 [17] RX_DP (0) Status bit from USB PHY +
|
||||
// 0x00010000 [16] RX_DD (0) Status bit from USB PHY +
|
||||
// 0x00008000 [15] TX_DIFFMODE (0)
|
||||
// 0x00004000 [14] TX_FSSLEW (0)
|
||||
// 0x00002000 [13] TX_PD (0)
|
||||
// 0x00001000 [12] RX_PD (0)
|
||||
// 0x00000800 [11] TX_DM (0) Value to drive to USB PHY when override enable is set...
|
||||
// 0x00000400 [10] TX_DP (0) Value to drive to USB PHY when override enable is set...
|
||||
// 0x00000200 [9] TX_DM_OE (0) Value to drive to USB PHY when override enable is set...
|
||||
// 0x00000100 [8] TX_DP_OE (0) Value to drive to USB PHY when override enable is set...
|
||||
// 0x00000040 [6] DM_PULLDN_EN (0) Value to drive to USB PHY when override enable is set...
|
||||
// 0x00000020 [5] DM_PULLUP_EN (0) Value to drive to USB PHY when override enable is set...
|
||||
// 0x00000010 [4] DM_PULLUP_HISEL (0) when dm_pullup_en is set high, this enables second resistor
|
||||
// 0x00000004 [2] DP_PULLDN_EN (0) Value to drive to USB PHY when override enable is set...
|
||||
// 0x00000002 [1] DP_PULLUP_EN (0) Value to drive to USB PHY when override enable is set...
|
||||
// 0x00000001 [0] DP_PULLUP_HISEL (0) when dp_pullup_en is set high, this enables second resistor
|
||||
io_rw_32 phy_direct;
|
||||
|
||||
_REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE
|
||||
// 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0)
|
||||
// 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0)
|
||||
// 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0)
|
||||
// 0x00000400 [10] TX_PD_OVERRIDE_EN (0)
|
||||
// 0x00000200 [9] RX_PD_OVERRIDE_EN (0)
|
||||
// 0x00000100 [8] TX_DM_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
|
||||
// 0x00000080 [7] TX_DP_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
|
||||
// 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
|
||||
// 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
|
||||
// 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
|
||||
// 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
|
||||
// 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
|
||||
// 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0)
|
||||
// 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0)
|
||||
io_rw_32 phy_direct_override;
|
||||
|
||||
_REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM
|
||||
// Note that most functions are driven directly from usb_fsls controller
|
||||
// 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY +
|
||||
// 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY +
|
||||
io_rw_32 phy_trim;
|
||||
|
||||
uint32_t _pad0;
|
||||
|
||||
_REG_(USB_INTR_OFFSET) // USB_INTR
|
||||
// Raw Interrupts
|
||||
// 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
|
||||
// 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
|
||||
// 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
|
||||
// 0x00010000 [16] SETUP_REQ (0) Device
|
||||
// 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
|
||||
// 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
|
||||
// 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
|
||||
// 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
|
||||
// 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
|
||||
// 0x00000400 [10] STALL (0) Source: SIE_STATUS
|
||||
// 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
|
||||
// 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
|
||||
// 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
|
||||
// 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
|
||||
// 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
|
||||
// 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
|
||||
// 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
|
||||
// 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
|
||||
// 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
|
||||
// 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
|
||||
io_ro_32 intr;
|
||||
|
||||
_REG_(USB_INTE_OFFSET) // USB_INTE
|
||||
// Interrupt Enable
|
||||
// 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
|
||||
// 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
|
||||
// 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
|
||||
// 0x00010000 [16] SETUP_REQ (0) Device
|
||||
// 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
|
||||
// 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
|
||||
// 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
|
||||
// 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
|
||||
// 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
|
||||
// 0x00000400 [10] STALL (0) Source: SIE_STATUS
|
||||
// 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
|
||||
// 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
|
||||
// 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
|
||||
// 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
|
||||
// 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
|
||||
// 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
|
||||
// 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
|
||||
// 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
|
||||
// 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
|
||||
// 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
|
||||
io_rw_32 inte;
|
||||
|
||||
_REG_(USB_INTF_OFFSET) // USB_INTF
|
||||
// Interrupt Force
|
||||
// 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
|
||||
// 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
|
||||
// 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
|
||||
// 0x00010000 [16] SETUP_REQ (0) Device
|
||||
// 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
|
||||
// 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
|
||||
// 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
|
||||
// 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
|
||||
// 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
|
||||
// 0x00000400 [10] STALL (0) Source: SIE_STATUS
|
||||
// 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
|
||||
// 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
|
||||
// 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
|
||||
// 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
|
||||
// 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
|
||||
// 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
|
||||
// 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
|
||||
// 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
|
||||
// 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
|
||||
// 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
|
||||
io_rw_32 intf;
|
||||
|
||||
_REG_(USB_INTS_OFFSET) // USB_INTS
|
||||
// Interrupt status after masking & forcing
|
||||
// 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
|
||||
// 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
|
||||
// 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
|
||||
// 0x00010000 [16] SETUP_REQ (0) Device
|
||||
// 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
|
||||
// 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
|
||||
// 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
|
||||
// 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
|
||||
// 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
|
||||
// 0x00000400 [10] STALL (0) Source: SIE_STATUS
|
||||
// 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
|
||||
// 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
|
||||
// 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
|
||||
// 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
|
||||
// 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
|
||||
// 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
|
||||
// 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
|
||||
// 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
|
||||
// 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
|
||||
// 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
|
||||
io_ro_32 ints;
|
||||
} usb_hw_t;
|
||||
|
||||
#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE)
|
||||
static_assert(sizeof (usb_hw_t) == 0x009c, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_USB_H
|
||||
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _HARDWARE_STRUCTS_USB_DPRAM_H
|
||||
#define _HARDWARE_STRUCTS_USB_DPRAM_H
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/usb.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/usb.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
|
||||
// 0-15
|
||||
#define USB_NUM_ENDPOINTS 16
|
||||
|
||||
// allow user to restrict number of endpoints available to save RAN
|
||||
#ifndef USB_MAX_ENDPOINTS
|
||||
#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS
|
||||
#endif
|
||||
|
||||
// 1-15
|
||||
#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1)
|
||||
|
||||
// Endpoint buffer control bits
|
||||
#define USB_BUF_CTRL_FULL 0x00008000u
|
||||
#define USB_BUF_CTRL_LAST 0x00004000u
|
||||
#define USB_BUF_CTRL_DATA0_PID 0x00000000u
|
||||
#define USB_BUF_CTRL_DATA1_PID 0x00002000u
|
||||
#define USB_BUF_CTRL_SEL 0x00001000u
|
||||
#define USB_BUF_CTRL_STALL 0x00000800u
|
||||
#define USB_BUF_CTRL_AVAIL 0x00000400u
|
||||
#define USB_BUF_CTRL_LEN_MASK 0x000003FFu
|
||||
#define USB_BUF_CTRL_LEN_LSB 0
|
||||
|
||||
// ep_inout_ctrl bits
|
||||
#define EP_CTRL_ENABLE_BITS (1u << 31u)
|
||||
#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30)
|
||||
#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29)
|
||||
#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28)
|
||||
#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16)
|
||||
#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17)
|
||||
#define EP_CTRL_BUFFER_TYPE_LSB 26u
|
||||
#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u
|
||||
|
||||
#define USB_DPRAM_SIZE 4096u
|
||||
|
||||
// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb
|
||||
// Allow user to claim some of the USB RAM for themselves
|
||||
#ifndef USB_DPRAM_MAX
|
||||
#define USB_DPRAM_MAX USB_DPRAM_SIZE
|
||||
#endif
|
||||
|
||||
// Define maximum packet sizes
|
||||
#define USB_MAX_ISO_PACKET_SIZE 1023
|
||||
#define USB_MAX_PACKET_SIZE 64
|
||||
|
||||
typedef struct {
|
||||
// 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
|
||||
volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
|
||||
|
||||
// Starts at ep1
|
||||
struct usb_device_dpram_ep_ctrl {
|
||||
io_rw_32 in;
|
||||
io_rw_32 out;
|
||||
} ep_ctrl[USB_NUM_ENDPOINTS - 1];
|
||||
|
||||
// Starts at ep0
|
||||
struct usb_device_dpram_ep_buf_ctrl {
|
||||
io_rw_32 in;
|
||||
io_rw_32 out;
|
||||
} ep_buf_ctrl[USB_NUM_ENDPOINTS];
|
||||
|
||||
// EP0 buffers are fixed. Assumes single buffered mode for EP0
|
||||
uint8_t ep0_buf_a[0x40];
|
||||
uint8_t ep0_buf_b[0x40];
|
||||
|
||||
// Rest of DPRAM can be carved up as needed
|
||||
uint8_t epx_data[USB_DPRAM_MAX - 0x180];
|
||||
} usb_device_dpram_t;
|
||||
|
||||
static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, "");
|
||||
static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, "");
|
||||
|
||||
typedef struct {
|
||||
// 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
|
||||
volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
|
||||
|
||||
// Interrupt endpoint control 1 -> 15
|
||||
struct usb_host_dpram_ep_ctrl {
|
||||
io_rw_32 ctrl;
|
||||
io_rw_32 spare;
|
||||
} int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
|
||||
|
||||
io_rw_32 epx_buf_ctrl;
|
||||
io_rw_32 _spare0;
|
||||
|
||||
// Interrupt endpoint buffer control
|
||||
struct usb_host_dpram_ep_buf_ctrl {
|
||||
io_rw_32 ctrl;
|
||||
io_rw_32 spare;
|
||||
} int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
|
||||
|
||||
io_rw_32 epx_ctrl;
|
||||
|
||||
uint8_t _spare1[124];
|
||||
|
||||
// Should start at 0x180
|
||||
uint8_t epx_data[USB_DPRAM_MAX - 0x180];
|
||||
} usb_host_dpram_t;
|
||||
|
||||
static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, "");
|
||||
static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, "");
|
||||
|
||||
#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE)
|
||||
#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE)
|
||||
|
||||
static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_USB_DPRAM_H
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
|
||||
#define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
|
||||
|
||||
/**
|
||||
* \file rp2040/vreg_and_chip_reset.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/vreg_and_chip_reset.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_vreg_and_chip_reset
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/vreg_and_chip_reset.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(VREG_AND_CHIP_RESET_VREG_OFFSET) // VREG_AND_CHIP_RESET_VREG
|
||||
// Voltage regulator control and status
|
||||
// 0x00001000 [12] ROK (0) regulation status +
|
||||
// 0x000000f0 [7:4] VSEL (0xb) output voltage select +
|
||||
// 0x00000002 [1] HIZ (0) high impedance mode select +
|
||||
// 0x00000001 [0] EN (1) enable +
|
||||
io_rw_32 vreg;
|
||||
|
||||
_REG_(VREG_AND_CHIP_RESET_BOD_OFFSET) // VREG_AND_CHIP_RESET_BOD
|
||||
// brown-out detection control
|
||||
// 0x000000f0 [7:4] VSEL (0x9) threshold select +
|
||||
// 0x00000001 [0] EN (1) enable +
|
||||
io_rw_32 bod;
|
||||
|
||||
_REG_(VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET) // VREG_AND_CHIP_RESET_CHIP_RESET
|
||||
// Chip reset control and status
|
||||
// 0x01000000 [24] PSM_RESTART_FLAG (0) This is set by psm_restart from the debugger
|
||||
// 0x00100000 [20] HAD_PSM_RESTART (0) Last reset was from the debug port
|
||||
// 0x00010000 [16] HAD_RUN (0) Last reset was from the RUN pin
|
||||
// 0x00000100 [8] HAD_POR (0) Last reset was from the power-on reset or brown-out...
|
||||
io_rw_32 chip_reset;
|
||||
} vreg_and_chip_reset_hw_t;
|
||||
|
||||
#define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *)VREG_AND_CHIP_RESET_BASE)
|
||||
static_assert(sizeof (vreg_and_chip_reset_hw_t) == 0x000c, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
|
||||
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_WATCHDOG_H
|
||||
#define _HARDWARE_STRUCTS_WATCHDOG_H
|
||||
|
||||
/**
|
||||
* \file rp2040/watchdog.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/watchdog.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL
|
||||
// Watchdog control
|
||||
// 0x80000000 [31] TRIGGER (0) Trigger a watchdog reset
|
||||
// 0x40000000 [30] ENABLE (0) When not enabled the watchdog timer is paused
|
||||
// 0x04000000 [26] PAUSE_DBG1 (1) Pause the watchdog timer when processor 1 is in debug mode
|
||||
// 0x02000000 [25] PAUSE_DBG0 (1) Pause the watchdog timer when processor 0 is in debug mode
|
||||
// 0x01000000 [24] PAUSE_JTAG (1) Pause the watchdog timer when JTAG is accessing the bus fabric
|
||||
// 0x00ffffff [23:0] TIME (0x000000) Indicates the number of ticks / 2 (see errata RP2040-E1)...
|
||||
io_rw_32 ctrl;
|
||||
|
||||
_REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD
|
||||
// Load the watchdog timer.
|
||||
// 0x00ffffff [23:0] LOAD (0x000000)
|
||||
io_wo_32 load;
|
||||
|
||||
_REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON
|
||||
// Logs the reason for the last reset.
|
||||
// 0x00000002 [1] FORCE (0)
|
||||
// 0x00000001 [0] TIMER (0)
|
||||
io_ro_32 reason;
|
||||
|
||||
// (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes)
|
||||
_REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0
|
||||
// Scratch register
|
||||
// 0xffffffff [31:0] SCRATCH0 (0x00000000)
|
||||
io_rw_32 scratch[8];
|
||||
|
||||
_REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK
|
||||
// Controls the tick generator
|
||||
// 0x000ff800 [19:11] COUNT (-) Count down timer: the remaining number clk_tick cycles...
|
||||
// 0x00000400 [10] RUNNING (-) Is the tick generator running?
|
||||
// 0x00000200 [9] ENABLE (1) start / stop tick generation
|
||||
// 0x000001ff [8:0] CYCLES (0x000) Total number of clk_tick cycles before the next tick
|
||||
io_rw_32 tick;
|
||||
} watchdog_hw_t;
|
||||
|
||||
#define watchdog_hw ((watchdog_hw_t *)WATCHDOG_BASE)
|
||||
static_assert(sizeof (watchdog_hw_t) == 0x0030, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_WATCHDOG_H
|
||||
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_XIP_H
|
||||
#define _HARDWARE_STRUCTS_XIP_H
|
||||
|
||||
/**
|
||||
* \file rp2040/xip.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/xip.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/xip.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
typedef struct {
|
||||
_REG_(XIP_CTRL_OFFSET) // XIP_CTRL
|
||||
// Cache control
|
||||
// 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down
|
||||
// 0x00000002 [1] ERR_BADWRITE (1) When 1, writes to any alias other than 0x0 (caching,...
|
||||
// 0x00000001 [0] EN (1) When 1, enable the cache
|
||||
io_rw_32 ctrl;
|
||||
|
||||
_REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH
|
||||
// Cache Flush control
|
||||
// 0x00000001 [0] FLUSH (0) Write 1 to flush the cache
|
||||
io_wo_32 flush;
|
||||
|
||||
_REG_(XIP_STAT_OFFSET) // XIP_STAT
|
||||
// Cache Status
|
||||
// 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full
|
||||
// 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty
|
||||
// 0x00000001 [0] FLUSH_READY (0) Reads as 0 while a cache flush is in progress, and 1 otherwise
|
||||
io_ro_32 stat;
|
||||
|
||||
_REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT
|
||||
// Cache Hit counter
|
||||
// 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each...
|
||||
io_rw_32 ctr_hit;
|
||||
|
||||
_REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC
|
||||
// Cache Access counter
|
||||
// 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each...
|
||||
io_rw_32 ctr_acc;
|
||||
|
||||
_REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR
|
||||
// FIFO stream address
|
||||
// 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash...
|
||||
io_rw_32 stream_addr;
|
||||
|
||||
_REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR
|
||||
// FIFO stream control
|
||||
// 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read
|
||||
io_rw_32 stream_ctr;
|
||||
|
||||
_REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO
|
||||
// FIFO stream data
|
||||
// 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA
|
||||
io_ro_32 stream_fifo;
|
||||
} xip_ctrl_hw_t;
|
||||
|
||||
#define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE)
|
||||
static_assert(sizeof (xip_ctrl_hw_t) == 0x0020, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_XIP_H
|
||||
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
// Support old header for compatibility (and if included, support old variable name)
|
||||
#include "hardware/structs/xip.h"
|
||||
#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS
|
||||
#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS
|
||||
#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
|
||||
|
||||
/**
|
||||
* Copyright (c) 2024 Raspberry Pi Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _HARDWARE_STRUCTS_XOSC_H
|
||||
#define _HARDWARE_STRUCTS_XOSC_H
|
||||
|
||||
/**
|
||||
* \file rp2040/xosc.h
|
||||
*/
|
||||
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/xosc.h"
|
||||
|
||||
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xosc
|
||||
//
|
||||
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
|
||||
// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h.
|
||||
//
|
||||
// Bit-field descriptions are of the form:
|
||||
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
|
||||
|
||||
/// \tag::xosc_hw[]
|
||||
typedef struct {
|
||||
_REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL
|
||||
// Crystal Oscillator Control
|
||||
// 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to DISABLE and the...
|
||||
// 0x00000fff [11:0] FREQ_RANGE (-) Frequency range
|
||||
io_rw_32 ctrl;
|
||||
|
||||
_REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS
|
||||
// Crystal Oscillator Status
|
||||
// 0x80000000 [31] STABLE (0) Oscillator is running and stable
|
||||
// 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or...
|
||||
// 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and...
|
||||
// 0x00000003 [1:0] FREQ_RANGE (-) The current frequency range setting, always reads 0
|
||||
io_rw_32 status;
|
||||
|
||||
_REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT
|
||||
// Crystal Oscillator pause control
|
||||
// 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the XOSC +
|
||||
io_rw_32 dormant;
|
||||
|
||||
_REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP
|
||||
// Controls the startup delay
|
||||
// 0x00100000 [20] X4 (-) Multiplies the startup_delay by 4
|
||||
// 0x00003fff [13:0] DELAY (-) in multiples of 256*xtal_period
|
||||
io_rw_32 startup;
|
||||
|
||||
uint32_t _pad0[3];
|
||||
|
||||
_REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT
|
||||
// A down counter running at the XOSC frequency which counts to zero and stops.
|
||||
// 0x000000ff [7:0] COUNT (0x00)
|
||||
io_rw_32 count;
|
||||
} xosc_hw_t;
|
||||
/// \end::xosc_hw[]
|
||||
|
||||
#define xosc_hw ((xosc_hw_t *)XOSC_BASE)
|
||||
static_assert(sizeof (xosc_hw_t) == 0x0020, "");
|
||||
|
||||
#endif // _HARDWARE_STRUCTS_XOSC_H
|
||||
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "pico.h"
|
||||
|
||||
# note we don't do this by default in this file for backwards comaptibility with user code
|
||||
# that may include this file, but not use unified syntax. Note that this macro does equivalent
|
||||
# setup to the pico_default_asm macro for inline assembly in C code.
|
||||
.macro pico_default_asm_setup
|
||||
.syntax unified
|
||||
.cpu cortex-m0plus
|
||||
.thumb
|
||||
.endm
|
||||
|
||||
// do not put align in here as it is used mid function sometimes
|
||||
.macro regular_func x
|
||||
.global \x
|
||||
.type \x,%function
|
||||
.thumb_func
|
||||
\x:
|
||||
.endm
|
||||
|
||||
.macro weak_func x
|
||||
.weak \x
|
||||
.type \x,%function
|
||||
.thumb_func
|
||||
\x:
|
||||
.endm
|
||||
|
||||
.macro regular_func_with_section x
|
||||
.section .text.\x
|
||||
regular_func \x
|
||||
.endm
|
||||
|
||||
// do not put align in here as it is used mid function sometimes
|
||||
.macro wrapper_func x
|
||||
regular_func WRAPPER_FUNC_NAME(\x)
|
||||
.endm
|
||||
|
||||
.macro weak_wrapper_func x
|
||||
weak_func WRAPPER_FUNC_NAME(\x)
|
||||
.endm
|
||||
|
||||
# backwards compatibility
|
||||
.macro __pre_init func, priority_string
|
||||
.section .preinit_array.\priority_string
|
||||
.p2align 2
|
||||
.word \func
|
||||
.endm
|
||||
210
lib/main/pico-sdk/rp2040/pico_platform/include/pico/platform.h
Normal file
210
lib/main/pico-sdk/rp2040/pico_platform/include/pico/platform.h
Normal file
|
|
@ -0,0 +1,210 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/** \file platform.h
|
||||
* \defgroup pico_platform pico_platform
|
||||
*
|
||||
* \brief Macros and definitions (and functions when included by non assembly code) for the RP2 family device / architecture
|
||||
* to provide a common abstraction over low level compiler / platform specifics
|
||||
*
|
||||
* This header may be included by assembly code
|
||||
*/
|
||||
|
||||
#ifndef _PICO_PLATFORM_H
|
||||
#define _PICO_PLATFORM_H
|
||||
|
||||
#ifndef _PICO_H
|
||||
#error pico/platform.h should not be included directly; include pico.h instead
|
||||
#endif
|
||||
|
||||
#include "pico/platform/compiler.h"
|
||||
#include "pico/platform/sections.h"
|
||||
#include "pico/platform/panic.h"
|
||||
#include "hardware/regs/addressmap.h"
|
||||
#include "hardware/regs/sio.h"
|
||||
|
||||
// PICO_CONFIG: PICO_STACK_SIZE, Minimum amount of stack space reserved in the linker script for each core. See also PICO_CORE1_STACK_SIZE, min=0x100, default=0x800, advanced=true, group=pico_platform
|
||||
#ifndef PICO_STACK_SIZE
|
||||
#define PICO_STACK_SIZE _u(0x800)
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: PICO_HEAP_SIZE, Minimum amount of heap space reserved by the linker script, min=0x100, default=0x800, advanced=true, group=pico_platform
|
||||
#ifndef PICO_HEAP_SIZE
|
||||
#define PICO_HEAP_SIZE _u(0x800)
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform
|
||||
#ifndef PICO_NO_RAM_VECTOR_TABLE
|
||||
#define PICO_NO_RAM_VECTOR_TABLE 0
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: PICO_RP2040_B0_SUPPORTED, Whether to include any specific software support for RP2040 B0 revision, type=bool, default=1, advanced=true, group=pico_platform
|
||||
#ifndef PICO_RP2040_B0_SUPPORTED
|
||||
#define PICO_RP2040_B0_SUPPORTED 1
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: PICO_FLOAT_SUPPORT_ROM_V1, Include float support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform
|
||||
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
|
||||
#define PICO_FLOAT_SUPPORT_ROM_V1 1
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: PICO_DOUBLE_SUPPORT_ROM_V1, Include double support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform
|
||||
#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
|
||||
#define PICO_DOUBLE_SUPPORT_ROM_V1 1
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: PICO_RP2040_B1_SUPPORTED, Whether to include any specific software support for RP2040 B1 revision, type=bool, default=1, advanced=true, group=pico_platform
|
||||
#ifndef PICO_RP2040_B1_SUPPORTED
|
||||
#define PICO_RP2040_B1_SUPPORTED 1
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: PICO_RP2040_B2_SUPPORTED, Whether to include any specific software support for RP2040 B2 revision, type=bool, default=1, advanced=true, group=pico_platform
|
||||
#ifndef PICO_RP2040_B2_SUPPORTED
|
||||
#define PICO_RP2040_B2_SUPPORTED 1
|
||||
#endif
|
||||
|
||||
#ifndef PICO_RAM_VECTOR_TABLE_SIZE
|
||||
#define PICO_RAM_VECTOR_TABLE_SIZE (VTABLE_FIRST_IRQ + NUM_IRQS)
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
/*! \brief No-op function for the body of tight loops
|
||||
* \ingroup pico_platform
|
||||
*
|
||||
* No-op function intended to be called by any tight hardware polling loop. Using this ubiquitously
|
||||
* makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup
|
||||
* debugging might be added
|
||||
*/
|
||||
static __force_inline void tight_loop_contents(void) {}
|
||||
|
||||
/*! \brief Helper method to busy-wait for at least the given number of cycles
|
||||
* \ingroup pico_platform
|
||||
*
|
||||
* This method is useful for introducing very short delays.
|
||||
*
|
||||
* This method busy-waits in a tight loop for the given number of system clock cycles. The total wait time is only accurate to within 2 cycles,
|
||||
* and this method uses a loop counter rather than a hardware timer, so the method will always take longer than expected if an
|
||||
* interrupt is handled on the calling core during the busy-wait; you can of course disable interrupts to prevent this.
|
||||
*
|
||||
* You can use \ref clock_get_hz(clk_sys) to determine the number of clock cycles per second if you want to convert an actual
|
||||
* time duration to a number of cycles.
|
||||
*
|
||||
* \param minimum_cycles the minimum number of system clock cycles to delay for
|
||||
*/
|
||||
static inline void busy_wait_at_least_cycles(uint32_t minimum_cycles) {
|
||||
pico_default_asm_volatile(
|
||||
"1: subs %0, #3\n"
|
||||
"bcs 1b\n"
|
||||
: "+l" (minimum_cycles) : : "cc", "memory"
|
||||
);
|
||||
}
|
||||
|
||||
// PICO_CONFIG: PICO_NO_FPGA_CHECK, Remove the FPGA platform check for small code size reduction, type=bool, default=1, advanced=true, group=pico_runtime
|
||||
#ifndef PICO_NO_FPGA_CHECK
|
||||
#define PICO_NO_FPGA_CHECK 1
|
||||
#endif
|
||||
|
||||
#if PICO_NO_FPGA_CHECK
|
||||
static inline bool running_on_fpga(void) {return false;}
|
||||
#else
|
||||
bool running_on_fpga(void);
|
||||
#endif
|
||||
|
||||
/*! \brief Execute a breakpoint instruction
|
||||
* \ingroup pico_platform
|
||||
*/
|
||||
static __force_inline void __breakpoint(void) {
|
||||
pico_default_asm_volatile ("bkpt #0" : : : "memory");
|
||||
}
|
||||
|
||||
/*! \brief Get the current core number
|
||||
* \ingroup pico_platform
|
||||
*
|
||||
* \return The core number the call was made from
|
||||
*/
|
||||
__force_inline static uint get_core_num(void) {
|
||||
return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET));
|
||||
}
|
||||
|
||||
/*! \brief Get the current exception level on this core
|
||||
* \ingroup pico_platform
|
||||
*
|
||||
* On Cortex-M this is the exception number defined in the architecture
|
||||
* reference, which is equal to VTABLE_FIRST_IRQ + irq num if inside an
|
||||
* interrupt handler. (VTABLE_FIRST_IRQ is defined in platform_defs.h).
|
||||
*
|
||||
* On Hazard3, this function returns VTABLE_FIRST_IRQ + irq num if inside of
|
||||
* an external IRQ handler (or a fault from such a handler), and 0 otherwise,
|
||||
* generally aligning with the Cortex-M values.
|
||||
*
|
||||
* \return the exception number if the CPU is handling an exception, or 0 otherwise
|
||||
*/
|
||||
static __force_inline uint __get_current_exception(void) {
|
||||
uint exception;
|
||||
pico_default_asm_volatile ( "mrs %0, ipsr" : "=l" (exception));
|
||||
return exception;
|
||||
}
|
||||
|
||||
#define host_safe_hw_ptr(x) ((uintptr_t)(x))
|
||||
#define native_safe_hw_ptr(x) host_safe_hw_ptr(x)
|
||||
|
||||
/*! \brief Returns the RP2040 chip revision number
|
||||
* \ingroup pico_platform
|
||||
* @return the RP2040 chip revision number (1 for B0/B1, 2 for B2)
|
||||
*/
|
||||
uint8_t rp2040_chip_version(void);
|
||||
|
||||
/*! \brief Returns the RP2040 rom version number
|
||||
* \ingroup pico_platform
|
||||
* @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2)
|
||||
*/
|
||||
static inline uint8_t rp2040_rom_version(void) {
|
||||
GCC_Pragma("GCC diagnostic push")
|
||||
GCC_Pragma("GCC diagnostic ignored \"-Warray-bounds\"")
|
||||
return *(uint8_t*)0x13;
|
||||
GCC_Pragma("GCC diagnostic pop")
|
||||
}
|
||||
|
||||
/*! \brief Multiply two integers using an assembly `MUL` instruction
|
||||
* \ingroup pico_platform
|
||||
*
|
||||
* This multiplies a by b using multiply instruction using the ARM mul instruction regardless of values (the compiler
|
||||
* might otherwise choose to perform shifts/adds), i.e. this is a 1 cycle operation.
|
||||
*
|
||||
* \param a the first operand
|
||||
* \param b the second operand
|
||||
* \return a * b
|
||||
*/
|
||||
__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) {
|
||||
#ifdef __riscv
|
||||
__asm ("mul %0, %0, %1" : "+l" (a) : "l" (b) : );
|
||||
#else
|
||||
pico_default_asm ("muls %0, %1" : "+l" (a) : "l" (b) : "cc");
|
||||
#endif
|
||||
return a;
|
||||
}
|
||||
|
||||
/*! \brief multiply two integer values using the fastest method possible
|
||||
* \ingroup pico_platform
|
||||
*
|
||||
* Efficiently multiplies value a by possibly constant value b.
|
||||
*
|
||||
* If b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default
|
||||
* which is often a slow combination of shifts and adds. If b is a power of 2 then a single shift is of course preferable
|
||||
* and will be used
|
||||
*
|
||||
* \param a the first operand
|
||||
* \param b the second operand
|
||||
* \return a * b
|
||||
*/
|
||||
#define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \
|
||||
(__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \
|
||||
(a)*(b))
|
||||
|
||||
#endif // __ASSEMBLER__
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/** \file platform.h
|
||||
* \defgroup pico_platform pico_platform
|
||||
*
|
||||
* \brief Macros and definitions for accessing the CPU registers
|
||||
*
|
||||
* This header may be included by assembly code
|
||||
*/
|
||||
|
||||
#ifndef _PICO_PLATFORM_CPU_REGS_H
|
||||
#define _PICO_PLATFORM_CPU_REGS_H
|
||||
|
||||
#include "hardware/regs/m0plus.h"
|
||||
#define ARM_CPU_PREFIXED(x) M0PLUS_ ## x
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include "hardware/structs/m0plus.h"
|
||||
#define arm_cpu_hw m0plus_hw
|
||||
#include "hardware/structs/nvic.h"
|
||||
#include "hardware/structs/scb.h"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
39
lib/main/pico-sdk/rp2040/pico_platform/platform.c
Normal file
39
lib/main/pico-sdk/rp2040/pico_platform/platform.c
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "pico.h"
|
||||
#include "hardware/address_mapped.h"
|
||||
#include "hardware/regs/tbman.h"
|
||||
#include "hardware/regs/sysinfo.h"
|
||||
|
||||
// Note we leave the FPGA check in by default so that we can run bug repro
|
||||
// binaries coming in from the wild on the FPGA platform. It takes up around
|
||||
// 48 bytes if you include all the calls, so you can pass PICO_NO_FPGA_CHECK=1
|
||||
// to remove it. The FPGA check is used to skip initialisation of hardware
|
||||
// (mainly clock generators and oscillators) that aren't present on FPGA.
|
||||
|
||||
#if !PICO_NO_FPGA_CHECK
|
||||
// Inline stub provided in header if this code is unused (so folding can be
|
||||
// done in each TU instead of relying on LTO)
|
||||
bool running_on_fpga(void) {
|
||||
return (*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_FPGA_BITS;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define MANUFACTURER_RPI 0x927
|
||||
#define PART_RP2 0x2
|
||||
|
||||
uint8_t rp2040_chip_version(void) {
|
||||
// First register of sysinfo is chip id
|
||||
uint32_t chip_id = *((io_ro_32*)(SYSINFO_BASE + SYSINFO_CHIP_ID_OFFSET));
|
||||
uint32_t __unused manufacturer = chip_id & SYSINFO_CHIP_ID_MANUFACTURER_BITS;
|
||||
uint32_t __unused part = (chip_id & SYSINFO_CHIP_ID_PART_BITS) >> SYSINFO_CHIP_ID_PART_LSB;
|
||||
assert(manufacturer == MANUFACTURER_RPI);
|
||||
assert(part == PART_RP2);
|
||||
// Version 1 == B0/B1
|
||||
uint version = (chip_id & SYSINFO_CHIP_ID_REVISION_BITS) >> SYSINFO_CHIP_ID_REVISION_LSB;
|
||||
return (uint8_t)version;
|
||||
}
|
||||
95
lib/main/pico-sdk/rp2040/rp2040_interface_pins.json
Normal file
95
lib/main/pico-sdk/rp2040/rp2040_interface_pins.json
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
{
|
||||
"interfaces": {
|
||||
"UART": {
|
||||
"instances": {
|
||||
"0": {
|
||||
"TX": [0, 12, 16, 28],
|
||||
"RX": [1, 13, 17, 29],
|
||||
"CTS": [2, 14, 18],
|
||||
"RTS": [3, 15, 19]
|
||||
},
|
||||
"1": {
|
||||
"TX": [4, 8, 20, 24],
|
||||
"RX": [5, 9, 21, 25],
|
||||
"CTS": [6, 10, 22, 26],
|
||||
"RTS": [7, 11, 23, 27]
|
||||
}
|
||||
},
|
||||
"expected_functions": {
|
||||
"one_of": ["TX", "RX"]
|
||||
}
|
||||
},
|
||||
"I2C": {
|
||||
"instances": {
|
||||
"0": {
|
||||
"SDA": [0, 4, 8, 12, 16, 20, 24, 28],
|
||||
"SCL": [1, 5, 9, 13, 17, 21, 25, 29]
|
||||
},
|
||||
"1": {
|
||||
"SDA": [2, 6, 10, 14, 18, 22, 26],
|
||||
"SCL": [3, 7, 11, 15, 19, 23, 27]
|
||||
}
|
||||
},
|
||||
"expected_functions": {
|
||||
"required": ["SDA", "SCL"]
|
||||
}
|
||||
},
|
||||
"SPI": {
|
||||
"instances": {
|
||||
"0": {
|
||||
"RX": [0, 4, 16, 20],
|
||||
"CSN": [1, 5, 17, 21],
|
||||
"SCK": [2, 6, 18, 22],
|
||||
"TX": [3, 7, 19, 23]
|
||||
},
|
||||
"1": {
|
||||
"RX": [8, 12, 24, 28],
|
||||
"CSN": [9, 13, 25, 29],
|
||||
"SCK": [10, 14, 26],
|
||||
"TX": [11, 15, 27]
|
||||
}
|
||||
},
|
||||
"expected_functions": {
|
||||
"required": ["SCK"],
|
||||
"one_of": ["RX", "TX"]
|
||||
}
|
||||
},
|
||||
"PWM": {
|
||||
"instances": {
|
||||
"0": {
|
||||
"A": [0, 16],
|
||||
"B": [1, 17]
|
||||
},
|
||||
"1": {
|
||||
"A": [2, 18],
|
||||
"B": [3, 19]
|
||||
},
|
||||
"2": {
|
||||
"A": [4, 20],
|
||||
"B": [5, 21]
|
||||
},
|
||||
"3": {
|
||||
"A": [6, 22],
|
||||
"B": [7, 23]
|
||||
},
|
||||
"4": {
|
||||
"A": [8, 24],
|
||||
"B": [9, 25]
|
||||
},
|
||||
"5": {
|
||||
"A": [10, 26],
|
||||
"B": [11, 27]
|
||||
},
|
||||
"6": {
|
||||
"A": [12, 28],
|
||||
"B": [13, 29]
|
||||
},
|
||||
"7": {
|
||||
"A": [14],
|
||||
"B": [15]
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"pins": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue