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Adding RP2350 SDK and target framework (#13988)
* Adding RP2350 SDK and target framework * Spacing * Removing board definitions
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J Blackman
GitHub
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2dd6f95aad
576 changed files with 435012 additions and 0 deletions
237
lib/main/pico-sdk/rp2_common/hardware_uart/uart.c
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237
lib/main/pico-sdk/rp2_common/hardware_uart/uart.c
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/*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/platform_defs.h"
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#include "hardware/uart.h"
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#include "hardware/structs/uart.h"
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#include "hardware/resets.h"
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#include "hardware/clocks.h"
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static inline uint32_t uart_clock_get_hz(__unused uart_inst_t *inst) {
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return clock_get_hz(UART_CLOCK_NUM(inst));
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}
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#include "hardware/timer.h"
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#include "pico/assert.h"
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#include "pico.h"
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check_hw_layout(uart_hw_t, fr, UART_UARTFR_OFFSET);
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check_hw_layout(uart_hw_t, dmacr, UART_UARTDMACR_OFFSET);
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#if PICO_UART_ENABLE_CRLF_SUPPORT
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short uart_char_to_line_feed[NUM_UARTS];
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#endif
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/// \tag::uart_reset[]
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static inline void uart_reset(uart_inst_t *uart) {
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reset_block_num(uart_get_reset_num(uart));
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}
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static inline void uart_unreset(uart_inst_t *uart) {
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unreset_block_num_wait_blocking(uart_get_reset_num(uart));
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}
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/// \end::uart_reset[]
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/// \tag::uart_init[]
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uint uart_init(uart_inst_t *uart, uint baudrate) {
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invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1);
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if (uart_clock_get_hz(uart) == 0) {
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return 0;
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}
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uart_reset(uart);
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uart_unreset(uart);
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#if PICO_UART_ENABLE_CRLF_SUPPORT
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uart_set_translate_crlf(uart, PICO_UART_DEFAULT_CRLF);
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#endif
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// Any LCR writes need to take place before enabling the UART
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uint baud = uart_set_baudrate(uart, baudrate);
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// inline the uart_set_format() call, as we don't need the CR disable/re-enable
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// protection, and also many people will never call it again, so having
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// the generic function is not useful, and much bigger than this inlined
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// code which is only a handful of instructions.
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//
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// The UART_UARTLCR_H_FEN_BITS setting is combined as well as it is the same register
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#if 0
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uart_set_format(uart, 8, 1, UART_PARITY_NONE);
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// Enable FIFOs (must be before setting UARTEN, as this is an LCR access)
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hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_FEN_BITS);
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#else
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uint data_bits = 8;
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uint stop_bits = 1;
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uint parity = UART_PARITY_NONE;
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hw_write_masked(&uart_get_hw(uart)->lcr_h,
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((data_bits - 5u) << UART_UARTLCR_H_WLEN_LSB) |
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((stop_bits - 1u) << UART_UARTLCR_H_STP2_LSB) |
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(bool_to_bit(parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) |
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(bool_to_bit(parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB) |
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UART_UARTLCR_H_FEN_BITS,
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UART_UARTLCR_H_WLEN_BITS | UART_UARTLCR_H_STP2_BITS |
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UART_UARTLCR_H_PEN_BITS | UART_UARTLCR_H_EPS_BITS |
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UART_UARTLCR_H_FEN_BITS);
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#endif
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// Enable the UART, both TX and RX
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uart_get_hw(uart)->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS;
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#if !PICO_UART_NO_DMACR_ENABLE
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// Always enable DREQ signals -- no harm in this if DMA is not listening
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uart_get_hw(uart)->dmacr = UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS;
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#endif
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return baud;
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}
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/// \end::uart_init[]
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void uart_deinit(uart_inst_t *uart) {
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invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1);
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uart_reset(uart);
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}
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static uint32_t uart_disable_before_lcr_write(uart_inst_t *uart) {
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// Notes from PL011 reference manual:
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//
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// - Before writing the LCR, if the UART is enabled it needs to be
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// disabled and any current TX + RX activity has to be completed
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//
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// - There is a BUSY flag which waits for the current TX char, but this is
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// OR'd with TX FIFO !FULL, so not usable when FIFOs are enabled and
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// potentially nonempty
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//
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// - FIFOs can't be set to disabled whilst a character is in progress
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// (else "FIFO integrity is not guaranteed")
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//
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// Combination of these means there is no general way to halt and poll for
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// end of TX character, if FIFOs may be enabled. Either way, there is no
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// way to poll for end of RX character.
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//
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// So, insert a 15 Baud period delay before changing the settings.
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// 15 Baud is comfortably higher than start + max data + parity + stop.
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// Anything else would require API changes to permit a non-enabled UART
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// state after init() where settings can be changed safely.
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uint32_t cr_save = uart_get_hw(uart)->cr;
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if (cr_save & UART_UARTCR_UARTEN_BITS) {
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hw_clear_bits(&uart_get_hw(uart)->cr,
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UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS);
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uint32_t current_ibrd = uart_get_hw(uart)->ibrd;
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uint32_t current_fbrd = uart_get_hw(uart)->fbrd;
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// Note: Maximise precision here. Show working, the compiler will mop this up.
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// Create a 16.6 fixed-point fractional division ratio; then scale to 32-bits.
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uint32_t brdiv_ratio = 64u * current_ibrd + current_fbrd;
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brdiv_ratio <<= 10;
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// 3662 is ~(15 * 244.14) where 244.14 is 16e6 / 2^16
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uint32_t scaled_freq = uart_clock_get_hz(uart) / 3662ul;
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uint32_t wait_time_us = brdiv_ratio / scaled_freq;
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busy_wait_us(wait_time_us);
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}
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return cr_save;
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}
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static void uart_write_lcr_bits_masked(uart_inst_t *uart, uint32_t values, uint32_t write_mask) {
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invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1);
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// (Potentially) Cleanly handle disabling the UART before touching LCR
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uint32_t cr_save = uart_disable_before_lcr_write(uart);
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hw_write_masked(&uart_get_hw(uart)->lcr_h, values, write_mask);
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uart_get_hw(uart)->cr = cr_save;
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}
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/// \tag::uart_set_baudrate[]
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uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) {
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invalid_params_if(HARDWARE_UART, baudrate == 0);
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uint32_t baud_rate_div = (8 * uart_clock_get_hz(uart) / baudrate) + 1;
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uint32_t baud_ibrd = baud_rate_div >> 7;
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uint32_t baud_fbrd;
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if (baud_ibrd == 0) {
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baud_ibrd = 1;
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baud_fbrd = 0;
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} else if (baud_ibrd >= 65535) {
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baud_ibrd = 65535;
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baud_fbrd = 0;
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} else {
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baud_fbrd = (baud_rate_div & 0x7f) >> 1;
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}
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uart_get_hw(uart)->ibrd = baud_ibrd;
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uart_get_hw(uart)->fbrd = baud_fbrd;
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// PL011 needs a (dummy) LCR_H write to latch in the divisors.
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// We don't want to actually change LCR_H contents here.
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uart_write_lcr_bits_masked(uart, 0, 0);
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// See datasheet
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return (4 * uart_clock_get_hz(uart)) / (64 * baud_ibrd + baud_fbrd);
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}
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/// \end::uart_set_baudrate[]
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void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity) {
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invalid_params_if(HARDWARE_UART, data_bits < 5 || data_bits > 8);
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invalid_params_if(HARDWARE_UART, stop_bits != 1 && stop_bits != 2);
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invalid_params_if(HARDWARE_UART, parity != UART_PARITY_NONE && parity != UART_PARITY_EVEN && parity != UART_PARITY_ODD);
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uart_write_lcr_bits_masked(uart,
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((data_bits - 5u) << UART_UARTLCR_H_WLEN_LSB) |
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((stop_bits - 1u) << UART_UARTLCR_H_STP2_LSB) |
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(bool_to_bit(parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) |
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(bool_to_bit(parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB),
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UART_UARTLCR_H_WLEN_BITS |
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UART_UARTLCR_H_STP2_BITS |
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UART_UARTLCR_H_PEN_BITS |
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UART_UARTLCR_H_EPS_BITS);
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}
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void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled) {
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uint32_t lcr_h_fen_bits = 0;
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if (enabled) {
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lcr_h_fen_bits = UART_UARTLCR_H_FEN_BITS;
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}
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uart_write_lcr_bits_masked(uart, lcr_h_fen_bits, UART_UARTLCR_H_FEN_BITS);
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}
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void uart_set_break(uart_inst_t *uart, bool en) {
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uint32_t lcr_h_brk_bits = 0;
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if (en) {
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lcr_h_brk_bits = UART_UARTLCR_H_BRK_BITS;
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}
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uart_write_lcr_bits_masked(uart, lcr_h_brk_bits, UART_UARTLCR_H_BRK_BITS);
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}
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void uart_set_translate_crlf(uart_inst_t *uart, bool crlf) {
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#if PICO_UART_ENABLE_CRLF_SUPPORT
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uart_char_to_line_feed[uart_get_index(uart)] = crlf ? '\n' : 0x100;
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#else
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panic_unsupported();
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#endif
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}
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bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us) {
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uint32_t t = time_us_32();
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do {
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if (uart_is_readable(uart)) {
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return true;
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}
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} while ((time_us_32() - t) <= us);
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return false;
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}
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