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https://github.com/betaflight/betaflight.git
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commit
30bf9e809f
4 changed files with 72 additions and 9 deletions
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@ -33,7 +33,7 @@
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#define SPI_IO_AF_SCK_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_DOWN)
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#define SPI_IO_AF_SCK_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_DOWN)
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#define SPI_IO_AF_MISO_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_UP)
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#define SPI_IO_AF_MISO_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_UP)
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#define SPI_IO_CS_CFG IO_CONFIG(GPIO_Mode_OUT, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL)
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#define SPI_IO_CS_CFG IO_CONFIG(GPIO_Mode_OUT, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL)
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#elif defined(STM32F7) || defined(STM32H7)
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#elif defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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#define SPI_IO_AF_CFG IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_NOPULL)
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#define SPI_IO_AF_CFG IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_NOPULL)
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#define SPI_IO_AF_SCK_CFG_HIGH IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP)
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#define SPI_IO_AF_SCK_CFG_HIGH IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP)
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#define SPI_IO_AF_SCK_CFG_LOW IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLDOWN)
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#define SPI_IO_AF_SCK_CFG_LOW IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLDOWN)
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@ -67,6 +67,12 @@ typedef enum {
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SPI_CLOCK_STANDARD = 8, //12.00000 MHz
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SPI_CLOCK_STANDARD = 8, //12.00000 MHz
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SPI_CLOCK_FAST = 4, //25.00000 MHz
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SPI_CLOCK_FAST = 4, //25.00000 MHz
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SPI_CLOCK_ULTRAFAST = 2 //50.00000 MHz
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SPI_CLOCK_ULTRAFAST = 2 //50.00000 MHz
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#elif defined(STM32G4)
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// @170MHz
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SPI_CLOCK_SLOW = 128, //00.78125 MHz
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SPI_CLOCK_STANDARD = 16, //10.62500 MHz
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SPI_CLOCK_FAST = 8, //21.25000 MHz
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SPI_CLOCK_ULTRAFAST = 4 //42.50000 MHz
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#else
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#else
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SPI_CLOCK_SLOW = 128, //00.56250 MHz
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SPI_CLOCK_SLOW = 128, //00.56250 MHz
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SPI_CLOCK_STANDARD = 4, //09.00000 MHz
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SPI_CLOCK_STANDARD = 4, //09.00000 MHz
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@ -60,7 +60,7 @@ void spiInitDevice(SPIDevice device, bool leadingEdge)
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IOConfigGPIOAF(IOGetByTag(spi->mosi), SPI_IO_AF_CFG, spi->af);
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IOConfigGPIOAF(IOGetByTag(spi->mosi), SPI_IO_AF_CFG, spi->af);
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#endif
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#endif
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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IOConfigGPIOAF(IOGetByTag(spi->sck), spi->leadingEdge ? SPI_IO_AF_SCK_CFG_LOW : SPI_IO_AF_SCK_CFG_HIGH, spi->sckAF);
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IOConfigGPIOAF(IOGetByTag(spi->sck), spi->leadingEdge ? SPI_IO_AF_SCK_CFG_LOW : SPI_IO_AF_SCK_CFG_HIGH, spi->sckAF);
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IOConfigGPIOAF(IOGetByTag(spi->miso), SPI_IO_AF_MISO_CFG, spi->misoAF);
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IOConfigGPIOAF(IOGetByTag(spi->miso), SPI_IO_AF_MISO_CFG, spi->misoAF);
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IOConfigGPIOAF(IOGetByTag(spi->mosi), SPI_IO_AF_CFG, spi->mosiAF);
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IOConfigGPIOAF(IOGetByTag(spi->mosi), SPI_IO_AF_CFG, spi->mosiAF);
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@ -85,8 +85,10 @@ void spiInitDevice(SPIDevice device, bool leadingEdge)
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spi->hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
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spi->hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
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spi->hspi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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spi->hspi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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spi->hspi.Init.TIMode = SPI_TIMODE_DISABLED;
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spi->hspi.Init.TIMode = SPI_TIMODE_DISABLED;
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#if !defined(STM32G4)
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spi->hspi.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
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spi->hspi.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
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spi->hspi.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE; /* Recommanded setting to avoid glitches */
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spi->hspi.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE; /* Recommanded setting to avoid glitches */
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#endif
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if (spi->leadingEdge) {
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if (spi->leadingEdge) {
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spi->hspi.Init.CLKPolarity = SPI_POLARITY_LOW;
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spi->hspi.Init.CLKPolarity = SPI_POLARITY_LOW;
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@ -20,7 +20,7 @@
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#pragma once
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#pragma once
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#if defined(STM32F1) || defined(STM32F3) || defined(STM32F4)
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#if defined(STM32F1) || defined(STM32F3) || defined(STM32F4) || defined(STM32G4)
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#define MAX_SPI_PIN_SEL 2
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#define MAX_SPI_PIN_SEL 2
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#elif defined(STM32F7)
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#elif defined(STM32F7)
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#define MAX_SPI_PIN_SEL 4
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#define MAX_SPI_PIN_SEL 4
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@ -32,7 +32,7 @@
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typedef struct spiPinDef_s {
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typedef struct spiPinDef_s {
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ioTag_t pin;
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ioTag_t pin;
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#if defined(STM32F7) || defined(STM32H7)
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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uint8_t af;
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uint8_t af;
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#endif
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#endif
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} spiPinDef_t;
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} spiPinDef_t;
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@ -59,7 +59,7 @@ typedef struct SPIDevice_s {
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ioTag_t sck;
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ioTag_t sck;
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ioTag_t miso;
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ioTag_t miso;
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ioTag_t mosi;
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ioTag_t mosi;
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#if defined(STM32F7) || defined(STM32H7)
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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uint8_t sckAF;
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uint8_t sckAF;
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uint8_t misoAF;
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uint8_t misoAF;
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uint8_t mosiAF;
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uint8_t mosiAF;
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@ -392,6 +392,61 @@ const spiHardware_t spiHardware[] = {
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//.dmaIrqHandler = DMA2_ST1_HANDLER,
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//.dmaIrqHandler = DMA2_ST1_HANDLER,
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},
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},
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#endif
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#endif
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#ifdef STM32G4
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{
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.device = SPIDEV_1,
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.reg = SPI1,
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.sckPins = {
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{ DEFIO_TAG_E(PA5), GPIO_AF5_SPI1 },
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{ DEFIO_TAG_E(PB3), GPIO_AF5_SPI1 },
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},
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.misoPins = {
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{ DEFIO_TAG_E(PA6), GPIO_AF5_SPI1 },
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{ DEFIO_TAG_E(PB4), GPIO_AF5_SPI1 },
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},
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.mosiPins = {
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{ DEFIO_TAG_E(PA7), GPIO_AF5_SPI1 },
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{ DEFIO_TAG_E(PB5), GPIO_AF5_SPI1 },
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},
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.rcc = RCC_APB2(SPI1),
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//.dmaIrqHandler = DMA2_ST3_HANDLER,
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},
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{
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.device = SPIDEV_2,
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.reg = SPI2,
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.sckPins = {
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{ DEFIO_TAG_E(PB13), GPIO_AF5_SPI2 },
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},
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.misoPins = {
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{ DEFIO_TAG_E(PA10), GPIO_AF5_SPI2 },
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{ DEFIO_TAG_E(PB14), GPIO_AF5_SPI2 },
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},
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.mosiPins = {
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{ DEFIO_TAG_E(PA11), GPIO_AF5_SPI2 },
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{ DEFIO_TAG_E(PB15), GPIO_AF5_SPI2 },
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},
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.rcc = RCC_APB11(SPI2),
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//.dmaIrqHandler = DMA1_ST4_HANDLER,
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},
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{
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.device = SPIDEV_3,
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.reg = SPI3,
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.sckPins = {
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{ DEFIO_TAG_E(PB3), GPIO_AF6_SPI3 },
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{ DEFIO_TAG_E(PC10), GPIO_AF6_SPI3 },
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},
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.misoPins = {
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{ DEFIO_TAG_E(PB4), GPIO_AF6_SPI3 },
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{ DEFIO_TAG_E(PC11), GPIO_AF6_SPI3 },
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},
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.mosiPins = {
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{ DEFIO_TAG_E(PB5), GPIO_AF6_SPI3 },
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{ DEFIO_TAG_E(PC12), GPIO_AF6_SPI3 },
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},
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.rcc = RCC_APB11(SPI3),
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//.dmaIrqHandler = DMA1_ST7_HANDLER,
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},
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#endif
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};
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};
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void spiPinConfigure(const spiPinConfig_t *pConfig)
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void spiPinConfigure(const spiPinConfig_t *pConfig)
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@ -409,19 +464,19 @@ void spiPinConfigure(const spiPinConfig_t *pConfig)
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for (int pindex = 0 ; pindex < MAX_SPI_PIN_SEL ; pindex++) {
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for (int pindex = 0 ; pindex < MAX_SPI_PIN_SEL ; pindex++) {
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if (pConfig[device].ioTagSck == hw->sckPins[pindex].pin) {
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if (pConfig[device].ioTagSck == hw->sckPins[pindex].pin) {
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pDev->sck = hw->sckPins[pindex].pin;
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pDev->sck = hw->sckPins[pindex].pin;
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#if defined(STM32F7) || defined(STM32H7)
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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pDev->sckAF = hw->sckPins[pindex].af;
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pDev->sckAF = hw->sckPins[pindex].af;
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#endif
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#endif
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}
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}
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if (pConfig[device].ioTagMiso == hw->misoPins[pindex].pin) {
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if (pConfig[device].ioTagMiso == hw->misoPins[pindex].pin) {
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pDev->miso = hw->misoPins[pindex].pin;
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pDev->miso = hw->misoPins[pindex].pin;
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#if defined(STM32F7) || defined(STM32H7)
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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pDev->misoAF = hw->misoPins[pindex].af;
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pDev->misoAF = hw->misoPins[pindex].af;
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#endif
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#endif
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}
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}
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if (pConfig[device].ioTagMosi == hw->mosiPins[pindex].pin) {
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if (pConfig[device].ioTagMosi == hw->mosiPins[pindex].pin) {
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pDev->mosi = hw->mosiPins[pindex].pin;
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pDev->mosi = hw->mosiPins[pindex].pin;
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#if defined(STM32F7) || defined(STM32H7)
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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pDev->mosiAF = hw->mosiPins[pindex].af;
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pDev->mosiAF = hw->mosiPins[pindex].af;
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#endif
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#endif
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}
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}
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@ -429,7 +484,7 @@ void spiPinConfigure(const spiPinConfig_t *pConfig)
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if (pDev->sck && pDev->miso && pDev->mosi) {
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if (pDev->sck && pDev->miso && pDev->mosi) {
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pDev->dev = hw->reg;
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pDev->dev = hw->reg;
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#if !(defined(STM32F7) || defined(STM32H7))
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#if !(defined(STM32F7) || defined(STM32H7) || defined(STM32G4))
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pDev->af = hw->af;
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pDev->af = hw->af;
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#endif
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#endif
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pDev->rcc = hw->rcc;
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pDev->rcc = hw->rcc;
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