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Allow mixed speed and mode on a SPI bus by CR1 caching

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This commit is contained in:
jflyper 2018-01-06 04:50:19 +09:00
parent 4778ad6c0f
commit 343e9b3a67
22 changed files with 390 additions and 58 deletions
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5
src/test/unit/baro_bmp280_unittest.cc
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@ -147,7 +147,10 @@ void delay(uint32_t) {}
bool busReadRegisterBuffer(const busDevice_t*, uint8_t, uint8_t*, uint8_t) {return true;}
bool busWriteRegister(const busDevice_t*, uint8_t, uint8_t) {return true;}
void spiSetDivisor() {
void spiBusSetDivisor() {
}
void spiBusTransactionInit() {
}
void spiPreinitByIO() {

2
src/test/unit/baro_ms5611_unittest.cc
View file

@ -149,7 +149,7 @@ void delayMicroseconds(uint32_t) {}
bool busReadRegisterBuffer(const busDevice_t*, uint8_t, uint8_t*, uint8_t) {return true;}
bool busWriteRegister(const busDevice_t*, uint8_t, uint8_t) {return true;}
void spiSetDivisor() {
void spiBusSetDivisor() {
}
void spiPreinitByIO() {