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update the files according to the comment of coderabbitai

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This commit is contained in:
jianpingwu1 2025-07-07 16:47:38 +08:00
parent a45945c994
commit 35360f4a3e
10 changed files with 14 additions and 24 deletions
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2
src/platform/GD32/bus_i2c_gd32.c
View file

@ -345,7 +345,7 @@ void i2c_ev_handler(I2CDevice device)
// Read SR1,2 to clear ADDR
__DMB(); // memory fence to control hardware
if (state->bytes == 1 && state->reading && ev_state->subaddress_sent) { // we are receiving 1 byte
i2c_ack_config(I2C0, I2C_ACK_DISABLE); // turn off ACK
i2c_ack_config(I2Cx, I2C_ACK_DISABLE); // turn off ACK
__DMB();
I2C_STAT1(I2Cx); // clear ADDR after ACK is turned off
i2c_stop_on_bus(I2Cx); // program the stop

2
src/platform/GD32/dma_gd32.c
View file

@ -272,7 +272,7 @@ uint16_t gd32_dma_transnum_get(uint32_t dma_chan_base)
return number;
}
FlagStatus gd32_dma_flags_get(uint32_t dma_chan_base, uint32_t flag)
FlagStatus gd32_dma_flag_get(uint32_t dma_chan_base, uint32_t flag)
{
uint32_t dma_periph ;
int channel;

6
src/platform/GD32/include/platform/dma.h
View file

@ -96,7 +96,7 @@ extern void gd32_dma_channel_state_config(uint32_t dma_chan_base, ControlStatus
extern void gd32_dma_int_config(uint32_t dma_chan_base, uint32_t source, ControlStatus new_state);
extern void gd32_dma_transnum_config(uint32_t dma_chan_base, uint32_t number);
extern uint16_t gd32_dma_transnum_get(uint32_t dma_chan_base);
extern FlagStatus gd32_dma_flags_get(uint32_t dma_chan_base, uint32_t flag);
extern FlagStatus gd32_dma_flag_get(uint32_t dma_chan_base, uint32_t flag);
extern void gd32_dma_chbase_parse(uint32_t dma_chan_base, uint32_t *dma_periph, int *dma_channel);
extern void gd32_dma_memory_addr_config(uint32_t dma_chan_base, uint32_t address, uint8_t memory_flag);
@ -106,8 +106,8 @@ extern void gd32_dma_memory_addr_config(uint32_t dma_chan_base, uint32_t address
#define xDMA_ITConfig(dmaResource, flags, newState) gd32_dma_int_config((uint32_t)(dmaResource), flags, newState)
#define xDMA_GetCurrDataCounter(dmaResource) gd32_dma_transnum_get((uint32_t)(dmaResource))
#define xDMA_SetCurrDataCounter(dmaResource, count) gd32_dma_transnum_config((uint32_t)(dmaResource), count)
#define xDMA_GetFlagStatus(dmaResource, flags) gd32_dma_flags_get((uint32_t)(dmaResource), flags)
#define xDMA_ClearFlag(dmaResource, flags) gd32_dma_flags_clear((uint32_t)(dmaResource), flags)
#define xDMA_GetFlagStatus(dmaResource, flags) gd32_dma_flag_get((uint32_t)(dmaResource), flags)
#define xDMA_ClearFlag(dmaResource, flags) gd32_dma_flag_clear((uint32_t)(dmaResource), flags)
#define xDMA_MemoryTargetConfig(dmaResource, address, target) gd32_dma_memory_addr_config((uint32_t)(dmaResource), address, target)
extern uint32_t dma_enable_status_get(uint32_t dma_chan_base);

4
src/platform/GD32/rcu_gd32.c
View file

@ -152,10 +152,10 @@ void RCC_ResetCmd(rccPeriphTag_t periphTag, FunctionalState NewState)
case RCC_AHB3:
rcu_ahb3_periph_rst_config(mask, NewState);
break;
case RCC_APB2:
case RCC_APB1:
rcu_apb1_periph_rst_config(mask, NewState);
break;
case RCC_APB1:
case RCC_APB2:
rcu_apb2_periph_rst_config(mask, NewState);
break;
}

10
src/platform/GD32/startup/system_gd32f4xx.c
View file

@ -708,7 +708,6 @@ static void system_clock_168m_8m_hxtal(void)
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
}
#if 1
/* Enable the high-drive to extend the clock frequency to 168 Mhz */
PMU_CTL |= PMU_CTL_HDEN;
while(0U == (PMU_CS & PMU_CS_HDRF)){
@ -719,10 +718,6 @@ static void system_clock_168m_8m_hxtal(void)
while(0U == (PMU_CS & PMU_CS_HDSRF)){
}
#else
FMC_WS = 0x00000705;
#endif
reg_temp = RCU_CFG0;
/* select PLL as system clock */
reg_temp &= ~RCU_CFG0_SCS;
@ -785,7 +780,6 @@ static void system_clock_168m_25m_hxtal(void)
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
}
#if 1
/* Enable the high-drive to extend the clock frequency to 168 Mhz */
PMU_CTL |= PMU_CTL_HDEN;
while(0U == (PMU_CS & PMU_CS_HDRF)){
@ -796,10 +790,6 @@ static void system_clock_168m_25m_hxtal(void)
while(0U == (PMU_CS & PMU_CS_HDSRF)){
}
#else
FMC_WS = 0x00000705;
#endif
reg_temp = RCU_CFG0;
/* select PLL as system clock */
reg_temp &= ~RCU_CFG0_SCS;

1
src/platform/GD32/target/GD32F425/target.h
View file

@ -92,6 +92,7 @@
#ifdef USE_SDCARD
#ifndef USE_SDCARD_SDIO
#define USE_SDCARD_SPI
#else
#define USE_SDCARD_SDIO
#endif
#endif

1
src/platform/GD32/target/GD32F460RG/target.h
View file

@ -91,6 +91,7 @@
#ifdef USE_SDCARD
#ifndef USE_SDCARD_SDIO
#define USE_SDCARD_SPI
#else
#define USE_SDCARD_SDIO
#endif
#endif

2
src/platform/GD32/usb_f4/usb_conf.h
View file

@ -132,7 +132,7 @@ OF SUCH DAMAGE.
/* __packed keyword used to decrease the data type alignment to 1-byte */
#if defined (__GNUC__) /* GNU Compiler */
#ifndef __packed
#define __packed __unaligned
#define __packed __attribute__((packed))
#endif
#elif defined (__TASKING__) /* TASKING Compiler */
#define __packed __unaligned

2
src/platform/GD32/usb_f4/usbd_desc.c
View file

@ -1,5 +1,5 @@
/*!
\file cdc_acm_core.c
\file usbd_desc.c
\brief CDC ACM driver
\version 2024-12-20, V3.3.1, firmware for GD32F4xx

8
src/platform/GD32/usb_msc_f4xx.c
View file

@ -24,7 +24,7 @@
#include <string.h>
#include "platform.h"
#define USE_USB_MSC
#if defined(USE_USB_MSC)
#include "build/build_config.h"
@ -109,12 +109,10 @@ uint8_t mscStart(void)
usbd_mem_fops = &usbd_internal_storage_fops;
usb_gpio_config();
usb_rcu_config();
//(void)(usbd_mem_fops);
usbd_init(&USB_OTG_dev, USB_CORE_ENUM_FS, &bf_msc_desc, &bf_msc_class);
usb_intr_config();
//(void)(usbd_mem_fops);
usbd_init(&USB_OTG_dev, USB_CORE_ENUM_FS, &bf_msc_desc, &bf_msc_class);
usb_intr_config();
// NVIC configuration for SYSTick
NVIC_DisableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn, NVIC_BUILD_PRIORITY(0, 0));