From 703deeb79fb40c107e6b3b811514e4952acc2e42 Mon Sep 17 00:00:00 2001
From: fishpepper <fishpepper@gmail.com>
Date: Tue, 22 Nov 2016 20:57:02 +0100
Subject: [PATCH] added support for ADC3 in F3 targets

---
 src/main/drivers/adc_impl.h      |  3 ++-
 src/main/drivers/adc_stm32f30x.c | 17 ++++++++++++++---
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/main/drivers/adc_impl.h b/src/main/drivers/adc_impl.h
index 36ec35c1f2..3c29f70da5 100644
--- a/src/main/drivers/adc_impl.h
+++ b/src/main/drivers/adc_impl.h
@@ -33,7 +33,8 @@ typedef enum ADCDevice {
     ADCDEV_1   = 0,
 #if defined(STM32F3)
     ADCDEV_2,
-    ADCDEV_MAX = ADCDEV_2,
+    ADCDEV_3,
+    ADCDEV_MAX = ADCDEV_3,
 #elif defined(STM32F4) || defined(STM32F7)
     ADCDEV_2,
     ADCDEV_3,
diff --git a/src/main/drivers/adc_stm32f30x.c b/src/main/drivers/adc_stm32f30x.c
index de158a69e2..13623a4e17 100644
--- a/src/main/drivers/adc_stm32f30x.c
+++ b/src/main/drivers/adc_stm32f30x.c
@@ -41,10 +41,11 @@
 const adcDevice_t adcHardware[] = {
     { .ADCx = ADC1, .rccADC = RCC_AHB(ADC12), .DMAy_Channelx = DMA1_Channel1 },
 #ifdef ADC24_DMA_REMAP
-    { .ADCx = ADC2, .rccADC = RCC_AHB(ADC12), .DMAy_Channelx = DMA2_Channel3 }
+    { .ADCx = ADC2, .rccADC = RCC_AHB(ADC12), .DMAy_Channelx = DMA2_Channel3 },
 #else
-    { .ADCx = ADC2, .rccADC = RCC_AHB(ADC12), .DMAy_Channelx = DMA2_Channel1 }
+    { .ADCx = ADC2, .rccADC = RCC_AHB(ADC12), .DMAy_Channelx = DMA2_Channel1 },
 #endif
+    { .ADCx = ADC3, .rccADC = RCC_AHB(ADC34), .DMAy_Channelx = DMA2_Channel5 }
 };
 
 const adcTagMap_t adcTagMap[] = {
@@ -97,6 +98,9 @@ ADCDevice adcDeviceByInstance(ADC_TypeDef *instance)
     if (instance == ADC2)
         return ADCDEV_2;
 
+    if (instance == ADC3)
+        return ADCDEV_3;
+
     return ADCINVALID;
 }
 
@@ -152,7 +156,14 @@ void adcInit(adcConfig_t *config)
         return;
     }
     
-    RCC_ADCCLKConfig(RCC_ADC12PLLCLK_Div256);  // 72 MHz divided by 256 = 281.25 kHz
+    if ((device == ADCDEV_1) || (device == ADCDEV_2)) {
+        // enable clock for ADC1+2
+        RCC_ADCCLKConfig(RCC_ADC12PLLCLK_Div256);  // 72 MHz divided by 256 = 281.25 kHz
+    } else {
+        // enable clock for ADC3+4
+        RCC_ADCCLKConfig(RCC_ADC34PLLCLK_Div256);  // 72 MHz divided by 256 = 281.25 kHz
+    }
+
     RCC_ClockCmd(adc.rccADC, ENABLE);
 
     dmaInit(dmaGetIdentifier(adc.DMAy_Channelx), OWNER_ADC, 0);