Mirror/betaflight
1
0
Fork 0
mirror of https://github.com/betaflight/betaflight.git synced 2025-07-19 22:35:23 +03:00
Code Issues Wiki Activity

Merge pull request #1636 from fishpepper/adding_support_for_F3_adc3

Browse source 
added support for ADC3 in F3 targets
This commit is contained in:
J Blackman 2016-11-23 08:49:46 +11:00 • committed by GitHub
commit 35d291325b
2 changed files with 16 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/main/drivers/adc_impl.h
View file

@ -33,7 +33,8 @@ typedef enum ADCDevice {
ADCDEV_1 = 0, ADCDEV_1 = 0,
#if defined(STM32F3) #if defined(STM32F3)
ADCDEV_2, ADCDEV_2,
ADCDEV_MAX = ADCDEV_2, ADCDEV_3,
ADCDEV_MAX = ADCDEV_3,
#elif defined(STM32F4) || defined(STM32F7) #elif defined(STM32F4) || defined(STM32F7)
ADCDEV_2, ADCDEV_2,
ADCDEV_3, ADCDEV_3,

15
src/main/drivers/adc_stm32f30x.c
View file

@ -41,10 +41,11 @@
const adcDevice_t adcHardware[] = { const adcDevice_t adcHardware[] = {
{ .ADCx = ADC1, .rccADC = RCC_AHB(ADC12), .DMAy_Channelx = DMA1_Channel1 }, { .ADCx = ADC1, .rccADC = RCC_AHB(ADC12), .DMAy_Channelx = DMA1_Channel1 },
#ifdef ADC24_DMA_REMAP #ifdef ADC24_DMA_REMAP
{ .ADCx = ADC2, .rccADC = RCC_AHB(ADC12), .DMAy_Channelx = DMA2_Channel3 } { .ADCx = ADC2, .rccADC = RCC_AHB(ADC12), .DMAy_Channelx = DMA2_Channel3 },
#else #else
{ .ADCx = ADC2, .rccADC = RCC_AHB(ADC12), .DMAy_Channelx = DMA2_Channel1 } { .ADCx = ADC2, .rccADC = RCC_AHB(ADC12), .DMAy_Channelx = DMA2_Channel1 },
#endif #endif
{ .ADCx = ADC3, .rccADC = RCC_AHB(ADC34), .DMAy_Channelx = DMA2_Channel5 }
}; };
const adcTagMap_t adcTagMap[] = { const adcTagMap_t adcTagMap[] = {
@ -97,6 +98,9 @@ ADCDevice adcDeviceByInstance(ADC_TypeDef *instance)
if (instance == ADC2) if (instance == ADC2)
return ADCDEV_2; return ADCDEV_2;
if (instance == ADC3)
return ADCDEV_3;
return ADCINVALID; return ADCINVALID;
} }
@ -152,7 +156,14 @@ void adcInit(adcConfig_t *config)
return; return;
} }
if ((device == ADCDEV_1) || (device == ADCDEV_2)) {
// enable clock for ADC1+2
RCC_ADCCLKConfig(RCC_ADC12PLLCLK_Div256); // 72 MHz divided by 256 = 281.25 kHz RCC_ADCCLKConfig(RCC_ADC12PLLCLK_Div256); // 72 MHz divided by 256 = 281.25 kHz
} else {
// enable clock for ADC3+4
RCC_ADCCLKConfig(RCC_ADC34PLLCLK_Div256); // 72 MHz divided by 256 = 281.25 kHz
}
RCC_ClockCmd(adc.rccADC, ENABLE); RCC_ClockCmd(adc.rccADC, ENABLE);
dmaInit(dmaGetIdentifier(adc.DMAy_Channelx), OWNER_ADC, 0); dmaInit(dmaGetIdentifier(adc.DMAy_Channelx), OWNER_ADC, 0);