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Whitespace tidy

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This commit is contained in:
Martin Budden 2018-01-10 16:56:54 +00:00
parent 940d85e20b
commit 3747d6742b
50 changed files with 584 additions and 583 deletions
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2
src/main/drivers/rx/rx_a7105.h
View file

@ -85,7 +85,7 @@ typedef enum {
A7105_32_FILTER_TEST = 0x32, A7105_32_FILTER_TEST = 0x32,
} A7105Reg_t; } A7105Reg_t;
/* Register: A7105_00_MODE */ /* Register: A7105_00_MODE */
#define A7105_MODE_FECF 0x40 // [0]: FEC pass. [1]: FEC error. (FECF is read only, it is updated internally while receiving every packet.) #define A7105_MODE_FECF 0x40 // [0]: FEC pass. [1]: FEC error. (FECF is read only, it is updated internally while receiving every packet.)
#define A7105_MODE_CRCF 0x20 // [0]: CRC pass. [1]: CRC error. (CRCF is read only, it is updated internally while receiving every packet.) #define A7105_MODE_CRCF 0x20 // [0]: CRC pass. [1]: CRC error. (CRCF is read only, it is updated internally while receiving every packet.)
#define A7105_MODE_CER 0x10 // [0]: RF chip is disabled. [1]: RF chip is enabled. #define A7105_MODE_CER 0x10 // [0]: RF chip is disabled. [1]: RF chip is enabled.

248
src/main/drivers/sdio_stdlib.c
View file

@ -367,47 +367,47 @@ uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes);
* @{ * @{
*/ */
#define SDIO_DATA IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_100MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL) #define SDIO_DATA IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_100MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL)
#define SDIO_CMD IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_100MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL) #define SDIO_CMD IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_100MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL)
#define SDIO_CLK IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_100MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL) #define SDIO_CLK IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_100MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL)
#define SDIO_DET IOCFG_IPU #define SDIO_DET IOCFG_IPU
static void SD_LowLevel_Init(void) { static void SD_LowLevel_Init(void) {
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD, ENABLE);
//Configure Pins //Configure Pins
const IO_t d0 = IOGetByTag(IO_TAG(PC8)); const IO_t d0 = IOGetByTag(IO_TAG(PC8));
const IO_t d1 = IOGetByTag(IO_TAG(PC9)); const IO_t d1 = IOGetByTag(IO_TAG(PC9));
const IO_t d2 = IOGetByTag(IO_TAG(PC10)); const IO_t d2 = IOGetByTag(IO_TAG(PC10));
const IO_t d3 = IOGetByTag(IO_TAG(PC11)); const IO_t d3 = IOGetByTag(IO_TAG(PC11));
const IO_t clk = IOGetByTag(IO_TAG(PC12)); const IO_t clk = IOGetByTag(IO_TAG(PC12));
const IO_t cmd = IOGetByTag(IO_TAG(PD2)); const IO_t cmd = IOGetByTag(IO_TAG(PD2));
IOInit(d0, OWNER_SDCARD, 0); IOInit(d0, OWNER_SDCARD, 0);
IOInit(d1, OWNER_SDCARD, 0); IOInit(d1, OWNER_SDCARD, 0);
IOInit(d2, OWNER_SDCARD, 0); IOInit(d2, OWNER_SDCARD, 0);
IOInit(d3, OWNER_SDCARD, 0); IOInit(d3, OWNER_SDCARD, 0);
IOInit(clk, OWNER_SDCARD, 0); IOInit(clk, OWNER_SDCARD, 0);
IOInit(cmd, OWNER_SDCARD, 0); IOInit(cmd, OWNER_SDCARD, 0);
IOConfigGPIOAF(d0, SDIO_DATA, GPIO_AF_SDIO); IOConfigGPIOAF(d0, SDIO_DATA, GPIO_AF_SDIO);
IOConfigGPIOAF(d1, SDIO_DATA, GPIO_AF_SDIO); IOConfigGPIOAF(d1, SDIO_DATA, GPIO_AF_SDIO);
IOConfigGPIOAF(d2, SDIO_DATA, GPIO_AF_SDIO); IOConfigGPIOAF(d2, SDIO_DATA, GPIO_AF_SDIO);
IOConfigGPIOAF(d3, SDIO_DATA, GPIO_AF_SDIO); IOConfigGPIOAF(d3, SDIO_DATA, GPIO_AF_SDIO);
IOConfigGPIOAF(clk, SDIO_CLK, GPIO_AF_SDIO); IOConfigGPIOAF(clk, SDIO_CLK, GPIO_AF_SDIO);
IOConfigGPIOAF(cmd, SDIO_CMD, GPIO_AF_SDIO); IOConfigGPIOAF(cmd, SDIO_CMD, GPIO_AF_SDIO);
#ifdef SDCARD_DETECT_PIN #ifdef SDCARD_DETECT_PIN
const IO_t sd_det = IOGetByTag(IO_TAG(SDCARD_DETECT_PIN)); const IO_t sd_det = IOGetByTag(IO_TAG(SDCARD_DETECT_PIN));
IOInit(sd_det, OWNER_SDCARD, 0); IOInit(sd_det, OWNER_SDCARD, 0);
IOConfigGPIO(sd_det, SDIO_DET); IOConfigGPIO(sd_det, SDIO_DET);
#endif #endif
/* Enable the SDIO APB2 Clock */ /* Enable the SDIO APB2 Clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE);
/* Enable the DMA2 Clock */ /* Enable the DMA2 Clock */
RCC_AHB1PeriphClockCmd(SD_SDIO_DMA_CLK, ENABLE); RCC_AHB1PeriphClockCmd(SD_SDIO_DMA_CLK, ENABLE);
NVIC_InitTypeDef NVIC_InitStructure; NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
@ -419,128 +419,128 @@ static void SD_LowLevel_Init(void) {
static void SD_LowLevel_DeInit(void) static void SD_LowLevel_DeInit(void)
{ {
NVIC_InitTypeDef NVIC_InitStructure; NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(1); NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(1);
NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(2); NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(2);
NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
NVIC_Init(&NVIC_InitStructure); NVIC_Init(&NVIC_InitStructure);
/*!< Disable SDIO Clock */ /*!< Disable SDIO Clock */
SDIO_ClockCmd(DISABLE); SDIO_ClockCmd(DISABLE);
/*!< Set Power State to OFF */ /*!< Set Power State to OFF */
SDIO_SetPowerState(SDIO_PowerState_OFF); SDIO_SetPowerState(SDIO_PowerState_OFF);
/*!< DeInitializes the SDIO peripheral */ /*!< DeInitializes the SDIO peripheral */
SDIO_DeInit(); SDIO_DeInit();
/* Disable the SDIO APB2 Clock */ /* Disable the SDIO APB2 Clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, DISABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, DISABLE);
//Configure Pins //Configure Pins
const IO_t d0 = IOGetByTag(IO_TAG(PC8)); const IO_t d0 = IOGetByTag(IO_TAG(PC8));
const IO_t d1 = IOGetByTag(IO_TAG(PC9)); const IO_t d1 = IOGetByTag(IO_TAG(PC9));
const IO_t d2 = IOGetByTag(IO_TAG(PC10)); const IO_t d2 = IOGetByTag(IO_TAG(PC10));
const IO_t d3 = IOGetByTag(IO_TAG(PC11)); const IO_t d3 = IOGetByTag(IO_TAG(PC11));
const IO_t clk = IOGetByTag(IO_TAG(PC12)); const IO_t clk = IOGetByTag(IO_TAG(PC12));
const IO_t cmd = IOGetByTag(IO_TAG(PD2)); const IO_t cmd = IOGetByTag(IO_TAG(PD2));
IOInit(d0, OWNER_FREE, 0); IOInit(d0, OWNER_FREE, 0);
IOInit(d1, OWNER_FREE, 0); IOInit(d1, OWNER_FREE, 0);
IOInit(d2, OWNER_FREE, 0); IOInit(d2, OWNER_FREE, 0);
IOInit(d3, OWNER_FREE, 0); IOInit(d3, OWNER_FREE, 0);
IOInit(clk, OWNER_FREE, 0); IOInit(clk, OWNER_FREE, 0);
IOInit(cmd, OWNER_FREE, 0); IOInit(cmd, OWNER_FREE, 0);
IOConfigGPIOAF(d0, IOCFG_IN_FLOATING, GPIO_AF_SDIO); IOConfigGPIOAF(d0, IOCFG_IN_FLOATING, GPIO_AF_SDIO);
IOConfigGPIOAF(d1, IOCFG_IN_FLOATING, GPIO_AF_SDIO); IOConfigGPIOAF(d1, IOCFG_IN_FLOATING, GPIO_AF_SDIO);
IOConfigGPIOAF(d2, IOCFG_IN_FLOATING, GPIO_AF_SDIO); IOConfigGPIOAF(d2, IOCFG_IN_FLOATING, GPIO_AF_SDIO);
IOConfigGPIOAF(d3, IOCFG_IN_FLOATING, GPIO_AF_SDIO); IOConfigGPIOAF(d3, IOCFG_IN_FLOATING, GPIO_AF_SDIO);
IOConfigGPIOAF(clk, IOCFG_IN_FLOATING, GPIO_AF_SDIO); IOConfigGPIOAF(clk, IOCFG_IN_FLOATING, GPIO_AF_SDIO);
IOConfigGPIOAF(cmd, IOCFG_IN_FLOATING, GPIO_AF_SDIO); IOConfigGPIOAF(cmd, IOCFG_IN_FLOATING, GPIO_AF_SDIO);
#ifdef SDCARD_DETECT_PIN #ifdef SDCARD_DETECT_PIN
const IO_t sd_det = IOGetByTag(IO_TAG(SDCARD_DETECT_PIN)); const IO_t sd_det = IOGetByTag(IO_TAG(SDCARD_DETECT_PIN));
IOInit(sd_det, OWNER_FREE, 0); IOInit(sd_det, OWNER_FREE, 0);
IOConfigGPIO(cmd, SDIO_DET); IOConfigGPIO(cmd, SDIO_DET);
#endif #endif
} }
void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize) void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize)
{ {
DMA_InitTypeDef SDDMA_InitStructure; DMA_InitTypeDef SDDMA_InitStructure;
DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF); DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF);
/* DMA2 Stream3 or Stream6 disable */ /* DMA2 Stream3 or Stream6 disable */
DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE); DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE);
/* DMA2 Stream3 or Stream6 Config */ /* DMA2 Stream3 or Stream6 Config */
DMA_DeInit(SD_SDIO_DMA_STREAM); DMA_DeInit(SD_SDIO_DMA_STREAM);
SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL; SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL;
SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS; SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferSRC; SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferSRC;
SDDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; SDDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
SDDMA_InitStructure.DMA_BufferSize = BufferSize; SDDMA_InitStructure.DMA_BufferSize = BufferSize;
SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4; SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4;
SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4;
dmaInit(dmaGetIdentifier(DMA2_Stream3), OWNER_SDCARD, 0); dmaInit(dmaGetIdentifier(DMA2_Stream3), OWNER_SDCARD, 0);
DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure); DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure);
dmaSetHandler(dmaGetIdentifier(SD_SDIO_DMA_STREAM), SD_ProcessDMAIRQ, 2, 0); dmaSetHandler(dmaGetIdentifier(SD_SDIO_DMA_STREAM), SD_ProcessDMAIRQ, 2, 0);
DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE); DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE);
DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral); DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral);
/* DMA2 Stream3 or Stream6 enable */ /* DMA2 Stream3 or Stream6 enable */
DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE); DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE);
} }
void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize) void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize)
{ {
DMA_InitTypeDef SDDMA_InitStructure; DMA_InitTypeDef SDDMA_InitStructure;
DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF); DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF);
/* DMA2 Stream3 or Stream6 disable */ /* DMA2 Stream3 or Stream6 disable */
DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE); DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE);
/* DMA2 Stream3 or Stream6 Config */ /* DMA2 Stream3 or Stream6 Config */
DMA_DeInit(SD_SDIO_DMA_STREAM); DMA_DeInit(SD_SDIO_DMA_STREAM);
SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL; SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL;
SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS; SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferDST; SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferDST;
SDDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; SDDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
SDDMA_InitStructure.DMA_BufferSize = BufferSize; SDDMA_InitStructure.DMA_BufferSize = BufferSize;
SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4; SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4;
SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4;
dmaInit(dmaGetIdentifier(DMA2_Stream3), OWNER_SDCARD, 0); dmaInit(dmaGetIdentifier(DMA2_Stream3), OWNER_SDCARD, 0);
DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure); DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure);
dmaSetHandler(dmaGetIdentifier(SD_SDIO_DMA_STREAM), SD_ProcessDMAIRQ, 2, 0); dmaSetHandler(dmaGetIdentifier(SD_SDIO_DMA_STREAM), SD_ProcessDMAIRQ, 2, 0);
DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE); DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE);
DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral); DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral);
/* DMA2 Stream3 or Stream6 enable */ /* DMA2 Stream3 or Stream6 enable */
DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE); DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE);
} }
/** /**
@ -3108,7 +3108,7 @@ SD_Error SD_HighSpeed (void)
//IRQ Handler //IRQ Handler
void SDIO_IRQHandler(void) { void SDIO_IRQHandler(void) {
SD_ProcessIRQSrc(); SD_ProcessIRQSrc();
} }
/** /**

2
src/main/drivers/sdio_stdlib.h
View file

@ -338,7 +338,7 @@ typedef struct
#define SD_SDIO_DMA DMA2 #define SD_SDIO_DMA DMA2
#define SD_SDIO_DMA_CLK RCC_AHB1Periph_DMA2 #define SD_SDIO_DMA_CLK RCC_AHB1Periph_DMA2
#define SD_SDIO_DMA_STREAM3 3 #define SD_SDIO_DMA_STREAM3 3
#ifdef SD_SDIO_DMA_STREAM3 #ifdef SD_SDIO_DMA_STREAM3
#define SD_SDIO_DMA_STREAM DMA2_Stream3 #define SD_SDIO_DMA_STREAM DMA2_Stream3

2
src/main/flight/pid.c
View file

@ -543,5 +543,5 @@ void pidController(const pidProfile_t *pidProfile, const rollAndPitchTrims_t *an
bool crashRecoveryModeActive(void) bool crashRecoveryModeActive(void)
{ {
return inCrashRecoveryMode; return inCrashRecoveryMode;
} }

2
src/main/io/ledstrip.c
View file

@ -458,7 +458,7 @@ static void applyLedFixedLayers(void)
hsvColor_t previousColor = ledStripConfig()->colors[(ledGetColor(ledConfig) - 1 + LED_CONFIGURABLE_COLOR_COUNT) % LED_CONFIGURABLE_COLOR_COUNT]; hsvColor_t previousColor = ledStripConfig()->colors[(ledGetColor(ledConfig) - 1 + LED_CONFIGURABLE_COLOR_COUNT) % LED_CONFIGURABLE_COLOR_COUNT];
if (ledGetOverlayBit(ledConfig, LED_OVERLAY_THROTTLE)) { //smooth fade with selected Aux channel of all HSV values from previousColor through color to nextColor if (ledGetOverlayBit(ledConfig, LED_OVERLAY_THROTTLE)) { //smooth fade with selected Aux channel of all HSV values from previousColor through color to nextColor
int centerPWM = (PWM_RANGE_MIN + PWM_RANGE_MAX) / 2; int centerPWM = (PWM_RANGE_MIN + PWM_RANGE_MAX) / 2;
if (auxInput < centerPWM) { if (auxInput < centerPWM) {
color.h = scaleRange(auxInput, PWM_RANGE_MIN, centerPWM, previousColor.h, color.h); color.h = scaleRange(auxInput, PWM_RANGE_MIN, centerPWM, previousColor.h, color.h);
color.s = scaleRange(auxInput, PWM_RANGE_MIN, centerPWM, previousColor.s, color.s); color.s = scaleRange(auxInput, PWM_RANGE_MIN, centerPWM, previousColor.s, color.s);

140
src/main/io/vtx_smartaudio.c
View file

@ -761,16 +761,16 @@ void vtxSAProcess(timeUs_t currentTimeUs)
// dprintf(("process: resending 0x%x\r\n", sa_outstanding)); // dprintf(("process: resending 0x%x\r\n", sa_outstanding));
// XXX Todo: Resend termination and possible offline transition // XXX Todo: Resend termination and possible offline transition
saResendCmd(); saResendCmd();
lastCommandSentMs = nowMs; lastCommandSentMs = nowMs;
} else if (!saQueueEmpty()) { } else if (!saQueueEmpty()) {
// Command pending. Send it. // Command pending. Send it.
// dprintf(("process: sending queue\r\n")); // dprintf(("process: sending queue\r\n"));
saSendQueue(); saSendQueue();
lastCommandSentMs = nowMs; lastCommandSentMs = nowMs;
} else if ((nowMs - lastCommandSentMs < SMARTAUDIO_POLLING_WINDOW) && (nowMs - sa_lastTransmissionMs >= SMARTAUDIO_POLLING_INTERVAL)) { } else if ((nowMs - lastCommandSentMs < SMARTAUDIO_POLLING_WINDOW) && (nowMs - sa_lastTransmissionMs >= SMARTAUDIO_POLLING_INTERVAL)) {
//dprintf(("process: sending status change polling\r\n")); //dprintf(("process: sending status change polling\r\n"));
saGetSettings(); saGetSettings();
saSendQueue(); saSendQueue();
} }
} }
@ -779,123 +779,123 @@ void vtxSAProcess(timeUs_t currentTimeUs)
vtxDevType_e vtxSAGetDeviceType(void) vtxDevType_e vtxSAGetDeviceType(void)
{ {
return VTXDEV_SMARTAUDIO; return VTXDEV_SMARTAUDIO;
} }
bool vtxSAIsReady(void) bool vtxSAIsReady(void)
{ {
return !(saDevice.version == 0); return !(saDevice.version == 0);
} }
void vtxSASetBandAndChannel(uint8_t band, uint8_t channel) void vtxSASetBandAndChannel(uint8_t band, uint8_t channel)
{ {
if (saValidateBandAndChannel(band, channel)) { if (saValidateBandAndChannel(band, channel)) {
saSetBandAndChannel(band - 1, channel - 1); saSetBandAndChannel(band - 1, channel - 1);
} }
} }
void vtxSASetPowerByIndex(uint8_t index) void vtxSASetPowerByIndex(uint8_t index)
{ {
if (index == 0) { if (index == 0) {
// SmartAudio doesn't support power off. // SmartAudio doesn't support power off.
return; return;
} }
saSetPowerByIndex(index - 1); saSetPowerByIndex(index - 1);
} }
void vtxSASetPitMode(uint8_t onoff) void vtxSASetPitMode(uint8_t onoff)
{ {
if (!(vtxSAIsReady() && (saDevice.version == 2))) { if (!(vtxSAIsReady() && (saDevice.version == 2))) {
return; return;
} }
if (onoff) { if (onoff) {
// SmartAudio can not turn pit mode on by software. // SmartAudio can not turn pit mode on by software.
return; return;
} }
uint8_t newmode = SA_MODE_CLR_PITMODE; uint8_t newmode = SA_MODE_CLR_PITMODE;
if (saDevice.mode & SA_MODE_GET_IN_RANGE_PITMODE) { if (saDevice.mode & SA_MODE_GET_IN_RANGE_PITMODE) {
newmode |= SA_MODE_SET_IN_RANGE_PITMODE; newmode |= SA_MODE_SET_IN_RANGE_PITMODE;
} }
if (saDevice.mode & SA_MODE_GET_OUT_RANGE_PITMODE) { if (saDevice.mode & SA_MODE_GET_OUT_RANGE_PITMODE) {
newmode |= SA_MODE_SET_OUT_RANGE_PITMODE; newmode |= SA_MODE_SET_OUT_RANGE_PITMODE;
} }
saSetMode(newmode); saSetMode(newmode);
return; return;
} }
void vtxSASetFreq(uint16_t freq) void vtxSASetFreq(uint16_t freq)
{ {
if (saValidateFreq(freq)) { if (saValidateFreq(freq)) {
saSetMode(0); //need to be in FREE mode to set freq saSetMode(0); //need to be in FREE mode to set freq
saSetFreq(freq); saSetFreq(freq);
} }
} }
bool vtxSAGetBandAndChannel(uint8_t *pBand, uint8_t *pChannel) bool vtxSAGetBandAndChannel(uint8_t *pBand, uint8_t *pChannel)
{ {
if (!vtxSAIsReady()) { if (!vtxSAIsReady()) {
return false; return false;
} }
// if in user-freq mode then report band as zero // if in user-freq mode then report band as zero
*pBand = (saDevice.mode & SA_MODE_GET_FREQ_BY_FREQ) ? 0 : *pBand = (saDevice.mode & SA_MODE_GET_FREQ_BY_FREQ) ? 0 :
(SA_DEVICE_CHVAL_TO_BAND(saDevice.channel) + 1); (SA_DEVICE_CHVAL_TO_BAND(saDevice.channel) + 1);
*pChannel = SA_DEVICE_CHVAL_TO_CHANNEL(saDevice.channel) + 1; *pChannel = SA_DEVICE_CHVAL_TO_CHANNEL(saDevice.channel) + 1;
return true; return true;
} }
bool vtxSAGetPowerIndex(uint8_t *pIndex) bool vtxSAGetPowerIndex(uint8_t *pIndex)
{ {
if (!vtxSAIsReady()) { if (!vtxSAIsReady()) {
return false; return false;
} }
*pIndex = ((saDevice.version == 1) ? saDacToPowerIndex(saDevice.power) : saDevice.power) + 1; *pIndex = ((saDevice.version == 1) ? saDacToPowerIndex(saDevice.power) : saDevice.power) + 1;
return true; return true;
} }
bool vtxSAGetPitMode(uint8_t *pOnOff) bool vtxSAGetPitMode(uint8_t *pOnOff)
{ {
if (!(vtxSAIsReady() && (saDevice.version == 2))) { if (!(vtxSAIsReady() && (saDevice.version == 2))) {
return false; return false;
} }
*pOnOff = (saDevice.mode & SA_MODE_GET_PITMODE) ? 1 : 0; *pOnOff = (saDevice.mode & SA_MODE_GET_PITMODE) ? 1 : 0;
return true; return true;
} }
bool vtxSAGetFreq(uint16_t *pFreq) bool vtxSAGetFreq(uint16_t *pFreq)
{ {
if (!vtxSAIsReady()) { if (!vtxSAIsReady()) {
return false; return false;
} }
// if not in user-freq mode then convert band/chan to frequency // if not in user-freq mode then convert band/chan to frequency
*pFreq = (saDevice.mode & SA_MODE_GET_FREQ_BY_FREQ) ? saDevice.freq : *pFreq = (saDevice.mode & SA_MODE_GET_FREQ_BY_FREQ) ? saDevice.freq :
vtx58_Bandchan2Freq(SA_DEVICE_CHVAL_TO_BAND(saDevice.channel) + 1, vtx58_Bandchan2Freq(SA_DEVICE_CHVAL_TO_BAND(saDevice.channel) + 1,
SA_DEVICE_CHVAL_TO_CHANNEL(saDevice.channel) + 1); SA_DEVICE_CHVAL_TO_CHANNEL(saDevice.channel) + 1);
return true; return true;
} }
static const vtxVTable_t saVTable = { static const vtxVTable_t saVTable = {
.process = vtxSAProcess, .process = vtxSAProcess,
.getDeviceType = vtxSAGetDeviceType, .getDeviceType = vtxSAGetDeviceType,
.isReady = vtxSAIsReady, .isReady = vtxSAIsReady,
.setBandAndChannel = vtxSASetBandAndChannel, .setBandAndChannel = vtxSASetBandAndChannel,
.setPowerByIndex = vtxSASetPowerByIndex, .setPowerByIndex = vtxSASetPowerByIndex,
.setPitMode = vtxSASetPitMode, .setPitMode = vtxSASetPitMode,
.setFrequency = vtxSASetFreq, .setFrequency = vtxSASetFreq,
.getBandAndChannel = vtxSAGetBandAndChannel, .getBandAndChannel = vtxSAGetBandAndChannel,
.getPowerIndex = vtxSAGetPowerIndex, .getPowerIndex = vtxSAGetPowerIndex,
.getPitMode = vtxSAGetPitMode, .getPitMode = vtxSAGetPitMode,
.getFrequency = vtxSAGetFreq, .getFrequency = vtxSAGetFreq,
}; };
#endif // VTX_COMMON #endif // VTX_COMMON

2
src/main/target/CC3D/target.c
View file

@ -38,7 +38,7 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
DEF_TIM(TIM4, CH2, PB7, TIM_USE_MOTOR, 0), // S3_OUT DEF_TIM(TIM4, CH2, PB7, TIM_USE_MOTOR, 0), // S3_OUT
DEF_TIM(TIM1, CH1, PA8, TIM_USE_MOTOR, 0), // S4_OUT DEF_TIM(TIM1, CH1, PA8, TIM_USE_MOTOR, 0), // S4_OUT
DEF_TIM(TIM4, CH1, PB6, TIM_USE_MOTOR, 0), // S1_IN/ DEF_TIM(TIM4, CH1, PB6, TIM_USE_MOTOR, 0), // S1_IN/
// DEF_TIM(TIM3, CH1, PB4, TIM_USE_MOTOR, 1), // S5_OUT <--Moved to allow Parallel PWM with proper ESC // DEF_TIM(TIM3, CH1, PB4, TIM_USE_MOTOR, 1), // S5_OUT <--Moved to allow Parallel PWM with proper ESC
DEF_TIM(TIM2, CH3, PA2, TIM_USE_MOTOR, 0), // S6_OUT DEF_TIM(TIM2, CH3, PA2, TIM_USE_MOTOR, 0), // S6_OUT
}; };

7
src/main/target/KISSFCV2F7/config.c
View file

@ -29,8 +29,9 @@
#ifdef USE_TARGET_CONFIG #ifdef USE_TARGET_CONFIG
void targetConfiguration(void){ void targetConfiguration(void)
rxConfigMutable()->halfDuplex = true; {
serialConfigMutable()->portConfigs[findSerialPortIndexByIdentifier(SERIAL_PORT_UART4)].functionMask = FUNCTION_MSP; rxConfigMutable()->halfDuplex = true;
serialConfigMutable()->portConfigs[findSerialPortIndexByIdentifier(SERIAL_PORT_UART4)].functionMask = FUNCTION_MSP;
} }
#endif #endif

16
src/main/target/KISSFCV2F7/target.c
View file

@ -26,17 +26,17 @@
const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
DEF_TIM(TIM9, CH1, PA2, TIM_USE_PWM | TIM_USE_PPM, 0, 0), DEF_TIM(TIM9, CH1, PA2, TIM_USE_PWM | TIM_USE_PPM, 0, 0),
DEF_TIM(TIM8, CH1, PC6, TIM_USE_MOTOR, 0, 0), DEF_TIM(TIM8, CH1, PC6, TIM_USE_MOTOR, 0, 0),
DEF_TIM(TIM5, CH1, PA0, TIM_USE_MOTOR, 0, 0), DEF_TIM(TIM5, CH1, PA0, TIM_USE_MOTOR, 0, 0),
DEF_TIM(TIM4, CH3, PB8, TIM_USE_MOTOR, 0, 0), DEF_TIM(TIM4, CH3, PB8, TIM_USE_MOTOR, 0, 0),
DEF_TIM(TIM4, CH1, PB6, TIM_USE_MOTOR, 0, 0), DEF_TIM(TIM4, CH1, PB6, TIM_USE_MOTOR, 0, 0),
DEF_TIM(TIM4, CH2, PB7, TIM_USE_MOTOR, 0, 0), DEF_TIM(TIM4, CH2, PB7, TIM_USE_MOTOR, 0, 0),
DEF_TIM(TIM8, CH2, PC7, TIM_USE_MOTOR, 0, 0), DEF_TIM(TIM8, CH2, PC7, TIM_USE_MOTOR, 0, 0),
DEF_TIM(TIM2, CH2, PB3, TIM_USE_LED, 0, 0) DEF_TIM(TIM2, CH2, PB3, TIM_USE_LED, 0, 0)
}; };

20
src/main/target/MATEKF411/target.c
View file

@ -25,17 +25,17 @@
#include "drivers/timer_def.h" #include "drivers/timer_def.h"
const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
DEF_TIM(TIM9, CH2, PA3, TIM_USE_PPM, 0, 0), // PPM IN DEF_TIM(TIM9, CH2, PA3, TIM_USE_PPM, 0, 0), // PPM IN
DEF_TIM(TIM3, CH1, PB4, TIM_USE_MOTOR, 0, 0), // S1_OUT DEF_TIM(TIM3, CH1, PB4, TIM_USE_MOTOR, 0, 0), // S1_OUT
DEF_TIM(TIM3, CH2, PB5, TIM_USE_MOTOR, 0, 0), // S2_OUT DEF_TIM(TIM3, CH2, PB5, TIM_USE_MOTOR, 0, 0), // S2_OUT
DEF_TIM(TIM4, CH1, PB6, TIM_USE_MOTOR, 0, 0), // S3_OUT DEF_TIM(TIM4, CH1, PB6, TIM_USE_MOTOR, 0, 0), // S3_OUT
DEF_TIM(TIM4, CH2, PB7, TIM_USE_MOTOR, 0, 0), // S4_OUT DEF_TIM(TIM4, CH2, PB7, TIM_USE_MOTOR, 0, 0), // S4_OUT
DEF_TIM(TIM2, CH2, PB3, TIM_USE_MOTOR, 0, 0), // S5 DEF_TIM(TIM2, CH2, PB3, TIM_USE_MOTOR, 0, 0), // S5
DEF_TIM(TIM2, CH3, PB10, TIM_USE_MOTOR, 0, 0), // S6 DEF_TIM(TIM2, CH3, PB10, TIM_USE_MOTOR, 0, 0), // S6
DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0), // RSSI pad DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0), // RSSI pad
DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0), // TX2 DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0), // TX2
DEF_TIM(TIM1, CH1, PA8, TIM_USE_LED, 0, 0), // LED DEF_TIM(TIM1, CH1, PA8, TIM_USE_LED, 0, 0), // LED
}; };

8
src/main/target/MATEKF411/target.h
View file

@ -31,8 +31,8 @@
#define USE_SPI_DEVICE_1 #define USE_SPI_DEVICE_1
#define SPI1_SCK_PIN PA5 #define SPI1_SCK_PIN PA5
#define SPI1_MISO_PIN PA6 #define SPI1_MISO_PIN PA6
#define SPI1_MOSI_PIN PA7 #define SPI1_MOSI_PIN PA7
#define MPU6000_CS_PIN PA4 #define MPU6000_CS_PIN PA4
#define MPU6000_SPI_INSTANCE SPI1 #define MPU6000_SPI_INSTANCE SPI1
@ -95,8 +95,8 @@
// *************** OSD ***************************** // *************** OSD *****************************
#define USE_SPI_DEVICE_2 #define USE_SPI_DEVICE_2
#define SPI2_SCK_PIN PB13 #define SPI2_SCK_PIN PB13
#define SPI2_MISO_PIN PB14 #define SPI2_MISO_PIN PB14
#define SPI2_MOSI_PIN PB15 #define SPI2_MOSI_PIN PB15
#define USE_OSD #define USE_OSD
#define USE_MAX7456 #define USE_MAX7456

8
src/main/telemetry/srxl.c
View file

@ -209,10 +209,10 @@ bool srxlFrameFlightPackCurrent(sbuf_t *dst, timeUs_t currentTimeUs)
/* /*
typedef struct typedef struct
{ {
UINT8 identifier; UINT8 identifier;
UINT8 sID; // Secondary ID UINT8 sID; // Secondary ID
UINT8 lineNumber; // Line number to display (0 = title, 1-8 for general, 254 = Refresh backlight, 255 = Erase all text on screen) UINT8 lineNumber; // Line number to display (0 = title, 1-8 for general, 254 = Refresh backlight, 255 = Erase all text on screen)
char text[13]; // 0-terminated text when < 13 chars char text[13]; // 0-terminated text when < 13 chars
} STRU_SPEKTRUM_SRXL_TEXTGEN; } STRU_SPEKTRUM_SRXL_TEXTGEN;
*/ */