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Configurable SDCARD, and clean up of DMA.

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This commit is contained in:
blckmn 2018-01-29 11:50:14 +11:00
parent b73ffbb592
commit 39bb6ffe04
54 changed files with 504 additions and 436 deletions
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102
src/main/drivers/dma_stm32f4xx.c
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@ -28,24 +28,24 @@
/*
* DMA descriptors.
*/
static dmaChannelDescriptor_t dmaDescriptors[DMA_MAX_DESCRIPTORS] = {
DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream0, 0, DMA1_Stream0_IRQn, RCC_AHB1Periph_DMA1),
DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream1, 6, DMA1_Stream1_IRQn, RCC_AHB1Periph_DMA1),
DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream2, 16, DMA1_Stream2_IRQn, RCC_AHB1Periph_DMA1),
DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream3, 22, DMA1_Stream3_IRQn, RCC_AHB1Periph_DMA1),
DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream4, 32, DMA1_Stream4_IRQn, RCC_AHB1Periph_DMA1),
DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream5, 38, DMA1_Stream5_IRQn, RCC_AHB1Periph_DMA1),
DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream6, 48, DMA1_Stream6_IRQn, RCC_AHB1Periph_DMA1),
DEFINE_DMA_CHANNEL(DMA1, DMA1_Stream7, 54, DMA1_Stream7_IRQn, RCC_AHB1Periph_DMA1),
static dmaChannelDescriptor_t dmaDescriptors[DMA_LAST_HANDLER] = {
DEFINE_DMA_CHANNEL(DMA1, 0, 0),
DEFINE_DMA_CHANNEL(DMA1, 1, 6),
DEFINE_DMA_CHANNEL(DMA1, 2, 16),
DEFINE_DMA_CHANNEL(DMA1, 3, 22),
DEFINE_DMA_CHANNEL(DMA1, 4, 32),
DEFINE_DMA_CHANNEL(DMA1, 5, 38),
DEFINE_DMA_CHANNEL(DMA1, 6, 48),
DEFINE_DMA_CHANNEL(DMA1, 7, 54),
DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream0, 0, DMA2_Stream0_IRQn, RCC_AHB1Periph_DMA2),
DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream1, 6, DMA2_Stream1_IRQn, RCC_AHB1Periph_DMA2),
DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream2, 16, DMA2_Stream2_IRQn, RCC_AHB1Periph_DMA2),
DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream3, 22, DMA2_Stream3_IRQn, RCC_AHB1Periph_DMA2),
DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream4, 32, DMA2_Stream4_IRQn, RCC_AHB1Periph_DMA2),
DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream5, 38, DMA2_Stream5_IRQn, RCC_AHB1Periph_DMA2),
DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream6, 48, DMA2_Stream6_IRQn, RCC_AHB1Periph_DMA2),
DEFINE_DMA_CHANNEL(DMA2, DMA2_Stream7, 54, DMA2_Stream7_IRQn, RCC_AHB1Periph_DMA2),
DEFINE_DMA_CHANNEL(DMA2, 0, 0),
DEFINE_DMA_CHANNEL(DMA2, 1, 6),
DEFINE_DMA_CHANNEL(DMA2, 2, 16),
DEFINE_DMA_CHANNEL(DMA2, 3, 22),
DEFINE_DMA_CHANNEL(DMA2, 4, 32),
DEFINE_DMA_CHANNEL(DMA2, 5, 38),
DEFINE_DMA_CHANNEL(DMA2, 6, 48),
DEFINE_DMA_CHANNEL(DMA2, 7, 54),
};
/*
@ -68,26 +68,13 @@ DEFINE_DMA_IRQ_HANDLER(2, 5, DMA2_ST5_HANDLER)
DEFINE_DMA_IRQ_HANDLER(2, 6, DMA2_ST6_HANDLER)
DEFINE_DMA_IRQ_HANDLER(2, 7, DMA2_ST7_HANDLER)
#define DMA_RCC(x) ((x) == DMA1 ? RCC_AHB1Periph_DMA1 : RCC_AHB1Periph_DMA2)
void dmaInit(dmaIdentifier_e identifier, resourceOwner_e owner, uint8_t resourceIndex)
{
RCC_AHB1PeriphClockCmd(dmaDescriptors[identifier].rcc, ENABLE);
dmaDescriptors[identifier].owner = owner;
dmaDescriptors[identifier].resourceIndex = resourceIndex;
}
void dmaSetHandler(dmaIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam)
{
NVIC_InitTypeDef NVIC_InitStructure;
RCC_AHB1PeriphClockCmd(dmaDescriptors[identifier].rcc, ENABLE);
dmaDescriptors[identifier].irqHandlerCallback = callback;
dmaDescriptors[identifier].userParam = userParam;
NVIC_InitStructure.NVIC_IRQChannel = dmaDescriptors[identifier].irqN;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(priority);
NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(priority);
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
const int index = DMA_IDENTIFIER_TO_INDEX(identifier);
RCC_AHB1PeriphClockCmd(DMA_RCC(dmaDescriptors[index].dma), ENABLE);
dmaDescriptors[index].owner = owner;
dmaDescriptors[index].resourceIndex = resourceIndex;
}
#define RETURN_TCIF_FLAG(s, n) if (s == DMA1_Stream ## n || s == DMA2_Stream ## n) return DMA_IT_TCIF ## n
@ -105,32 +92,65 @@ uint32_t dmaFlag_IT_TCIF(const DMA_Stream_TypeDef *stream)
return 0;
}
void dmaSetHandler(dmaIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam)
{
NVIC_InitTypeDef NVIC_InitStructure;
const int index = DMA_IDENTIFIER_TO_INDEX(identifier);
RCC_AHB1PeriphClockCmd(DMA_RCC(dmaDescriptors[index].dma), ENABLE);
dmaDescriptors[index].irqHandlerCallback = callback;
dmaDescriptors[index].userParam = userParam;
dmaDescriptors[index].completeFlag = dmaFlag_IT_TCIF(dmaDescriptors[index].ref);
NVIC_InitStructure.NVIC_IRQChannel = dmaDescriptors[index].irqN;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(priority);
NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(priority);
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
resourceOwner_e dmaGetOwner(dmaIdentifier_e identifier)
{
return dmaDescriptors[identifier].owner;
return dmaDescriptors[DMA_IDENTIFIER_TO_INDEX(identifier)].owner;
}
uint8_t dmaGetResourceIndex(dmaIdentifier_e identifier)
{
return dmaDescriptors[identifier].resourceIndex;
return dmaDescriptors[DMA_IDENTIFIER_TO_INDEX(identifier)].resourceIndex;
}
dmaIdentifier_e dmaGetIdentifier(const DMA_Stream_TypeDef* stream)
{
for (int i = 0; i < DMA_MAX_DESCRIPTORS; i++) {
for (int i = 0; i < DMA_LAST_HANDLER; i++) {
if (dmaDescriptors[i].ref == stream) {
return i;
return i + 1;
}
}
return 0;
}
dmaChannelDescriptor_t* getDmaDescriptor(const DMA_Stream_TypeDef* stream)
dmaChannelDescriptor_t* dmaGetDescriptor(const DMA_Stream_TypeDef* stream)
{
for (int i = 0; i < DMA_MAX_DESCRIPTORS; i++) {
for (int i = 0; i < DMA_LAST_HANDLER; i++) {
if (dmaDescriptors[i].ref == stream) {
return &dmaDescriptors[i];
}
}
return NULL;
}
DMA_Stream_TypeDef* dmaGetRefByIdentifier(const dmaIdentifier_e identifier)
{
return dmaDescriptors[DMA_IDENTIFIER_TO_INDEX(identifier)].ref;
}
dmaChannelDescriptor_t* dmaGetDescriptorByIdentifier(const dmaIdentifier_e identifier)
{
return &dmaDescriptors[DMA_IDENTIFIER_TO_INDEX(identifier)];
}
uint32_t dmaGetChannel(const uint8_t channel)
{
return ((uint32_t)channel*2)<<24;
}