From 1dbd7ee732d70fd10ee3f923107b02fa963fed5d Mon Sep 17 00:00:00 2001 From: blckmn Date: Tue, 8 Nov 2016 15:47:25 +1100 Subject: [PATCH 1/6] Simplified target timer definitions --- src/main/drivers/tim_def.h | 357 +++++++++++++++++++++++++++++ src/main/drivers/timer.h | 1 + src/main/target/BLUEJAYF4/target.c | 14 ++ 3 files changed, 372 insertions(+) create mode 100644 src/main/drivers/tim_def.h diff --git a/src/main/drivers/tim_def.h b/src/main/drivers/tim_def.h new file mode 100644 index 0000000000..51090375ce --- /dev/null +++ b/src/main/drivers/tim_def.h @@ -0,0 +1,357 @@ +/* + * This file is part of Cleanflight. + * + * Cleanflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Cleanflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Cleanflight. If not, see . + */ + +#pragma once + +#include +#include "common/utils.h" + +#if defined(STM32F3) + +#define DEF_TIM(tim, chan, pin, flags, out) {\ + tim,\ + IO_TAG(pin),\ + EXPAND(DEF_CHAN_ ## chan),\ + flags,\ + (DEF_CHAN_ ## chan ## _OUTPUT | out),\ + EXPAND(GPIO_AF__ ## pin ## _ ## tim ## _ ## chan),\ + CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _TYPE),\ + CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _HANDLER)\ + } + +#define DEF_TIM_CHAN(chan) DEF_CHAN_ ## chan +#define DEF_TIM_OUTPUT(chan, out) ( DEF_CHAN_ ## chan ## _OUTPUT | out ) + +#define DEF_DMA_TYPE(tim, chan) CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _TYPE) +#define DEF_DMA_HANDLER(tim, chan) CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _HANDLER) + +/* add the DMA mappings here */ +#define DEF_TIM_DMACHAN_TIM1_CH1 DMA1_CH2 +#define DEF_TIM_DMACHAN_TIM1_CH2 DMA1_CH3 +#define DEF_TIM_DMACHAN_TIM1_CH4 DMA1_CH4 +#define DEF_TIM_DMACHAN_TIM1_TRIG DMA1_CH4 +#define DEF_TIM_DMACHAN_TIM1_COM DMA1_CH4 +#define DEF_TIM_DMACHAN_TIM1_UP DMA1_CH5 +#define DEF_TIM_DMACHAN_TIM1_CH3 DMA1_CH6 + +#define DEF_TIM_DMACHAN_TIM2_CH3 DMA1_CH1 +#define DEF_TIM_DMACHAN_TIM2_UP DMA1_CH2 +#define DEF_TIM_DMACHAN_TIM2_CH1 DMA1_CH5 +#define DEF_TIM_DMACHAN_TIM2_CH2 DMA1_CH7 +#define DEF_TIM_DMACHAN_TIM2_CH4 DMA1_CH7 + +#define DEF_TIM_DMACHAN_TIM3_CH2 DMA_NONE +#define DEF_TIM_DMACHAN_TIM3_CH3 DMA1_CH2 +#define DEF_TIM_DMACHAN_TIM3_CH4 DMA1_CH3 +#define DEF_TIM_DMACHAN_TIM3_UP DMA1_CH3 +#define DEF_TIM_DMACHAN_TIM3_CH1 DMA1_CH6 +#define DEF_TIM_DMACHAN_TIM3_TRIG DMA1_CH6 + +#define DEF_TIM_DMACHAN_TIM4_CH1 DMA1_CH1 +#define DEF_TIM_DMACHAN_TIM4_CH2 DMA1_CH4 +#define DEF_TIM_DMACHAN_TIM4_CH3 DMA1_CH5 +#define DEF_TIM_DMACHAN_TIM4_UP DMA1_CH7 +#define DEF_TIM_DMACHAN_TIM4_CH4 DMA_NONE + +#define DEF_TIM_DMACHAN_TIM15_CH1 DMA1_CH5 +#define DEF_TIM_DMACHAN_TIM15_CH2 DMA_NONE +#define DEF_TIM_DMACHAN_TIM15_UP DMA1_CH5 +#define DEF_TIM_DMACHAN_TIM15_TRIG DMA1_CH5 +#define DEF_TIM_DMACHAN_TIM15_COM DMA1_CH5 + +#ifdef DMA_TIMER16_REMAP +#define DEF_TIM_DMACHAN_TIM16_CH1 DMA1_CH6 +#define DEF_TIM_DMACHAN_TIM16_UP DMA1_CH6 +#else +#define DEF_TIM_DMACHAN_TIM16_CH1 DMA1_CH3 +#define DEF_TIM_DMACHAN_TIM16_UP DMA1_CH3 +#endif + +#ifdef DMA_TIMER17_REMAP +#define DEF_TIM_DMACHAN_TIM17_CH1 DMA1_CH7 +#define DEF_TIM_DMACHAN_TIM17_UP DMA1_CH7 +#else +#define DEF_TIM_DMACHAN_TIM17_CH1 DMA1_CH1 +#define DEF_TIM_DMACHAN_TIM17_UP DMA1_CH1 +#endif + +#define DEF_TIM_DMACHAN_TIM8_CH3 DMA2_CH1 +#define DEF_TIM_DMACHAN_TIM8_UP DMA2_CH1 +#define DEF_TIM_DMACHAN_TIM8_CH4 DMA2_CH2 +#define DEF_TIM_DMACHAN_TIM8_TRIG DMA2_CH2 +#define DEF_TIM_DMACHAN_TIM8_COM DMA2_CH2 +#define DEF_TIM_DMACHAN_TIM8_CH1 DMA2_CH3 +#define DEF_TIM_DMACHAN_TIM8_CH2 DMA2_CH5 + + +#define DMA1_CH1_TYPE DMA1_Channel1 +#define DMA1_CH2_TYPE DMA1_Channel2 +#define DMA1_CH3_TYPE DMA1_Channel3 +#define DMA1_CH4_TYPE DMA1_Channel4 +#define DMA1_CH5_TYPE DMA1_Channel5 +#define DMA1_CH6_TYPE DMA1_Channel6 +#define DMA1_CH7_TYPE DMA1_Channel7 +#define DMA2_CH1_TYPE DMA2_Channel1 +#define DMA2_CH2_TYPE DMA2_Channel2 +#define DMA2_CH3_TYPE DMA2_Channel3 +#define DMA2_CH4_TYPE DMA2_Channel4 +#define DMA2_CH5_TYPE DMA2_Channel5 +#define DMA2_CH6_TYPE DMA2_Channel6 +#define DMA2_CH7_TYPE DMA2_Channel7 + +#define GPIO_AF(p, t) CONCAT(GPIO_AF__, p, _, t) + +#define GPIO_AF__PA0_TIM2_CH1 GPIO_AF_1 +#define GPIO_AF__PA1_TIM2_CH2 GPIO_AF_1 +#define GPIO_AF__PA2_TIM2_CH3 GPIO_AF_1 +#define GPIO_AF__PA3_TIM2_CH3 GPIO_AF_1 +#define GPIO_AF__PA5_TIM2_CH1 GPIO_AF_1 +#define GPIO_AF__PA6_TIM16_CH1 GPIO_AF_1 +#define GPIO_AF__PA7_TIM17_CH1 GPIO_AF_1 +#define GPIO_AF__PA12_TIM16_CH1 GPIO_AF_1 +#define GPIO_AF__PA13_TIM16_CH1N GPIO_AF_1 +#define GPIO_AF__PA15_TIM2_CH1 GPIO_AF_1 + +#define GPIO_AF__PA4_TIM3_CH2 GPIO_AF_2 +#define GPIO_AF__PA6_TIM3_CH1 GPIO_AF_2 +#define GPIO_AF__PA7_TIM3_CH2 GPIO_AF_2 +#define GPIO_AF__PA15_TIM8_CH1 GPIO_AF_2 + +#define GPIO_AF__PA7_TIM8_CH1N GPIO_AF_4 + +#define GPIO_AF__PA14_TIM4_CH2 GPIO_AF_5 + +#define GPIO_AF__PA7_TIM1_CH1N GPIO_AF_6 +#define GPIO_AF__PA8_TIM1_CH1 GPIO_AF_6 +#define GPIO_AF__PA9_TIM1_CH2 GPIO_AF_6 +#define GPIO_AF__PA10_TIM1_CH3 GPIO_AF_6 +#define GPIO_AF__PA11_TIM1_CH1N GPIO_AF_6 +#define GPIO_AF__PA12_TIM1_CH2N GPIO_AF_6 + +#define GPIO_AF__PA1_TIM15_CH1N GPIO_AF_9 +#define GPIO_AF__PA2_TIM15_CH1 GPIO_AF_9 +#define GPIO_AF__PA3_TIM15_CH2 GPIO_AF_9 + +#define GPIO_AF__PA9_TIM2_CH3 GPIO_AF_10 +#define GPIO_AF__PA10_TIM2_CH4 GPIO_AF_10 +#define GPIO_AF__PA11_TIM4_CH1 GPIO_AF_10 +#define GPIO_AF__PA12_TIM4_CH2 GPIO_AF_10 +#define GPIO_AF__PA13_TIM4_CH3 GPIO_AF_10 +#define GPIO_AF__PA11_TIM1_CH4 GPIO_AF_11 + +#define GPIO_AF__PB3_TIM2_CH2 GPIO_AF_1 +#define GPIO_AF__PB4_TIM16_CH1 GPIO_AF_1 +#define GPIO_AF__PB6_TIM16_CH1N GPIO_AF_1 +#define GPIO_AF__PB7_TIM17_CH1N GPIO_AF_1 +#define GPIO_AF__PB8_TIM16_CH1 GPIO_AF_1 +#define GPIO_AF__PB9_TIM17_CH1 GPIO_AF_1 +#define GPIO_AF__PB10_TIM2_CH3 GPIO_AF_1 +#define GPIO_AF__PB11_TIM2_CH4 GPIO_AF_1 +#define GPIO_AF__PB14_TIM15_CH1 GPIO_AF_1 +#define GPIO_AF__PB15_TIM15_CH2 GPIO_AF_1 + +#define GPIO_AF__PB0_TIM3_CH3 GPIO_AF_2 +#define GPIO_AF__PB1_TIM3_CH4 GPIO_AF_2 +#define GPIO_AF__PB4_TIM3_CH1 GPIO_AF_2 +#define GPIO_AF__PB5_TIM3_CH2 GPIO_AF_2 +#define GPIO_AF__PB6_TIM4_CH1 GPIO_AF_2 +#define GPIO_AF__PB7_TIM4_CH2 GPIO_AF_2 +#define GPIO_AF__PB8_TIM4_CH3 GPIO_AF_2 +#define GPIO_AF__PB9_TIM4_CH4 GPIO_AF_2 +#define GPIO_AF__PB15_TIM15_CH1N GPIO_AF_2 + +#define GPIO_AF__PB0_TIM8_CH2N GPIO_AF_4 +#define GPIO_AF__PB1_TIM8_CH3N GPIO_AF_4 +#define GPIO_AF__PB3_TIM8_CH1N GPIO_AF_4 +#define GPIO_AF__PB4_TIM8_CH2N GPIO_AF_4 +#define GPIO_AF__PB15_TIM1_CH3N GPIO_AF_4 + +#define GPIO_AF__PB6_TIM8_CH1 GPIO_AF_5 + +#define GPIO_AF__PB0_TIM1_CH2N GPIO_AF_6 +#define GPIO_AF__PB1_TIM1_CH3N GPIO_AF_6 +#define GPIO_AF__PB13_TIM1_CH1N GPIO_AF_6 +#define GPIO_AF__PB14_TIM1_CH2N GPIO_AF_6 + +#define GPIO_AF__PB5_TIM17_CH1 GPIO_AF_10 +#define GPIO_AF__PB7_TIM3_CH4 GPIO_AF_10 +#define GPIO_AF__PB8_TIM8_CH2 GPIO_AF_10 +#define GPIO_AF__PB9_TIM8_CH3 GPIO_AF_10 + +#define GPIO_AF__PC6_TIM3_CH1 GPIO_AF_2 +#define GPIO_AF__PC7_TIM3_CH2 GPIO_AF_2 +#define GPIO_AF__PC8_TIM3_CH3 GPIO_AF_2 +#define GPIO_AF__PC9_TIM3_CH4 GPIO_AF_2 + +#define GPIO_AF__PC6_TIM8_CH1 GPIO_AF_4 +#define GPIO_AF__PC7_TIM8_CH2 GPIO_AF_4 +#define GPIO_AF__PC8_TIM8_CH3 GPIO_AF_4 +#define GPIO_AF__PC9_TIM8_CH4 GPIO_AF_4 + +#define GPIO_AF__PC10_TIM8_CH1N GPIO_AF_4 +#define GPIO_AF__PC11_TIM8_CH2N GPIO_AF_4 +#define GPIO_AF__PC12_TIM8_CH3N GPIO_AF_4 +#define GPIO_AF__PC13_TIM8_CH1N GPIO_AF_4 + +#define GPIO_AF__PD3_TIM2_CH1 GPIO_AF_2 +#define GPIO_AF__PD4_TIM2_CH2 GPIO_AF_2 +#define GPIO_AF__PD6_TIM2_CH4 GPIO_AF_2 +#define GPIO_AF__PD7_TIM2_CH3 GPIO_AF_2 + +#define GPIO_AF__PD12_TIM4_CH1 GPIO_AF_2 +#define GPIO_AF__PD13_TIM4_CH2 GPIO_AF_2 +#define GPIO_AF__PD14_TIM4_CH3 GPIO_AF_2 +#define GPIO_AF__PD15_TIM4_CH4 GPIO_AF_2 + +#define GPIO_AF__PD1_TIM8_CH4 GPIO_AF_4 + +#elif defined(STM32F4) + +#define DEF_TIM(tim, chan, pin, flags, out, dmaopt) {\ + tim,\ + IO_TAG(pin),\ + EXPAND(DEF_CHAN_ ## chan),\ + flags,\ + (DEF_CHAN_ ## chan ## _OUTPUT | out),\ + EXPAND(GPIO_AF_## tim),\ + CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## _ ## tim ## _ ## chan), _TYPE),\ + EXPAND(DEF_TIM_DMA_CHN_ ## dmaopt ## _ ## tim ## _ ## chan),\ + CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## _ ## tim ## _ ## chan), _HANDLER)\ + } + +/* F4 Stream Mappings */ + +#define DEF_TIM_DMA_STR_0_TIM1_CH1 DMA2_ST6 +#define DEF_TIM_DMA_STR_1_TIM1_CH1 DMA2_ST1 +#define DEF_TIM_DMA_STR_2_TIM1_CH1 DMA2_ST3 +#define DEF_TIM_DMA_STR_0_TIM1_CH2 DMA2_ST6 +#define DEF_TIM_DMA_STR_1_TIM1_CH2 DMA2_ST2 +#define DEF_TIM_DMA_STR_0_TIM1_CH3 DMA2_ST6 +#define DEF_TIM_DMA_STR_1_TIM1_CH3 DMA2_ST6 +#define DEF_TIM_DMA_STR_0_TIM1_CH4 DMA2_ST4 + +#define DEF_TIM_DMA_STR_0_TIM2_CH1 DMA1_ST5 +#define DEF_TIM_DMA_STR_0_TIM2_CH2 DMA1_ST6 +#define DEF_TIM_DMA_STR_0_TIM2_CH3 DMA1_ST1 +#define DEF_TIM_DMA_STR_0_TIM2_CH4 DMA1_ST7 +#define DEF_TIM_DMA_STR_1_TIM2_CH4 DMA1_ST6 + +#define DEF_TIM_DMA_STR_0_TIM3_CH1 DMA1_ST4 +#define DEF_TIM_DMA_STR_0_TIM3_CH2 DMA1_ST5 +#define DEF_TIM_DMA_STR_0_TIM3_CH3 DMA1_ST7 +#define DEF_TIM_DMA_STR_0_TIM3_CH4 DMA1_ST2 + +#define DEF_TIM_DMA_STR_0_TIM4_CH1 DMA1_ST0 +#define DEF_TIM_DMA_STR_0_TIM4_CH2 DMA1_ST4 +#define DEF_TIM_DMA_STR_0_TIM4_CH3 DMA1_ST7 +#define DEF_TIM_DMA_STR_0_TIM4_CH4 DMA1_ST3 + +#define DEF_TIM_DMA_STR_0_TIM5_CH1 DMA1_ST2 +#define DEF_TIM_DMA_STR_0_TIM5_CH2 DMA1_ST4 +#define DEF_TIM_DMA_STR_0_TIM5_CH3 DMA1_ST0 +#define DEF_TIM_DMA_STR_0_TIM5_CH4 DMA1_ST1 +#define DEF_TIM_DMA_STR_1_TIM5_CH4 DMA1_ST3 + +#define DEF_TIM_DMA_STR_0_TIM8_CH1 DMA2_ST2 +#define DEF_TIM_DMA_STR_1_TIM8_CH1 DMA2_ST2 +#define DEF_TIM_DMA_STR_0_TIM8_CH2 DMA2_ST3 +#define DEF_TIM_DMA_STR_1_TIM8_CH2 DMA2_ST2 +#define DEF_TIM_DMA_STR_0_TIM8_CH3 DMA2_ST2 +#define DEF_TIM_DMA_STR_0_TIM8_CH4 DMA2_ST7 + +/* F4 Channel Mappings */ + +#define DEF_TIM_DMA_CHN_0_TIM1_CH1 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_1_TIM1_CH1 DMA_Channel_6 +#define DEF_TIM_DMA_CHN_2_TIM1_CH1 DMA_Channel_6 +#define DEF_TIM_DMA_CHN_0_TIM1_CH2 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_1_TIM1_CH2 DMA_Channel_6 +#define DEF_TIM_DMA_CHN_0_TIM1_CH3 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_1_TIM1_CH3 DMA_Channel_6 +#define DEF_TIM_DMA_CHN_0_TIM1_CH4 DMA_Channel_6 + +#define DEF_TIM_DMA_CHN_0_TIM2_CH1 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0_TIM2_CH2 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0_TIM2_CH3 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0_TIM2_CH4 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_1_TIM2_CH4 DMA_Channel_3 + +#define DEF_TIM_DMA_CHN_0_TIM3_CH1 DMA_Channel_5 +#define DEF_TIM_DMA_CHN_0_TIM3_CH2 DMA_Channel_5 +#define DEF_TIM_DMA_CHN_0_TIM3_CH3 DMA_Channel_5 +#define DEF_TIM_DMA_CHN_0_TIM3_CH4 DMA_Channel_5 + +#define DEF_TIM_DMA_CHN_0_TIM4_CH1 DMA_Channel_2 +#define DEF_TIM_DMA_CHN_0_TIM4_CH2 DMA_Channel_2 +#define DEF_TIM_DMA_CHN_0_TIM4_CH3 DMA_Channel_2 +#define DEF_TIM_DMA_CHN_0_TIM4_CH4 DMA_Channel_2 + +#define DEF_TIM_DMA_CHN_0_TIM5_CH1 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0_TIM5_CH2 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0_TIM5_CH3 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0_TIM5_CH4 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_1_TIM5_CH4 DMA_Channel_3 + +#define DEF_TIM_DMA_CHN_0_TIM8_CH1 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_1_TIM8_CH1 DMA_Channel_7 +#define DEF_TIM_DMA_CHN_0_TIM8_CH2 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_1_TIM8_CH2 DMA_Channel_7 +#define DEF_TIM_DMA_CHN_0_TIM8_CH3 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_0_TIM8_CH4 DMA_Channel_7 + +#define DMA1_ST0_TYPE DMA1_Stream0 +#define DMA1_ST1_TYPE DMA1_Stream1 +#define DMA1_ST2_TYPE DMA1_Stream2 +#define DMA1_ST3_TYPE DMA1_Stream3 +#define DMA1_ST4_TYPE DMA1_Stream4 +#define DMA1_ST5_TYPE DMA1_Stream5 +#define DMA1_ST6_TYPE DMA1_Stream6 +#define DMA1_ST7_TYPE DMA1_Stream7 +#define DMA2_ST0_TYPE DMA2_Stream0 +#define DMA2_ST1_TYPE DMA2_Stream1 +#define DMA2_ST2_TYPE DMA2_Stream2 +#define DMA2_ST3_TYPE DMA2_Stream3 +#define DMA2_ST4_TYPE DMA2_Stream4 +#define DMA2_ST5_TYPE DMA2_Stream5 +#define DMA2_ST6_TYPE DMA2_Stream6 +#define DMA2_ST7_TYPE DMA2_Stream7 + +#endif + +/**** Common Defines across all targets ****/ + +#define NONE 0 +#define DMA_NONE_TYPE NULL +#define DMA_NONE_HANDLER 0 + +#define DEF_CHAN_CH1 TIM_Channel_1 +#define DEF_CHAN_CH2 TIM_Channel_2 +#define DEF_CHAN_CH3 TIM_Channel_3 +#define DEF_CHAN_CH4 TIM_Channel_4 +#define DEF_CHAN_CH1N TIM_Channel_1 +#define DEF_CHAN_CH2N TIM_Channel_2 +#define DEF_CHAN_CH3N TIM_Channel_3 +#define DEF_CHAN_CH4N TIM_Channel_4 + +#define DEF_CHAN_CH1_OUTPUT TIMER_OUTPUT_NONE +#define DEF_CHAN_CH2_OUTPUT TIMER_OUTPUT_NONE +#define DEF_CHAN_CH3_OUTPUT TIMER_OUTPUT_NONE +#define DEF_CHAN_CH4_OUTPUT TIMER_OUTPUT_NONE +#define DEF_CHAN_CH1N_OUTPUT TIMER_OUTPUT_N_CHANNEL +#define DEF_CHAN_CH2N_OUTPUT TIMER_OUTPUT_N_CHANNEL +#define DEF_CHAN_CH3N_OUTPUT TIMER_OUTPUT_N_CHANNEL +#define DEF_CHAN_CH4N_OUTPUT TIMER_OUTPUT_N_CHANNEL diff --git a/src/main/drivers/timer.h b/src/main/drivers/timer.h index a6fa48f8a9..bb7a6c5bc1 100644 --- a/src/main/drivers/timer.h +++ b/src/main/drivers/timer.h @@ -105,6 +105,7 @@ typedef struct timerHardware_s { } timerHardware_t; typedef enum { + TIMER_OUTPUT_NONE = 0x00, TIMER_INPUT_ENABLED = 0x00, TIMER_OUTPUT_ENABLED = 0x01, TIMER_OUTPUT_INVERTED = 0x02, diff --git a/src/main/target/BLUEJAYF4/target.c b/src/main/target/BLUEJAYF4/target.c index d0d2b450de..6ab553f5fa 100644 --- a/src/main/target/BLUEJAYF4/target.c +++ b/src/main/target/BLUEJAYF4/target.c @@ -22,6 +22,9 @@ #include "drivers/timer.h" #include "drivers/dma.h" +#include "drivers/tim_def.h" + +/* const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { { TIM8, IO_TAG(PC7), TIM_Channel_2, TIM_USE_PPM, 0, GPIO_AF_TIM8, NULL, 0, 0 }, // PPM IN { TIM5, IO_TAG(PA0), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_TIM5, DMA1_Stream2, DMA_Channel_6, DMA1_ST2_HANDLER }, // S1_OUT @@ -31,4 +34,15 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { { TIM3, IO_TAG(PB1), TIM_Channel_4, TIM_USE_MOTOR | TIM_USE_LED, 1, GPIO_AF_TIM3, DMA1_Stream2, DMA_Channel_5, DMA1_ST2_HANDLER }, // S5_OUT { TIM3, IO_TAG(PB0), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_TIM3, DMA1_Stream7, DMA_Channel_5, DMA1_ST7_HANDLER }, // S6_OUT }; +*/ + +const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { + DEF_TIM(TIM8, CH2, PC7, TIM_USE_PPM, 0, 0 ), // PPM IN + DEF_TIM(TIM5, CH1, PA0, TIM_USE_MOTOR, 0, 0 ), // S1_OUT + DEF_TIM(TIM5, CH2, PA1, TIM_USE_MOTOR, 0, 0 ), // S2_OUT + DEF_TIM(TIM2, CH3, PA2, TIM_USE_MOTOR, 0, 0 ), // S3_OUT + DEF_TIM(TIM2, CH4, PA3, TIM_USE_MOTOR, 0, 0 ), // S4_OUT + DEF_TIM(TIM3, CH4, PB1, TIM_USE_MOTOR | TIM_USE_LED, 0, 0 ), // S5_OUT + DEF_TIM(TIM3, CH3, PB0, TIM_USE_MOTOR, 0, 0 ), // S6_OUT +}; From 1a8f11261e3ac39e0bd532d148f4a30bdef20191 Mon Sep 17 00:00:00 2001 From: blckmn Date: Wed, 9 Nov 2016 08:47:43 +1100 Subject: [PATCH 2/6] Updates following review --- src/main/drivers/tim_def.h | 308 +++++++++++++++++++------------------ 1 file changed, 156 insertions(+), 152 deletions(-) diff --git a/src/main/drivers/tim_def.h b/src/main/drivers/tim_def.h index 51090375ce..e41260f86e 100644 --- a/src/main/drivers/tim_def.h +++ b/src/main/drivers/tim_def.h @@ -33,85 +33,82 @@ CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _HANDLER)\ } -#define DEF_TIM_CHAN(chan) DEF_CHAN_ ## chan -#define DEF_TIM_OUTPUT(chan, out) ( DEF_CHAN_ ## chan ## _OUTPUT | out ) - -#define DEF_DMA_TYPE(tim, chan) CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _TYPE) -#define DEF_DMA_HANDLER(tim, chan) CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _HANDLER) +#define DEF_DMA_CHANNEL(tim, chan) CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _CHANNEL) +#define DEF_DMA_HANDLER(tim, chan) CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _HANDLER) /* add the DMA mappings here */ -#define DEF_TIM_DMACHAN_TIM1_CH1 DMA1_CH2 -#define DEF_TIM_DMACHAN_TIM1_CH2 DMA1_CH3 -#define DEF_TIM_DMACHAN_TIM1_CH4 DMA1_CH4 -#define DEF_TIM_DMACHAN_TIM1_TRIG DMA1_CH4 -#define DEF_TIM_DMACHAN_TIM1_COM DMA1_CH4 -#define DEF_TIM_DMACHAN_TIM1_UP DMA1_CH5 -#define DEF_TIM_DMACHAN_TIM1_CH3 DMA1_CH6 +#define DEF_TIM_DMA__TIM1_CH1 DMA1_CH2 +#define DEF_TIM_DMA__TIM1_CH2 DMA1_CH3 +#define DEF_TIM_DMA__TIM1_CH4 DMA1_CH4 +#define DEF_TIM_DMA__TIM1_TRIG DMA1_CH4 +#define DEF_TIM_DMA__TIM1_COM DMA1_CH4 +#define DEF_TIM_DMA__TIM1_UP DMA1_CH5 +#define DEF_TIM_DMA__TIM1_CH3 DMA1_CH6 -#define DEF_TIM_DMACHAN_TIM2_CH3 DMA1_CH1 -#define DEF_TIM_DMACHAN_TIM2_UP DMA1_CH2 -#define DEF_TIM_DMACHAN_TIM2_CH1 DMA1_CH5 -#define DEF_TIM_DMACHAN_TIM2_CH2 DMA1_CH7 -#define DEF_TIM_DMACHAN_TIM2_CH4 DMA1_CH7 +#define DEF_TIM_DMA__TIM2_CH3 DMA1_CH1 +#define DEF_TIM_DMA__TIM2_UP DMA1_CH2 +#define DEF_TIM_DMA__TIM2_CH1 DMA1_CH5 +#define DEF_TIM_DMA__TIM2_CH2 DMA1_CH7 +#define DEF_TIM_DMA__TIM2_CH4 DMA1_CH7 -#define DEF_TIM_DMACHAN_TIM3_CH2 DMA_NONE -#define DEF_TIM_DMACHAN_TIM3_CH3 DMA1_CH2 -#define DEF_TIM_DMACHAN_TIM3_CH4 DMA1_CH3 -#define DEF_TIM_DMACHAN_TIM3_UP DMA1_CH3 -#define DEF_TIM_DMACHAN_TIM3_CH1 DMA1_CH6 -#define DEF_TIM_DMACHAN_TIM3_TRIG DMA1_CH6 +#define DEF_TIM_DMA__TIM3_CH2 DMA_NONE +#define DEF_TIM_DMA__TIM3_CH3 DMA1_CH2 +#define DEF_TIM_DMA__TIM3_CH4 DMA1_CH3 +#define DEF_TIM_DMA__TIM3_UP DMA1_CH3 +#define DEF_TIM_DMA__TIM3_CH1 DMA1_CH6 +#define DEF_TIM_DMA__TIM3_TRIG DMA1_CH6 -#define DEF_TIM_DMACHAN_TIM4_CH1 DMA1_CH1 -#define DEF_TIM_DMACHAN_TIM4_CH2 DMA1_CH4 -#define DEF_TIM_DMACHAN_TIM4_CH3 DMA1_CH5 -#define DEF_TIM_DMACHAN_TIM4_UP DMA1_CH7 -#define DEF_TIM_DMACHAN_TIM4_CH4 DMA_NONE +#define DEF_TIM_DMA__TIM4_CH1 DMA1_CH1 +#define DEF_TIM_DMA__TIM4_CH2 DMA1_CH4 +#define DEF_TIM_DMA__TIM4_CH3 DMA1_CH5 +#define DEF_TIM_DMA__TIM4_UP DMA1_CH7 +#define DEF_TIM_DMA__TIM4_CH4 DMA_NONE -#define DEF_TIM_DMACHAN_TIM15_CH1 DMA1_CH5 -#define DEF_TIM_DMACHAN_TIM15_CH2 DMA_NONE -#define DEF_TIM_DMACHAN_TIM15_UP DMA1_CH5 -#define DEF_TIM_DMACHAN_TIM15_TRIG DMA1_CH5 -#define DEF_TIM_DMACHAN_TIM15_COM DMA1_CH5 +#define DEF_TIM_DMA__TIM15_CH1 DMA1_CH5 +#define DEF_TIM_DMA__TIM15_CH2 DMA_NONE +#define DEF_TIM_DMA__TIM15_UP DMA1_CH5 +#define DEF_TIM_DMA__TIM15_TRIG DMA1_CH5 +#define DEF_TIM_DMA__TIM15_COM DMA1_CH5 #ifdef DMA_TIMER16_REMAP -#define DEF_TIM_DMACHAN_TIM16_CH1 DMA1_CH6 -#define DEF_TIM_DMACHAN_TIM16_UP DMA1_CH6 +#define DEF_TIM_DMA__TIM16_CH1 DMA1_CH6 +#define DEF_TIM_DMA__TIM16_UP DMA1_CH6 #else -#define DEF_TIM_DMACHAN_TIM16_CH1 DMA1_CH3 -#define DEF_TIM_DMACHAN_TIM16_UP DMA1_CH3 +#define DEF_TIM_DMA__TIM16_CH1 DMA1_CH3 +#define DEF_TIM_DMA__TIM16_UP DMA1_CH3 #endif #ifdef DMA_TIMER17_REMAP -#define DEF_TIM_DMACHAN_TIM17_CH1 DMA1_CH7 -#define DEF_TIM_DMACHAN_TIM17_UP DMA1_CH7 +#define DEF_TIM_DMA__TIM17_CH1 DMA1_CH7 +#define DEF_TIM_DMA__TIM17_UP DMA1_CH7 #else -#define DEF_TIM_DMACHAN_TIM17_CH1 DMA1_CH1 -#define DEF_TIM_DMACHAN_TIM17_UP DMA1_CH1 +#define DEF_TIM_DMA__TIM17_CH1 DMA1_CH1 +#define DEF_TIM_DMA__TIM17_UP DMA1_CH1 #endif -#define DEF_TIM_DMACHAN_TIM8_CH3 DMA2_CH1 -#define DEF_TIM_DMACHAN_TIM8_UP DMA2_CH1 -#define DEF_TIM_DMACHAN_TIM8_CH4 DMA2_CH2 -#define DEF_TIM_DMACHAN_TIM8_TRIG DMA2_CH2 -#define DEF_TIM_DMACHAN_TIM8_COM DMA2_CH2 -#define DEF_TIM_DMACHAN_TIM8_CH1 DMA2_CH3 -#define DEF_TIM_DMACHAN_TIM8_CH2 DMA2_CH5 +#define DEF_TIM_DMA__TIM8_CH3 DMA2_CH1 +#define DEF_TIM_DMA__TIM8_UP DMA2_CH1 +#define DEF_TIM_DMA__TIM8_CH4 DMA2_CH2 +#define DEF_TIM_DMA__TIM8_TRIG DMA2_CH2 +#define DEF_TIM_DMA__TIM8_COM DMA2_CH2 +#define DEF_TIM_DMA__TIM8_CH1 DMA2_CH3 +#define DEF_TIM_DMA__TIM8_CH2 DMA2_CH5 -#define DMA1_CH1_TYPE DMA1_Channel1 -#define DMA1_CH2_TYPE DMA1_Channel2 -#define DMA1_CH3_TYPE DMA1_Channel3 -#define DMA1_CH4_TYPE DMA1_Channel4 -#define DMA1_CH5_TYPE DMA1_Channel5 -#define DMA1_CH6_TYPE DMA1_Channel6 -#define DMA1_CH7_TYPE DMA1_Channel7 -#define DMA2_CH1_TYPE DMA2_Channel1 -#define DMA2_CH2_TYPE DMA2_Channel2 -#define DMA2_CH3_TYPE DMA2_Channel3 -#define DMA2_CH4_TYPE DMA2_Channel4 -#define DMA2_CH5_TYPE DMA2_Channel5 -#define DMA2_CH6_TYPE DMA2_Channel6 -#define DMA2_CH7_TYPE DMA2_Channel7 +#define DMA1_CH1_CHANNEL DMA1_Channel1 +#define DMA1_CH2_CHANNEL DMA1_Channel2 +#define DMA1_CH3_CHANNEL DMA1_Channel3 +#define DMA1_CH4_CHANNEL DMA1_Channel4 +#define DMA1_CH5_CHANNEL DMA1_Channel5 +#define DMA1_CH6_CHANNEL DMA1_Channel6 +#define DMA1_CH7_CHANNEL DMA1_Channel7 +#define DMA2_CH1_CHANNEL DMA2_Channel1 +#define DMA2_CH2_CHANNEL DMA2_Channel2 +#define DMA2_CH3_CHANNEL DMA2_Channel3 +#define DMA2_CH4_CHANNEL DMA2_Channel4 +#define DMA2_CH5_CHANNEL DMA2_Channel5 +#define DMA2_CH6_CHANNEL DMA2_Channel6 +#define DMA2_CH7_CHANNEL DMA2_Channel7 #define GPIO_AF(p, t) CONCAT(GPIO_AF__, p, _, t) @@ -212,12 +209,12 @@ #define GPIO_AF__PD6_TIM2_CH4 GPIO_AF_2 #define GPIO_AF__PD7_TIM2_CH3 GPIO_AF_2 -#define GPIO_AF__PD12_TIM4_CH1 GPIO_AF_2 -#define GPIO_AF__PD13_TIM4_CH2 GPIO_AF_2 -#define GPIO_AF__PD14_TIM4_CH3 GPIO_AF_2 -#define GPIO_AF__PD15_TIM4_CH4 GPIO_AF_2 +#define GPIO_AF__PD12_TIM4_CH1 GPIO_AF_2 +#define GPIO_AF__PD13_TIM4_CH2 GPIO_AF_2 +#define GPIO_AF__PD14_TIM4_CH3 GPIO_AF_2 +#define GPIO_AF__PD15_TIM4_CH4 GPIO_AF_2 -#define GPIO_AF__PD1_TIM8_CH4 GPIO_AF_4 +#define GPIO_AF__PD1_TIM8_CH4 GPIO_AF_4 #elif defined(STM32F4) @@ -228,114 +225,121 @@ flags,\ (DEF_CHAN_ ## chan ## _OUTPUT | out),\ EXPAND(GPIO_AF_## tim),\ - CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## _ ## tim ## _ ## chan), _TYPE),\ - EXPAND(DEF_TIM_DMA_CHN_ ## dmaopt ## _ ## tim ## _ ## chan),\ - CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## _ ## tim ## _ ## chan), _HANDLER)\ + CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _STREAM),\ + EXPAND(DEF_TIM_DMA_CHN_ ## dmaopt ## __ ## tim ## _ ## chan),\ + CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _HANDLER)\ } +#define DEF_DMA_CHANNEL(tim, chan, dmaopt) EXPAND(DEF_TIM_DMA_CHN_ ## dmaopt ## __ ## tim ## _ ## chan) +#define DEF_DMA_STREAM(tim, chan, dmaopt) CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _STREAM) +#define DEF_DMA_HANDLER(tim, chan, dmaopt) CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _HANDLER) + /* F4 Stream Mappings */ -#define DEF_TIM_DMA_STR_0_TIM1_CH1 DMA2_ST6 -#define DEF_TIM_DMA_STR_1_TIM1_CH1 DMA2_ST1 -#define DEF_TIM_DMA_STR_2_TIM1_CH1 DMA2_ST3 -#define DEF_TIM_DMA_STR_0_TIM1_CH2 DMA2_ST6 -#define DEF_TIM_DMA_STR_1_TIM1_CH2 DMA2_ST2 -#define DEF_TIM_DMA_STR_0_TIM1_CH3 DMA2_ST6 -#define DEF_TIM_DMA_STR_1_TIM1_CH3 DMA2_ST6 -#define DEF_TIM_DMA_STR_0_TIM1_CH4 DMA2_ST4 +#define DEF_TIM_DMA_STR_0__TIM1_CH1 DMA2_ST6 +#define DEF_TIM_DMA_STR_1__TIM1_CH1 DMA2_ST1 +#define DEF_TIM_DMA_STR_2__TIM1_CH1 DMA2_ST3 +#define DEF_TIM_DMA_STR_0__TIM1_CH2 DMA2_ST6 +#define DEF_TIM_DMA_STR_1__TIM1_CH2 DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM1_CH3 DMA2_ST6 +#define DEF_TIM_DMA_STR_1__TIM1_CH3 DMA2_ST6 +#define DEF_TIM_DMA_STR_0__TIM1_CH4 DMA2_ST4 -#define DEF_TIM_DMA_STR_0_TIM2_CH1 DMA1_ST5 -#define DEF_TIM_DMA_STR_0_TIM2_CH2 DMA1_ST6 -#define DEF_TIM_DMA_STR_0_TIM2_CH3 DMA1_ST1 -#define DEF_TIM_DMA_STR_0_TIM2_CH4 DMA1_ST7 -#define DEF_TIM_DMA_STR_1_TIM2_CH4 DMA1_ST6 +#define DEF_TIM_DMA_STR_0__TIM2_CH1 DMA1_ST5 +#define DEF_TIM_DMA_STR_0__TIM2_CH2 DMA1_ST6 +#define DEF_TIM_DMA_STR_0__TIM2_CH3 DMA1_ST1 +#define DEF_TIM_DMA_STR_0__TIM2_CH4 DMA1_ST7 +#define DEF_TIM_DMA_STR_1__TIM2_CH4 DMA1_ST6 -#define DEF_TIM_DMA_STR_0_TIM3_CH1 DMA1_ST4 -#define DEF_TIM_DMA_STR_0_TIM3_CH2 DMA1_ST5 -#define DEF_TIM_DMA_STR_0_TIM3_CH3 DMA1_ST7 -#define DEF_TIM_DMA_STR_0_TIM3_CH4 DMA1_ST2 +#define DEF_TIM_DMA_STR_0__TIM3_CH1 DMA1_ST4 +#define DEF_TIM_DMA_STR_0__TIM3_CH2 DMA1_ST5 +#define DEF_TIM_DMA_STR_0__TIM3_CH3 DMA1_ST7 +#define DEF_TIM_DMA_STR_0__TIM3_CH4 DMA1_ST2 -#define DEF_TIM_DMA_STR_0_TIM4_CH1 DMA1_ST0 -#define DEF_TIM_DMA_STR_0_TIM4_CH2 DMA1_ST4 -#define DEF_TIM_DMA_STR_0_TIM4_CH3 DMA1_ST7 -#define DEF_TIM_DMA_STR_0_TIM4_CH4 DMA1_ST3 +#define DEF_TIM_DMA_STR_0__TIM4_CH1 DMA1_ST0 +#define DEF_TIM_DMA_STR_0__TIM4_CH2 DMA1_ST4 +#define DEF_TIM_DMA_STR_0__TIM4_CH3 DMA1_ST7 +#define DEF_TIM_DMA_STR_0__TIM4_CH4 DMA1_ST3 -#define DEF_TIM_DMA_STR_0_TIM5_CH1 DMA1_ST2 -#define DEF_TIM_DMA_STR_0_TIM5_CH2 DMA1_ST4 -#define DEF_TIM_DMA_STR_0_TIM5_CH3 DMA1_ST0 -#define DEF_TIM_DMA_STR_0_TIM5_CH4 DMA1_ST1 -#define DEF_TIM_DMA_STR_1_TIM5_CH4 DMA1_ST3 +#define DEF_TIM_DMA_STR_0__TIM5_CH1 DMA1_ST2 +#define DEF_TIM_DMA_STR_0__TIM5_CH2 DMA1_ST4 +#define DEF_TIM_DMA_STR_0__TIM5_CH3 DMA1_ST0 +#define DEF_TIM_DMA_STR_0__TIM5_CH4 DMA1_ST1 +#define DEF_TIM_DMA_STR_1__TIM5_CH4 DMA1_ST3 -#define DEF_TIM_DMA_STR_0_TIM8_CH1 DMA2_ST2 -#define DEF_TIM_DMA_STR_1_TIM8_CH1 DMA2_ST2 -#define DEF_TIM_DMA_STR_0_TIM8_CH2 DMA2_ST3 -#define DEF_TIM_DMA_STR_1_TIM8_CH2 DMA2_ST2 -#define DEF_TIM_DMA_STR_0_TIM8_CH3 DMA2_ST2 -#define DEF_TIM_DMA_STR_0_TIM8_CH4 DMA2_ST7 +#define DEF_TIM_DMA_STR_0__TIM8_CH1 DMA2_ST2 +#define DEF_TIM_DMA_STR_1__TIM8_CH1 DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM8_CH2 DMA2_ST3 +#define DEF_TIM_DMA_STR_1__TIM8_CH2 DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM8_CH3 DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM8_CH4 DMA2_ST7 /* F4 Channel Mappings */ -#define DEF_TIM_DMA_CHN_0_TIM1_CH1 DMA_Channel_0 -#define DEF_TIM_DMA_CHN_1_TIM1_CH1 DMA_Channel_6 -#define DEF_TIM_DMA_CHN_2_TIM1_CH1 DMA_Channel_6 -#define DEF_TIM_DMA_CHN_0_TIM1_CH2 DMA_Channel_0 -#define DEF_TIM_DMA_CHN_1_TIM1_CH2 DMA_Channel_6 -#define DEF_TIM_DMA_CHN_0_TIM1_CH3 DMA_Channel_0 -#define DEF_TIM_DMA_CHN_1_TIM1_CH3 DMA_Channel_6 -#define DEF_TIM_DMA_CHN_0_TIM1_CH4 DMA_Channel_6 +#define DEF_TIM_DMA_CHN_0__TIM1_CH1 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_1__TIM1_CH1 DMA_Channel_6 +#define DEF_TIM_DMA_CHN_2__TIM1_CH1 DMA_Channel_6 +#define DEF_TIM_DMA_CHN_0__TIM1_CH2 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_1__TIM1_CH2 DMA_Channel_6 +#define DEF_TIM_DMA_CHN_0__TIM1_CH3 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_1__TIM1_CH3 DMA_Channel_6 +#define DEF_TIM_DMA_CHN_0__TIM1_CH4 DMA_Channel_6 -#define DEF_TIM_DMA_CHN_0_TIM2_CH1 DMA_Channel_3 -#define DEF_TIM_DMA_CHN_0_TIM2_CH2 DMA_Channel_3 -#define DEF_TIM_DMA_CHN_0_TIM2_CH3 DMA_Channel_3 -#define DEF_TIM_DMA_CHN_0_TIM2_CH4 DMA_Channel_3 -#define DEF_TIM_DMA_CHN_1_TIM2_CH4 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0__TIM2_CH1 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0__TIM2_CH2 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0__TIM2_CH3 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0__TIM2_CH4 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_1__TIM2_CH4 DMA_Channel_3 -#define DEF_TIM_DMA_CHN_0_TIM3_CH1 DMA_Channel_5 -#define DEF_TIM_DMA_CHN_0_TIM3_CH2 DMA_Channel_5 -#define DEF_TIM_DMA_CHN_0_TIM3_CH3 DMA_Channel_5 -#define DEF_TIM_DMA_CHN_0_TIM3_CH4 DMA_Channel_5 +#define DEF_TIM_DMA_CHN_0__TIM3_CH1 DMA_Channel_5 +#define DEF_TIM_DMA_CHN_0__TIM3_CH2 DMA_Channel_5 +#define DEF_TIM_DMA_CHN_0__TIM3_CH3 DMA_Channel_5 +#define DEF_TIM_DMA_CHN_0__TIM3_CH4 DMA_Channel_5 -#define DEF_TIM_DMA_CHN_0_TIM4_CH1 DMA_Channel_2 -#define DEF_TIM_DMA_CHN_0_TIM4_CH2 DMA_Channel_2 -#define DEF_TIM_DMA_CHN_0_TIM4_CH3 DMA_Channel_2 -#define DEF_TIM_DMA_CHN_0_TIM4_CH4 DMA_Channel_2 +#define DEF_TIM_DMA_CHN_0__TIM4_CH1 DMA_Channel_2 +#define DEF_TIM_DMA_CHN_0__TIM4_CH2 DMA_Channel_2 +#define DEF_TIM_DMA_CHN_0__TIM4_CH3 DMA_Channel_2 +#define DEF_TIM_DMA_CHN_0__TIM4_CH4 DMA_Channel_2 -#define DEF_TIM_DMA_CHN_0_TIM5_CH1 DMA_Channel_3 -#define DEF_TIM_DMA_CHN_0_TIM5_CH2 DMA_Channel_3 -#define DEF_TIM_DMA_CHN_0_TIM5_CH3 DMA_Channel_3 -#define DEF_TIM_DMA_CHN_0_TIM5_CH4 DMA_Channel_3 -#define DEF_TIM_DMA_CHN_1_TIM5_CH4 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0__TIM5_CH1 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0__TIM5_CH2 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0__TIM5_CH3 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_0__TIM5_CH4 DMA_Channel_3 +#define DEF_TIM_DMA_CHN_1__TIM5_CH4 DMA_Channel_3 -#define DEF_TIM_DMA_CHN_0_TIM8_CH1 DMA_Channel_0 -#define DEF_TIM_DMA_CHN_1_TIM8_CH1 DMA_Channel_7 -#define DEF_TIM_DMA_CHN_0_TIM8_CH2 DMA_Channel_0 -#define DEF_TIM_DMA_CHN_1_TIM8_CH2 DMA_Channel_7 -#define DEF_TIM_DMA_CHN_0_TIM8_CH3 DMA_Channel_0 -#define DEF_TIM_DMA_CHN_0_TIM8_CH4 DMA_Channel_7 +#define DEF_TIM_DMA_CHN_0__TIM8_CH1 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_1__TIM8_CH1 DMA_Channel_7 +#define DEF_TIM_DMA_CHN_0__TIM8_CH2 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_1__TIM8_CH2 DMA_Channel_7 +#define DEF_TIM_DMA_CHN_0__TIM8_CH3 DMA_Channel_0 +#define DEF_TIM_DMA_CHN_0__TIM8_CH4 DMA_Channel_7 -#define DMA1_ST0_TYPE DMA1_Stream0 -#define DMA1_ST1_TYPE DMA1_Stream1 -#define DMA1_ST2_TYPE DMA1_Stream2 -#define DMA1_ST3_TYPE DMA1_Stream3 -#define DMA1_ST4_TYPE DMA1_Stream4 -#define DMA1_ST5_TYPE DMA1_Stream5 -#define DMA1_ST6_TYPE DMA1_Stream6 -#define DMA1_ST7_TYPE DMA1_Stream7 -#define DMA2_ST0_TYPE DMA2_Stream0 -#define DMA2_ST1_TYPE DMA2_Stream1 -#define DMA2_ST2_TYPE DMA2_Stream2 -#define DMA2_ST3_TYPE DMA2_Stream3 -#define DMA2_ST4_TYPE DMA2_Stream4 -#define DMA2_ST5_TYPE DMA2_Stream5 -#define DMA2_ST6_TYPE DMA2_Stream6 -#define DMA2_ST7_TYPE DMA2_Stream7 +#define DMA1_ST0_STREAM DMA1_Stream0 +#define DMA1_ST1_STREAM DMA1_Stream1 +#define DMA1_ST2_STREAM DMA1_Stream2 +#define DMA1_ST3_STREAM DMA1_Stream3 +#define DMA1_ST4_STREAM DMA1_Stream4 +#define DMA1_ST5_STREAM DMA1_Stream5 +#define DMA1_ST6_STREAM DMA1_Stream6 +#define DMA1_ST7_STREAM DMA1_Stream7 +#define DMA2_ST0_STREAM DMA2_Stream0 +#define DMA2_ST1_STREAM DMA2_Stream1 +#define DMA2_ST2_STREAM DMA2_Stream2 +#define DMA2_ST3_STREAM DMA2_Stream3 +#define DMA2_ST4_STREAM DMA2_Stream4 +#define DMA2_ST5_STREAM DMA2_Stream5 +#define DMA2_ST6_STREAM DMA2_Stream6 +#define DMA2_ST7_STREAM DMA2_Stream7 #endif /**** Common Defines across all targets ****/ -#define NONE 0 -#define DMA_NONE_TYPE NULL +#define DEF_TIM_CHAN(chan) DEF_CHAN_ ## chan +#define DEF_TIM_OUTPUT(chan, out) ( DEF_CHAN_ ## chan ## _OUTPUT | out ) + +#define DMA_NONE_CHANNEL NULL +#define DMA_NONE_STREAM NULL #define DMA_NONE_HANDLER 0 #define DEF_CHAN_CH1 TIM_Channel_1 From 2cacc9671010f38a01a0268dcacf0cf9cc21b618 Mon Sep 17 00:00:00 2001 From: blckmn Date: Wed, 9 Nov 2016 16:31:36 +1100 Subject: [PATCH 3/6] Rename file, and fix F3 support. Added DSHOT support to DOGE (requires testing) --- src/main/drivers/{tim_def.h => timer_def.h} | 4 ++-- src/main/target/BLUEJAYF4/target.c | 2 +- src/main/target/DOGE/target.c | 21 +++++++++++---------- src/main/target/DOGE/target.h | 1 + 4 files changed, 15 insertions(+), 13 deletions(-) rename src/main/drivers/{tim_def.h => timer_def.h} (99%) diff --git a/src/main/drivers/tim_def.h b/src/main/drivers/timer_def.h similarity index 99% rename from src/main/drivers/tim_def.h rename to src/main/drivers/timer_def.h index e41260f86e..81d1c810f3 100644 --- a/src/main/drivers/tim_def.h +++ b/src/main/drivers/timer_def.h @@ -29,8 +29,8 @@ flags,\ (DEF_CHAN_ ## chan ## _OUTPUT | out),\ EXPAND(GPIO_AF__ ## pin ## _ ## tim ## _ ## chan),\ - CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _TYPE),\ - CONCAT(EXPAND(DEF_TIM_DMACHAN_ ## tim ## _ ## chan), _HANDLER)\ + CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _CHANNEL),\ + CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _HANDLER)\ } #define DEF_DMA_CHANNEL(tim, chan) CONCAT(EXPAND(DEF_TIM_DMA__ ## tim ## _ ## chan), _CHANNEL) diff --git a/src/main/target/BLUEJAYF4/target.c b/src/main/target/BLUEJAYF4/target.c index 6ab553f5fa..8bbbe806a9 100644 --- a/src/main/target/BLUEJAYF4/target.c +++ b/src/main/target/BLUEJAYF4/target.c @@ -22,7 +22,7 @@ #include "drivers/timer.h" #include "drivers/dma.h" -#include "drivers/tim_def.h" +#include "drivers/timer_def.h" /* const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { diff --git a/src/main/target/DOGE/target.c b/src/main/target/DOGE/target.c index 243de4dc18..92957613d5 100644 --- a/src/main/target/DOGE/target.c +++ b/src/main/target/DOGE/target.c @@ -22,16 +22,17 @@ #include "drivers/timer.h" #include "drivers/dma.h" +#include "drivers/timer_def.h" const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { - { TIM1, IO_TAG(PA8), TIM_Channel_1, TIM_USE_PPM, 0, GPIO_AF_6 , NULL, 0 }, // PWM1 - PA8 - { TIM4, IO_TAG(PB8), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_2 , NULL, 0 }, // PWM2 - PB8 - { TIM4, IO_TAG(PB9), TIM_Channel_4, TIM_USE_MOTOR, 1, GPIO_AF_2 , NULL, 0 }, // PWM3 - PB9 - { TIM2, IO_TAG(PA10), TIM_Channel_4, TIM_USE_MOTOR, 1, GPIO_AF_10, NULL, 0 }, // PMW4 - PA10 - { TIM2, IO_TAG(PA9), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_10, NULL, 0 }, // PWM5 - PA9 - { TIM2, IO_TAG(PA0), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_1 , NULL, 0 }, // PWM6 - PA0 - { TIM2, IO_TAG(PA1), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_1 , NULL, 0 }, // PWM7 - PA1 - { TIM3, IO_TAG(PB0), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_2 , NULL, 0 }, // PWM8 - PB1 - { TIM3, IO_TAG(PB1), TIM_Channel_4, TIM_USE_MOTOR, 1, GPIO_AF_2 , NULL, 0 }, // PWM9 - PB0 - { TIM16, IO_TAG(PA6), TIM_Channel_1, TIM_USE_LED, 1, GPIO_AF_1, DMA1_Channel3, DMA1_CH3_HANDLER }, // PWM9 - PB0 + DEF_TIM(TIM1, CH1, PA8, TIM_USE_PPM, 0), // PWM1 - PA8 + DEF_TIM(TIM4, CH3, PB8, TIM_USE_MOTOR, 1), // PWM2 - PB8 + DEF_TIM(TIM4, CH4, PB9, TIM_USE_MOTOR, 1), // PWM3 - PB9 + DEF_TIM(TIM2, CH4, PA10, TIM_USE_MOTOR, 1), // PMW4 - PA10 + DEF_TIM(TIM2, CH3, PA9, TIM_USE_MOTOR, 1), // PWM5 - PA9 + DEF_TIM(TIM2, CH1, PA0, TIM_USE_MOTOR, 1), // PWM6 - PA0 + DEF_TIM(TIM2, CH2, PA1, TIM_USE_MOTOR, 1), // PWM7 - PA1 + DEF_TIM(TIM3, CH3, PB0, TIM_USE_MOTOR, 1), // PWM8 - PB1 + DEF_TIM(TIM3, CH4, PB1, TIM_USE_MOTOR, 1), // PWM9 - PB0 + DEF_TIM(TIM16, CH1, PA6, TIM_USE_LED, 1), // PWM9 - PB0 }; diff --git a/src/main/target/DOGE/target.h b/src/main/target/DOGE/target.h index ff03fbe1bd..ee10bfd70f 100644 --- a/src/main/target/DOGE/target.h +++ b/src/main/target/DOGE/target.h @@ -124,6 +124,7 @@ #define ENSURE_MPU_DATA_READY_IS_LOW #define LED_STRIP +#define USE_DSHOT #define DEFAULT_RX_FEATURE FEATURE_RX_PPM From 97a83abab31107665148b726cd156c28cc3f2fd4 Mon Sep 17 00:00:00 2001 From: blckmn Date: Wed, 9 Nov 2016 17:13:00 +1100 Subject: [PATCH 4/6] Added more targets for DSHOT --- src/main/drivers/timer_def.h | 33 ++++++++++++++++++++++++++++-- src/main/target/MOTOLAB/target.c | 21 ++++++++++--------- src/main/target/MOTOLAB/target.h | 1 + src/main/target/RMDO/target.c | 35 ++++++++++++++++---------------- src/main/target/RMDO/target.h | 1 + src/main/target/SOULF4/target.c | 25 ++++++++++++----------- src/main/target/SOULF4/target.h | 1 + src/main/target/SPARKY2/target.c | 24 ++++++++++++---------- src/main/target/SPARKY2/target.h | 3 ++- 9 files changed, 91 insertions(+), 53 deletions(-) diff --git a/src/main/drivers/timer_def.h b/src/main/drivers/timer_def.h index 81d1c810f3..1ddf0bc771 100644 --- a/src/main/drivers/timer_def.h +++ b/src/main/drivers/timer_def.h @@ -274,6 +274,20 @@ #define DEF_TIM_DMA_STR_0__TIM8_CH3 DMA2_ST2 #define DEF_TIM_DMA_STR_0__TIM8_CH4 DMA2_ST7 +#define DEF_TIM_DMA_STR_0__TIM9_CH1 DMA_NONE +#define DEF_TIM_DMA_STR_0__TIM9_CH2 DMA_NONE + +#define DEF_TIM_DMA_STR_0__TIM10_CH1 DMA_NONE + +#define DEF_TIM_DMA_STR_0__TIM11_CH1 DMA_NONE + +#define DEF_TIM_DMA_STR_0__TIM12_CH1 DMA_NONE +#define DEF_TIM_DMA_STR_0__TIM12_CH2 DMA_NONE + +#define DEF_TIM_DMA_STR_0__TIM13_CH1 DMA_NONE + +#define DEF_TIM_DMA_STR_0__TIM14_CH1 DMA_NONE + /* F4 Channel Mappings */ #define DEF_TIM_DMA_CHN_0__TIM1_CH1 DMA_Channel_0 @@ -314,6 +328,20 @@ #define DEF_TIM_DMA_CHN_0__TIM8_CH3 DMA_Channel_0 #define DEF_TIM_DMA_CHN_0__TIM8_CH4 DMA_Channel_7 +#define DEF_TIM_DMA_CHN_0__TIM9_CH1 0 +#define DEF_TIM_DMA_CHN_0__TIM9_CH2 0 + +#define DEF_TIM_DMA_CHN_0__TIM10_CH1 0 + +#define DEF_TIM_DMA_CHN_0__TIM11_CH1 0 + +#define DEF_TIM_DMA_CHN_0__TIM12_CH1 0 +#define DEF_TIM_DMA_CHN_0__TIM12_CH2 0 + +#define DEF_TIM_DMA_CHN_0__TIM13_CH1 0 + +#define DEF_TIM_DMA_CHN_0__TIM14_CH1 0 + #define DMA1_ST0_STREAM DMA1_Stream0 #define DMA1_ST1_STREAM DMA1_Stream1 #define DMA1_ST2_STREAM DMA1_Stream2 @@ -334,12 +362,13 @@ #endif /**** Common Defines across all targets ****/ +#define DMA_NONE_CHANNEL NULL +#define DMA_NONE_STREAM NULL + #define DEF_TIM_CHAN(chan) DEF_CHAN_ ## chan #define DEF_TIM_OUTPUT(chan, out) ( DEF_CHAN_ ## chan ## _OUTPUT | out ) -#define DMA_NONE_CHANNEL NULL -#define DMA_NONE_STREAM NULL #define DMA_NONE_HANDLER 0 #define DEF_CHAN_CH1 TIM_Channel_1 diff --git a/src/main/target/MOTOLAB/target.c b/src/main/target/MOTOLAB/target.c index 4a9603edec..c9adecf16f 100644 --- a/src/main/target/MOTOLAB/target.c +++ b/src/main/target/MOTOLAB/target.c @@ -21,18 +21,19 @@ #include "drivers/io.h" #include "drivers/timer.h" +#include "drivers/timer_def.h" #include "drivers/dma.h" const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { - { TIM3, IO_TAG(PA4), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_2, NULL, 0 }, // PWM1 - PA4 - *TIM3_CH2 - { TIM3, IO_TAG(PA6), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_2, NULL, 0 }, // PWM2 - PA6 - *TIM3_CH1, TIM8_BKIN, TIM1_BKIN, TIM16_CH1 - { TIM3, IO_TAG(PB0), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_2, NULL, 0 }, // PWM3 - PB0 - *TIM3_CH3, TIM1_CH2N, TIM8_CH2N - { TIM3, IO_TAG(PB1), TIM_Channel_4, TIM_USE_MOTOR, 1, GPIO_AF_2, NULL, 0 }, // PWM4 - PB1 - *TIM3_CH4, TIM1_CH3N, TIM8_CH3N - { TIM2, IO_TAG(PA1), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_1, NULL, 0 }, // PWM5 - PA1 - *TIM2_CH2, TIM15_CH1N - { TIM2, IO_TAG(PA2), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_1, NULL, 0 }, // PWM6 - PA2 - *TIM2_CH3, !TIM15_CH1 - { TIM15, IO_TAG(PA3), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_9, NULL, 0 }, // PWM7 - PA3 - *TIM15_CH2, TIM2_CH4 - { TIM1, IO_TAG(PA8), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_6, NULL, 0 }, // PWM8 - PA8 - *TIM1_CH1, TIM4_ETR - { TIM17, IO_TAG(PA7), TIM_Channel_1, TIM_USE_PPM, 0, GPIO_AF_1, NULL, 0 }, // PPM - PA7 - *TIM17_CH1, TIM1_CH1N, TIM8_CH1 - { TIM16, IO_TAG(PB8), TIM_Channel_1, TIM_USE_LED, 0, GPIO_AF_1, DMA1_Channel3, DMA1_CH3_HANDLER }, // PPM - PA7 - *TIM17_CH1, TIM1_CH1N, TIM8_CH1 + DEF_TIM(TIM3, CH2, PA4, TIM_USE_MOTOR, 1 ), // PWM1 - PA4 - *TIM3_CH2 + DEF_TIM(TIM3, CH1, PA6, TIM_USE_MOTOR, 1 ), // PWM2 - PA6 - *TIM3_CH1, TIM8_BKIN, TIM1_BKIN, TIM16_CH1 + DEF_TIM(TIM3, CH3, PB0, TIM_USE_MOTOR, 1 ), // PWM3 - PB0 - *TIM3_CH3, TIM1_CH2N, TIM8_CH2N + DEF_TIM(TIM3, CH4, PB1, TIM_USE_MOTOR, 1 ), // PWM4 - PB1 - *TIM3_CH4, TIM1_CH3N, TIM8_CH3N + DEF_TIM(TIM2, CH2, PA1, TIM_USE_MOTOR, 1 ), // PWM5 - PA1 - *TIM2_CH2, TIM15_CH1N + DEF_TIM(TIM2, CH3, PA2, TIM_USE_MOTOR, 1 ), // PWM6 - PA2 - *TIM2_CH3, !TIM15_CH1 + DEF_TIM(TIM15, CH2, PA3, TIM_USE_MOTOR, 1 ), // PWM7 - PA3 - *TIM15_CH2, TIM2_CH4 + DEF_TIM(TIM1, CH1, PA8, TIM_USE_MOTOR, 1 ), // PWM8 - PA8 - *TIM1_CH1, TIM4_ETR + DEF_TIM(TIM17, CH1, PA7, TIM_USE_PPM, 0 ), // PPM - PA7 - *TIM17_CH1, TIM1_CH1N, TIM8_CH1 + DEF_TIM(TIM16, CH1, PB8, TIM_USE_LED, 0 ), // PPM - PA7 - *TIM17_CH1, TIM1_CH1N, TIM8_CH1 }; diff --git a/src/main/target/MOTOLAB/target.h b/src/main/target/MOTOLAB/target.h index a5429e9683..a2739251a7 100644 --- a/src/main/target/MOTOLAB/target.h +++ b/src/main/target/MOTOLAB/target.h @@ -102,6 +102,7 @@ #define RSSI_ADC_PIN PB2 #define LED_STRIP +#define USE_DSHOT #define SPEKTRUM_BIND // USART2, PB4 diff --git a/src/main/target/RMDO/target.c b/src/main/target/RMDO/target.c index ebaeeaf24a..6e71f3cd0d 100644 --- a/src/main/target/RMDO/target.c +++ b/src/main/target/RMDO/target.c @@ -21,24 +21,25 @@ #include "drivers/io.h" #include "drivers/timer.h" +#include "drivers/timer_def.h" #include "drivers/dma.h" const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { - { TIM2, IO_TAG(PA0), TIM_Channel_1, TIM_USE_PWM | TIM_USE_PPM, 0, GPIO_AF_1, NULL, 0}, // RC_CH1 - PA0 - *TIM2_CH1 - { TIM2, IO_TAG(PA1), TIM_Channel_2, TIM_USE_PWM, 0, GPIO_AF_1 , NULL, 0}, // RC_CH2 - PA1 - *TIM2_CH2, TIM15_CH1N - { TIM2, IO_TAG(PB11), TIM_Channel_4, TIM_USE_PWM, 0, GPIO_AF_1 , NULL, 0}, // RC_CH3 - PB11 - *TIM2_CH4, UART3_RX (AF7) - { TIM2, IO_TAG(PB10), TIM_Channel_3, TIM_USE_PWM, 0, GPIO_AF_1 , NULL, 0}, // RC_CH4 - PB10 - *TIM2_CH3, UART3_TX (AF7) - { TIM3, IO_TAG(PB4), TIM_Channel_1, TIM_USE_PWM, 0, GPIO_AF_2 , NULL, 0}, // RC_CH5 - PB4 - *TIM3_CH1 - { TIM3, IO_TAG(PB5), TIM_Channel_2, TIM_USE_PWM, 0, GPIO_AF_2 , NULL, 0}, // RC_CH6 - PB5 - *TIM3_CH2 - { TIM3, IO_TAG(PB0), TIM_Channel_3, TIM_USE_PWM, 0, GPIO_AF_2 , NULL, 0}, // RC_CH7 - PB0 - *TIM3_CH3, TIM1_CH2N, TIM8_CH2N - { TIM3, IO_TAG(PB1), TIM_Channel_4, TIM_USE_PWM, 0, GPIO_AF_2 , NULL, 0}, // RC_CH8 - PB1 - *TIM3_CH4, TIM1_CH3N, TIM8_CH3N - { TIM16, IO_TAG(PA6), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_1 , NULL, 0}, // PWM1 - PA6 - TIM3_CH1, TIM8_BKIN, TIM1_BKIN, *TIM16_CH1 - { TIM17, IO_TAG(PA7), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_1 , NULL, 0}, // PWM2 - PA7 - TIM3_CH2, *TIM17_CH1, TIM1_CH1N, TIM8_CH1 - { TIM4, IO_TAG(PA11), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_10, NULL, 0}, // PWM3 - PA11 - { TIM4, IO_TAG(PA12), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_10, NULL, 0}, // PWM4 - PA12 - { TIM4, IO_TAG(PB8), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_2 , NULL, 0}, // PWM5 - PB8 - { TIM4, IO_TAG(PB9), TIM_Channel_4, TIM_USE_MOTOR, 1, GPIO_AF_2 , NULL, 0}, // PWM6 - PB9 - { TIM15, IO_TAG(PA2), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_9 , NULL, 0}, // PWM7 - PA2 - { TIM15, IO_TAG(PA3), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_9 , NULL, 0}, // PWM8 - PA3 - { TIM1, IO_TAG(PA8), TIM_Channel_1, TIM_USE_MOTOR | TIM_USE_LED, 1, GPIO_AF_6, DMA1_Channel2, DMA1_CH2_HANDLER }, // GPIO_TIMER / LED_STRIP + DEF_TIM(TIM2, CH1, PA0, TIM_USE_PWM | TIM_USE_PPM, 0 ), // RC_CH1 - PA0 - *TIM2_CH1 + DEF_TIM(TIM2, CH2, PA1, TIM_USE_PWM, 0 ), // RC_CH2 - PA1 - *TIM2_CH2, TIM15_CH1N + DEF_TIM(TIM2, CH4, PB11, TIM_USE_PWM, 0 ), // RC_CH3 - PB11 - *TIM2_CH4, UART3_RX (AF7) + DEF_TIM(TIM2, CH3, PB10, TIM_USE_PWM, 0 ), // RC_CH4 - PB10 - *TIM2_CH3, UART3_TX (AF7) + DEF_TIM(TIM3, CH1, PB4, TIM_USE_PWM, 0 ), // RC_CH5 - PB4 - *TIM3_CH1 + DEF_TIM(TIM3, CH2, PB5, TIM_USE_PWM, 0 ), // RC_CH6 - PB5 - *TIM3_CH2 + DEF_TIM(TIM3, CH3, PB0, TIM_USE_PWM, 0 ), // RC_CH7 - PB0 - *TIM3_CH3, TIM1_CH2N, TIM8_CH2N + DEF_TIM(TIM3, CH4, PB1, TIM_USE_PWM, 0 ), // RC_CH8 - PB1 - *TIM3_CH4, TIM1_CH3N, TIM8_CH3N + DEF_TIM(TIM16, CH1, PA6, TIM_USE_MOTOR, 1 ), // PWM1 - PA6 - TIM3_CH1, TIM8_BKIN, TIM1_BKIN, *TIM16_CH1 + DEF_TIM(TIM17, CH1, PA7, TIM_USE_MOTOR, 1 ), // PWM2 - PA7 - TIM3_CH2, *TIM17_CH1, TIM1_CH1N, TIM8_CH1 + DEF_TIM(TIM4, CH1, PA11, TIM_USE_MOTOR, 1 ), // PWM3 - PA11 + DEF_TIM(TIM4, CH2, PA12, TIM_USE_MOTOR, 1 ), // PWM4 - PA12 + DEF_TIM(TIM4, CH3, PB8, TIM_USE_MOTOR, 1 ), // PWM5 - PB8 + DEF_TIM(TIM4, CH4, PB9, TIM_USE_MOTOR, 1 ), // PWM6 - PB9 + DEF_TIM(TIM15, CH1, PA2, TIM_USE_MOTOR, 1 ), // PWM7 - PA2 + DEF_TIM(TIM15, CH2, PA3, TIM_USE_MOTOR, 1 ), // PWM8 - PA3 + DEF_TIM(TIM1, CH1, PA8, TIM_USE_MOTOR | TIM_USE_LED, 1 ), // GPIO_TIMER / LED_STRIP }; diff --git a/src/main/target/RMDO/target.h b/src/main/target/RMDO/target.h index 69d3575f58..658f6528e9 100644 --- a/src/main/target/RMDO/target.h +++ b/src/main/target/RMDO/target.h @@ -95,6 +95,7 @@ #define RSSI_ADC_PIN PB2 #define LED_STRIP +#define USE_DSHOT #undef GPS diff --git a/src/main/target/SOULF4/target.c b/src/main/target/SOULF4/target.c index f1aeb50ff6..3428d2e6a4 100644 --- a/src/main/target/SOULF4/target.c +++ b/src/main/target/SOULF4/target.c @@ -20,19 +20,20 @@ #include #include "drivers/io.h" #include "drivers/timer.h" +#include "drivers/timer_def.h" #include "drivers/dma.h" const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { - { TIM12, IO_TAG(PB14), TIM_Channel_1, TIM_USE_PWM | TIM_USE_PPM, 0, GPIO_AF_TIM12, NULL, 0, 0 }, // PPM (5th pin on FlexiIO port) - { TIM12, IO_TAG(PB15), TIM_Channel_2, TIM_USE_PWM, 0, GPIO_AF_TIM12, NULL, 0, 0 }, // S2_IN - GPIO_PartialRemap_TIM3 - { TIM8, IO_TAG(PC6), TIM_Channel_1, TIM_USE_PWM, 0, GPIO_AF_TIM8 , NULL, 0, 0 }, // S3_IN - { TIM8, IO_TAG(PC7), TIM_Channel_2, TIM_USE_PWM, 0, GPIO_AF_TIM8 , NULL, 0, 0 }, // S4_IN - { TIM8, IO_TAG(PC8), TIM_Channel_3, TIM_USE_PWM, 0, GPIO_AF_TIM8 , NULL, 0, 0 }, // S5_IN - { TIM8, IO_TAG(PC9), TIM_Channel_4, TIM_USE_PWM, 0, GPIO_AF_TIM8 , NULL, 0, 0 }, // S6_IN - { TIM3, IO_TAG(PB0), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_TIM3 , NULL, 0, 0 }, // S1_OUT - { TIM3, IO_TAG(PB1), TIM_Channel_4, TIM_USE_MOTOR, 1, GPIO_AF_TIM3 , NULL, 0, 0 }, // S2_OUT - { TIM9, IO_TAG(PA3), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_TIM9 , NULL, 0, 0 }, // S3_OUT - { TIM2, IO_TAG(PA2), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_TIM2 , NULL, 0, 0 }, // S4_OUT - { TIM5, IO_TAG(PA1), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_TIM5, NULL, 0, 0 }, // S5_OUT - GPIO_PartialRemap_TIM3 - { TIM5, IO_TAG(PA0), TIM_Channel_1, TIM_USE_MOTOR | TIM_USE_LED, 1, GPIO_AF_TIM5 , DMA1_Stream2, DMA_Channel_6, DMA1_ST2_HANDLER }, // S6_OUT + DEF_TIM(TIM12, CH1, PB14, TIM_USE_PWM | TIM_USE_PPM, 0, 0 ), // PPM (5th pin on FlexiIO port) + DEF_TIM(TIM12, CH2, PB15, TIM_USE_PWM, 0, 0 ), // S2_IN - GPIO_PartialRemap_TIM3 + DEF_TIM(TIM8, CH1, PC6, TIM_USE_PWM, 0, 0 ), // S3_IN + DEF_TIM(TIM8, CH2, PC7, TIM_USE_PWM, 0, 0 ), // S4_IN + DEF_TIM(TIM8, CH3, PC8, TIM_USE_PWM, 0, 0 ), // S5_IN + DEF_TIM(TIM8, CH4, PC9, TIM_USE_PWM, 0, 0 ), // S6_IN + DEF_TIM(TIM3, CH3, PB0, TIM_USE_MOTOR, 1, 0 ), // S1_OUT + DEF_TIM(TIM3, CH4, PB1, TIM_USE_MOTOR, 1, 0 ), // S2_OUT + DEF_TIM(TIM2, CH4, PA3, TIM_USE_MOTOR, 1, 0 ), // S3_OUT + DEF_TIM(TIM2, CH3, PA2, TIM_USE_MOTOR, 1, 0 ), // S4_OUT + DEF_TIM(TIM5, CH2, PA1, TIM_USE_MOTOR, 1, 0 ), // S5_OUT - GPIO_PartialRemap_TIM3 + DEF_TIM(TIM5, CH1, PA0, TIM_USE_MOTOR | TIM_USE_LED, 1, 0 ), // S6_OUT }; diff --git a/src/main/target/SOULF4/target.h b/src/main/target/SOULF4/target.h index 84752a82ce..410841e747 100644 --- a/src/main/target/SOULF4/target.h +++ b/src/main/target/SOULF4/target.h @@ -104,6 +104,7 @@ #define SERIALRX_PROVIDER SERIALRX_SBUS #define LED_STRIP +#define USE_DSHOT #define SPEKTRUM_BIND // USART3, diff --git a/src/main/target/SPARKY2/target.c b/src/main/target/SPARKY2/target.c index 22a00fa936..1bf8f23511 100644 --- a/src/main/target/SPARKY2/target.c +++ b/src/main/target/SPARKY2/target.c @@ -21,18 +21,20 @@ #include "drivers/io.h" #include "drivers/timer.h" +#include "drivers/timer_def.h" +#include "drivers/dma.h" const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { - { TIM8, IO_TAG(PC7), TIM_Channel_2, TIM_USE_PWM | TIM_USE_PPM, 0, GPIO_AF_TIM8 }, // PPM IN - { TIM12, IO_TAG(PB14), TIM_Channel_1, TIM_USE_PWM, 0, GPIO_AF_TIM12 }, // S2_IN - { TIM12, IO_TAG(PB15), TIM_Channel_2, TIM_USE_PWM, 0, GPIO_AF_TIM12 }, // S3_IN - GPIO_PartialRemap_TIM3 - { TIM8, IO_TAG(PC8), TIM_Channel_3, TIM_USE_PWM, 0, GPIO_AF_TIM8 }, // S4_IN - { TIM8, IO_TAG(PC9), TIM_Channel_4, TIM_USE_PWM, 0, GPIO_AF_TIM8 }, // S5_IN - { TIM3, IO_TAG(PB0), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_TIM3 }, // S1_OUT - { TIM3, IO_TAG(PB1), TIM_Channel_4, TIM_USE_MOTOR, 1, GPIO_AF_TIM3 }, // S2_OUT - { TIM9, IO_TAG(PA3), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_TIM9 }, // S3_OUT - { TIM2, IO_TAG(PA2), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_TIM2 }, // S4_OUT - { TIM5, IO_TAG(PA1), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_TIM5 }, // S5_OUT - GPIO_PartialRemap_TIM3 - { TIM5, IO_TAG(PA0), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_TIM5 }, // S6_OUT + DEF_TIM(TIM8, CH2, PC7, TIM_USE_PWM | TIM_USE_PPM, 0, 0 ), // PPM IN + DEF_TIM(TIM12, CH1, PB14, TIM_USE_PWM, 0, 0 ), // S2_IN + DEF_TIM(TIM12, CH2, PB15, TIM_USE_PWM, 0, 0 ), // S3_IN - GPIO_PartialRemap_TIM3 + DEF_TIM(TIM8, CH3, PC8, TIM_USE_PWM, 0, 0 ), // S4_IN + DEF_TIM(TIM8, CH4, PC9, TIM_USE_PWM, 0, 0 ), // S5_IN + DEF_TIM(TIM3, CH3, PB0, TIM_USE_MOTOR, 1, 0 ), // S1_OUT + DEF_TIM(TIM3, CH4, PB1, TIM_USE_MOTOR, 1, 0 ), // S2_OUT + DEF_TIM(TIM2, CH4, PA3, TIM_USE_MOTOR, 1, 0 ), // S3_OUT + DEF_TIM(TIM2, CH3, PA2, TIM_USE_MOTOR, 1, 0 ), // S4_OUT + DEF_TIM(TIM5, CH2, PA1, TIM_USE_MOTOR, 1, 0 ), // S5_OUT - GPIO_PartialRemap_TIM3 + DEF_TIM(TIM5, CH1, PA0, TIM_USE_MOTOR, 1, 0 ), // S6_OUT }; diff --git a/src/main/target/SPARKY2/target.h b/src/main/target/SPARKY2/target.h index 48a01c39a4..69a120a06b 100644 --- a/src/main/target/SPARKY2/target.h +++ b/src/main/target/SPARKY2/target.h @@ -32,10 +32,11 @@ #define BEEPER PC9 #define BEEPER_INVERTED - #define INVERTER PC6 #define INVERTER_USART USART6 +#define USE_DSHOT + // MPU9250 interrupt #define USE_EXTI #define MPU_INT_EXTI PC5 From 4f84f907df1dff431a98cf4c95eec454ec5eb41d Mon Sep 17 00:00:00 2001 From: blckmn Date: Wed, 9 Nov 2016 17:34:37 +1100 Subject: [PATCH 5/6] Adding DSHOT to EVO - needs testing. --- src/main/target/SPRACINGF3EVO/target.c | 25 +++++++++++++------------ src/main/target/SPRACINGF3EVO/target.h | 1 + 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/main/target/SPRACINGF3EVO/target.c b/src/main/target/SPRACINGF3EVO/target.c index 247082280f..526fa029e9 100644 --- a/src/main/target/SPRACINGF3EVO/target.c +++ b/src/main/target/SPRACINGF3EVO/target.c @@ -21,20 +21,21 @@ #include "drivers/io.h" #include "drivers/timer.h" +#include "drivers/timer_def.h" #include "drivers/dma.h" const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { // PPM / UART2 RX - { TIM8, IO_TAG(PA15), TIM_Channel_1, TIM_USE_PPM, 0, GPIO_AF_2, NULL, 0 }, // PPM - { TIM2, IO_TAG(PA0), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_1, NULL, 0 }, // PWM1 - { TIM2, IO_TAG(PA1), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_1, NULL, 0 }, // PWM2 - { TIM15, IO_TAG(PA2), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_9, NULL, 0 }, // PWM3 - { TIM15, IO_TAG(PA3), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_9, NULL, 0 }, // PWM4 - { TIM3, IO_TAG(PA6), TIM_Channel_1, TIM_USE_MOTOR, 1, GPIO_AF_2, NULL, 0 }, // PWM5 - { TIM3, IO_TAG(PA7), TIM_Channel_2, TIM_USE_MOTOR, 1, GPIO_AF_2, NULL, 0 }, // PWM6 - { TIM3, IO_TAG(PB0), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_2, NULL, 0 }, // PWM7 - { TIM3, IO_TAG(PB1), TIM_Channel_4, TIM_USE_MOTOR, 1, GPIO_AF_2, NULL, 0 }, // PWM8 - { TIM2, IO_TAG(PB10), TIM_Channel_3, TIM_USE_MOTOR, 1, GPIO_AF_1, NULL, 0 }, // RC_CH4 - PB10 - *TIM2_CH3, UART3_TX (AF7) - { TIM2, IO_TAG(PB11), TIM_Channel_4, TIM_USE_MOTOR, 1, GPIO_AF_1, NULL, 0 }, // RC_CH3 - PB11 - *TIM2_CH4, UART3_RX (AF7) - { TIM1, IO_TAG(PA8), TIM_Channel_1, TIM_USE_LED, 1, GPIO_AF_6, DMA1_Channel2, DMA1_CH2_HANDLER }, // GPIO_TIMER / LED_STRIP + DEF_TIM(TIM8, CH1, PA15, TIM_USE_PPM, 0 ), // PPM + DEF_TIM(TIM2, CH1, PA0, TIM_USE_MOTOR, 1 ), // PWM1 + DEF_TIM(TIM2, CH2, PA1, TIM_USE_MOTOR, 1 ), // PWM2 + DEF_TIM(TIM15, CH1, PA2, TIM_USE_MOTOR, 1 ), // PWM3 + DEF_TIM(TIM15, CH2, PA3, TIM_USE_MOTOR, 1 ), // PWM4 + DEF_TIM(TIM3, CH1, PA6, TIM_USE_MOTOR, 1 ), // PWM5 + DEF_TIM(TIM3, CH2, PA7, TIM_USE_MOTOR, 1 ), // PWM6 + DEF_TIM(TIM3, CH3, PB0, TIM_USE_MOTOR, 1 ), // PWM7 + DEF_TIM(TIM3, CH4, PB1, TIM_USE_MOTOR, 1 ), // PWM8 + DEF_TIM(TIM2, CH3, PB10, TIM_USE_MOTOR, 1 ), // RC_CH4 - PB10 - *TIM2_CH3, UART3_TX (AF7) + DEF_TIM(TIM2, CH4, PB11, TIM_USE_MOTOR, 1 ), // RC_CH3 - PB11 - *TIM2_CH4, UART3_RX (AF7) + DEF_TIM(TIM1, CH1, PA8, TIM_USE_LED, 1 ), // GPIO_TIMER / LED_STRIP }; diff --git a/src/main/target/SPRACINGF3EVO/target.h b/src/main/target/SPRACINGF3EVO/target.h index 280af8c8a5..516d023dba 100755 --- a/src/main/target/SPRACINGF3EVO/target.h +++ b/src/main/target/SPRACINGF3EVO/target.h @@ -35,6 +35,7 @@ #define USE_MAG_DATA_READY_SIGNAL #define ENSURE_MAG_DATA_READY_IS_HIGH +#define USE_DSHOT #define GYRO #define USE_GYRO_SPI_MPU6500 From 9df456cbd79dd2f29382a4103fb57a7ea0a16c09 Mon Sep 17 00:00:00 2001 From: blckmn Date: Wed, 9 Nov 2016 17:40:01 +1100 Subject: [PATCH 6/6] Using defines from @boris.b. for remapping F3 T16 and 17 --- src/main/drivers/timer_def.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/drivers/timer_def.h b/src/main/drivers/timer_def.h index 1ddf0bc771..bfc1f1c7ed 100644 --- a/src/main/drivers/timer_def.h +++ b/src/main/drivers/timer_def.h @@ -70,7 +70,7 @@ #define DEF_TIM_DMA__TIM15_TRIG DMA1_CH5 #define DEF_TIM_DMA__TIM15_COM DMA1_CH5 -#ifdef DMA_TIMER16_REMAP +#ifdef REMAP_TIM16_DMA #define DEF_TIM_DMA__TIM16_CH1 DMA1_CH6 #define DEF_TIM_DMA__TIM16_UP DMA1_CH6 #else @@ -78,7 +78,7 @@ #define DEF_TIM_DMA__TIM16_UP DMA1_CH3 #endif -#ifdef DMA_TIMER17_REMAP +#ifdef REMAP_TIM17_DMA #define DEF_TIM_DMA__TIM17_CH1 DMA1_CH7 #define DEF_TIM_DMA__TIM17_UP DMA1_CH7 #else