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Merge pull request #1415 from blckmn/development

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This commit is contained in:
J Blackman 2016-10-27 19:13:30 +11:00 • committed by GitHub
commit 42cd8da0e6
2 changed files with 28 additions and 161 deletions
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2
src/main/config/config_eeprom.c
View file

@ -76,7 +76,7 @@
#if defined(STM32F40_41xxx) #if defined(STM32F40_41xxx)
#define FLASH_PAGE_COUNT 4 // just to make calculations work #define FLASH_PAGE_COUNT 4 // just to make calculations work
#elif defined (STM32F411xE) #elif defined (STM32F411xE)
#define FLASH_PAGE_COUNT 4 // just to make calculations work #define FLASH_PAGE_COUNT 3 // just to make calculations work
#elif defined (STM32F745xx) #elif defined (STM32F745xx)
#define FLASH_PAGE_COUNT 4 // just to make calculations work #define FLASH_PAGE_COUNT 4 // just to make calculations work
#else #else

187
src/main/target/system_stm32f4xx.c
View file

@ -346,21 +346,6 @@ uint32_t hse_value = HSE_VALUE;
/* #define DATA_IN_ExtSDRAM */ /* #define DATA_IN_ExtSDRAM */
#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
#if defined(STM32F410xx) || defined(STM32F411xE)
/*!< Uncomment the following line if you need to clock the STM32F410xx/STM32F411xE by HSE Bypass
through STLINK MCO pin of STM32F103 microcontroller. The frequency cannot be changed
and is fixed at 8 MHz.
Hardware configuration needed for Nucleo Board:
– SB54, SB55 OFF
– R35 removed
– SB16, SB50 ON */
/* #define USE_HSE_BYPASS */
#if defined(USE_HSE_BYPASS)
#define HSE_BYPASS_INPUT_FREQUENCY 8000000
#endif /* USE_HSE_BYPASS */
#endif /* STM32F410xx || STM32F411xE */
/*!< Uncomment the following line if you need to relocate your vector Table in /*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */ Internal SRAM. */
/* #define VECT_TAB_SRAM */ /* #define VECT_TAB_SRAM */
@ -379,17 +364,10 @@ uint32_t hse_value = HSE_VALUE;
#elif defined (STM32F446xx) #elif defined (STM32F446xx)
#define PLL_M 8 #define PLL_M 8
#elif defined (STM32F410xx) || defined (STM32F411xE) #elif defined (STM32F410xx) || defined (STM32F411xE)
#if defined(USE_HSE_BYPASS) #define PLL_M 8
#define PLL_M 8
#else /* !USE_HSE_BYPASS */
#define PLL_M 8
#endif /* USE_HSE_BYPASS */
#else #else
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */ #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
#if defined(STM32F446xx) #if defined(STM32F446xx)
/* PLL division factor for I2S, SAI, SYSTEM and SPDIF: Clock = PLL_VCO / PLLR */ /* PLL division factor for I2S, SAI, SYSTEM and SPDIF: Clock = PLL_VCO / PLLR */
#define PLL_R 7 #define PLL_R 7
@ -399,24 +377,32 @@ uint32_t hse_value = HSE_VALUE;
#define PLL_N 360 #define PLL_N 360
/* SYSCLK = PLL_VCO / PLL_P */ /* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2 #define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
#if defined (STM32F40_41xxx) #if defined (STM32F40_41xxx)
#define PLL_N 336 #define PLL_N 336
/* SYSCLK = PLL_VCO / PLL_P */ /* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2 #define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
#endif /* STM32F40_41xxx */ #endif /* STM32F40_41xxx */
#if defined(STM32F401xx) #if defined(STM32F401xx)
#define PLL_N 336 #define PLL_N 336
/* SYSCLK = PLL_VCO / PLL_P */ /* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 4 #define PLL_P 4
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
#endif /* STM32F401xx */ #endif /* STM32F401xx */
#if defined(STM32F410xx) || defined(STM32F411xE) #if defined(STM32F410xx) || defined(STM32F411xE)
#define PLL_N 400 #define PLL_N 384
/* SYSCLK = PLL_VCO / PLL_P */ /* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 4 #define PLL_P 4
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 8
#endif /* STM32F410xx || STM32F411xE */ #endif /* STM32F410xx || STM32F411xE */
/******************************************************************************/ /******************************************************************************/
@ -450,7 +436,7 @@ uint32_t hse_value = HSE_VALUE;
#endif /* STM32F401xx */ #endif /* STM32F401xx */
#if defined(STM32F410xx) || defined(STM32F411xE) #if defined(STM32F410xx) || defined(STM32F411xE)
uint32_t SystemCoreClock = 100000000; uint32_t SystemCoreClock = 96000000;
#endif /* STM32F410xx || STM32F401xE */ #endif /* STM32F410xx || STM32F401xE */
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
@ -585,7 +571,6 @@ void SystemCoreClockUpdate(void)
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
if (pllsource != 0) if (pllsource != 0)
{ {
/* HSE used as PLL clock source */ /* HSE used as PLL clock source */
@ -596,21 +581,7 @@ void SystemCoreClockUpdate(void)
/* HSI used as PLL clock source */ /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
} }
#elif defined(STM32F410xx) || defined(STM32F411xE)
#if defined(USE_HSE_BYPASS)
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
#else
if (pllsource == 0)
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
#endif /* USE_HSE_BYPASS */
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F446xx || STM32F469_479xx */
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp; SystemCoreClock = pllvco/pllp;
break; break;
@ -657,7 +628,6 @@ void SystemCoreClockUpdate(void)
*/ */
void SetSysClock(void) void SetSysClock(void)
{ {
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx)|| defined(STM32F469_479xx)
/******************************************************************************/ /******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */ /* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/ /******************************************************************************/
@ -707,16 +677,22 @@ void SetSysClock(void)
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
#endif /* STM32F401xx */ #endif /* STM32F401xx */
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx) #if defined(STM32F410xx) || defined(STM32F411xE)
/* Configure the main PLL */ /* PCLK2 = HCLK / 2*/
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
#endif /* STM32F40_41xxx || STM32F401xx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */ /* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
#endif /* STM32F410xx || STM32F411xE */
#if defined(STM32F446xx) #if defined(STM32F446xx)
/* Configure the main PLL */ /* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28); (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28);
#else
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
#endif /* STM32F446xx */ #endif /* STM32F446xx */
/* Enable the main PLL */ /* Enable the main PLL */
@ -737,19 +713,17 @@ void SetSysClock(void)
while((PWR->CSR & PWR_CSR_ODSWRDY) == 0) while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
{ {
} }
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
#if defined(STM32F40_41xxx) #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
#endif /* STM32F40_41xxx */ #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
#if defined(STM32F401xx) #if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE)
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS; FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
#endif /* STM32F401xx */ #endif /* STM32F401xx || STM32F410xx || STM32F411xE*/
/* Select the main PLL as system clock source */ /* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
@ -764,113 +738,6 @@ void SetSysClock(void)
{ /* If HSE fails to start-up, the application will have wrong clock { /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */ configuration. User can add here some code to deal with this error */
} }
#elif defined(STM32F410xx) || defined(STM32F411xE)
#if defined(USE_HSE_BYPASS)
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Enable HSE and HSE BYPASS */
RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Select regulator voltage output Scale 1 mode */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
#else /* HSI will be used as PLL clock source */
/* Select regulator voltage output Scale 1 mode */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
#endif /* USE_HSE_BYPASS */
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */
} }
/** /**