diff --git a/lib/main/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/lib/main/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c index b2ca5f1648..d9befc711c 100644 --- a/lib/main/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ b/lib/main/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -475,6 +475,7 @@ __ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIG static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, uint8_t cfgidx) { + (void)cfgidx; uint8_t ret = 0; USBD_CDC_HandleTypeDef *hcdc; @@ -563,6 +564,7 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, uint8_t cfgidx) { + (void)cfgidx; uint8_t ret = 0; /* Open EP IN */ @@ -663,6 +665,7 @@ static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, */ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) { + (void)epnum; USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; if(pdev->pClassData != NULL) diff --git a/lib/main/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/lib/main/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c index 0158829c52..7ebb1873a1 100644 --- a/lib/main/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c +++ b/lib/main/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c @@ -212,6 +212,7 @@ USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev) */ USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev) { + (void)pdev; return USBD_OK; } @@ -508,6 +509,8 @@ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { + (void)pdev; + (void)epnum; return USBD_OK; } @@ -519,6 +522,8 @@ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t ep */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { + (void)pdev; + (void)epnum; return USBD_OK; } @@ -530,6 +535,7 @@ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t e */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { + (void)pdev; return USBD_OK; } diff --git a/lib/main/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/lib/main/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c index 49330c667b..0f38e9af3e 100644 --- a/lib/main/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c +++ b/lib/main/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c @@ -716,6 +716,7 @@ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) void USBD_CtlError( USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) { + (void)req; USBD_LL_StallEP(pdev , 0x80); USBD_LL_StallEP(pdev , 0); } diff --git a/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c b/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c index 4cb8ca8c5d..64416398e0 100644 --- a/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c +++ b/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c @@ -756,6 +756,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) */ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) { + (void)hadc; /* Return the multi mode conversion value */ return ADC->CDR; } diff --git a/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c b/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c index f761655d00..1e164b883a 100644 --- a/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c +++ b/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c @@ -2845,6 +2845,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { + (void)DevAddress; if(hi2c->Mode == HAL_I2C_MODE_MASTER) { /* Process Locked */ @@ -3684,6 +3685,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { + (void)ITFlags; uint8_t transferdirection = 0; uint16_t slaveaddrcode = 0; uint16_t ownadd1code = 0; @@ -4254,6 +4256,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) /* No specific action, Master fully manage the generation of STOP condition */ /* Mean that this generation can arrive at any time, at the end or during DMA process */ /* So STOP condition should be manage through Interrupt treatment */ + (void)hdma; } /** @@ -4308,6 +4311,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) /* No specific action, Master fully manage the generation of STOP condition */ /* Mean that this generation can arrive at any time, at the end or during DMA process */ /* So STOP condition should be manage through Interrupt treatment */ + (void)hdma; } /** diff --git a/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c b/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c index 9d59c0124f..6811622868 100644 --- a/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c +++ b/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c @@ -404,6 +404,7 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { + (void)Regulator; /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); diff --git a/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c b/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c index 4776fb4e34..de97e1feb3 100644 --- a/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c +++ b/lib/main/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c @@ -2118,7 +2118,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ - + (void)OutputChannel; TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); @@ -2150,6 +2150,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + (void)OutputChannel; TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2187,6 +2188,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ + (void)OutputChannel; /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -2218,6 +2220,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + (void)OutputChannel; /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);