Mirror/betaflight
1
0
Fork 0
mirror of https://github.com/betaflight/betaflight.git synced 2025-07-23 16:25:31 +03:00
Code Issues Wiki Activity

Add fullTimerHardware for F3 for use with USE_TIMER_MGMT.

Browse source 
STM32F3 doesn't have TIM5.
This commit is contained in:
Dominic Clifton 2019-08-27 01:16:59 +02:00
parent 2b1d256396
commit 4eb839c7bf
2 changed files with 125 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

119
src/main/drivers/timer_stm32f30x.c
View file

@ -47,3 +47,122 @@ uint32_t timerClock(TIM_TypeDef *tim)
return SystemCoreClock;
}
#endif
#if defined(USE_TIMER_MGMT)
const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
// Auto-generated from 'timer_def.h'
// Search: \#define DEF_TIM_AF__(.*)__TCH_(.*)_([^ ]*).*
// Replace: DEF_TIM($2, $3, $1, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH1, PA0, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH2, PA1, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH3, PA2, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH4, PA3, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH1, PA5, TIM_USE_ANY, 0),
DEF_TIM(TIM16, CH1, PA6, TIM_USE_ANY, 0),
DEF_TIM(TIM17, CH1, PA7, TIM_USE_ANY, 0),
DEF_TIM(TIM16, CH1, PA12, TIM_USE_ANY, 0),
DEF_TIM(TIM16, CH1N, PA13, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH1, PA15, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH2, PA4, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH1, PA6, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH2, PA7, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH1, PA15, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH1N, PA7, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH2, PA14, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH1N, PA7, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH1, PA8, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH2, PA9, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH3, PA10, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH1N, PA11, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH2N, PA12, TIM_USE_ANY, 0),
DEF_TIM(TIM15, CH1N, PA1, TIM_USE_ANY, 0),
DEF_TIM(TIM15, CH1, PA2, TIM_USE_ANY, 0),
DEF_TIM(TIM15, CH2, PA3, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH3, PA9, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH4, PA10, TIM_USE_ANY, 0),
DEF_TIM(TIM4, CH1, PA11, TIM_USE_ANY, 0),
DEF_TIM(TIM4, CH2, PA12, TIM_USE_ANY, 0),
DEF_TIM(TIM4, CH3, PA13, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH4, PA11, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH2, PB3, TIM_USE_ANY, 0),
DEF_TIM(TIM16, CH1, PB4, TIM_USE_ANY, 0),
DEF_TIM(TIM16, CH1N, PB6, TIM_USE_ANY, 0),
DEF_TIM(TIM17, CH1N, PB7, TIM_USE_ANY, 0),
DEF_TIM(TIM16, CH1, PB8, TIM_USE_ANY, 0),
DEF_TIM(TIM17, CH1, PB9, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0),
DEF_TIM(TIM15, CH1, PB14, TIM_USE_ANY, 0),
DEF_TIM(TIM15, CH2, PB15, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH3, PB0, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH4, PB1, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH1, PB4, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH2, PB5, TIM_USE_ANY, 0),
DEF_TIM(TIM4, CH1, PB6, TIM_USE_ANY, 0),
DEF_TIM(TIM4, CH2, PB7, TIM_USE_ANY, 0),
DEF_TIM(TIM4, CH3, PB8, TIM_USE_ANY, 0),
DEF_TIM(TIM4, CH4, PB9, TIM_USE_ANY, 0),
DEF_TIM(TIM15, CH1N, PB15, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH3N, PB5, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH2N, PB0, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH3N, PB1, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH1N, PB3, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH2N, PB4, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH3N, PB15, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH1, PB6, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH2N, PB0, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH3N, PB1, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH1N, PB13, TIM_USE_ANY, 0),
DEF_TIM(TIM1, CH2N, PB14, TIM_USE_ANY, 0),
DEF_TIM(TIM17, CH1, PB5, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH4, PB7, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH2, PB8, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH3, PB9, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH1, PC6, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH2, PC7, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH3, PC8, TIM_USE_ANY, 0),
DEF_TIM(TIM3, CH4, PC9, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH1, PC6, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH2, PC7, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH3, PC8, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH4, PC9, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH1N, PC10, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH2N, PC11, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH3N, PC12, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH1N, PC13, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH1, PD3, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH2, PD4, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH4, PD6, TIM_USE_ANY, 0),
DEF_TIM(TIM2, CH3, PD7, TIM_USE_ANY, 0),
DEF_TIM(TIM4, CH1, PD12, TIM_USE_ANY, 0),
DEF_TIM(TIM4, CH2, PD13, TIM_USE_ANY, 0),
DEF_TIM(TIM4, CH3, PD14, TIM_USE_ANY, 0),
DEF_TIM(TIM4, CH4, PD15, TIM_USE_ANY, 0),
DEF_TIM(TIM8, CH4, PD1, TIM_USE_ANY, 0),
DEF_TIM(TIM15, CH1, PF9, TIM_USE_ANY, 0),
DEF_TIM(TIM15, CH2, PF10, TIM_USE_ANY, 0),
};
#endif