From f598145b48644b0dd36ed8a15db1903b33a1119e Mon Sep 17 00:00:00 2001 From: atomiclama Date: Tue, 12 Sep 2017 13:33:46 +0100 Subject: [PATCH] Initialise rtc6705 CS to high. Currently the pin initialisation sets it low, this allows any initialisation glitches on the DATA and CLK lines to possibly be detected. This PR changes the order and forces the CS high before any changes to the DATA and CLK lines. I know there is information out there that the rtc6705 ignores the CS but as we are using it lets do it properly. --- src/main/drivers/vtx_rtc6705_soft_spi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/drivers/vtx_rtc6705_soft_spi.c b/src/main/drivers/vtx_rtc6705_soft_spi.c index 2bffc9f6cc..bc66ae2001 100644 --- a/src/main/drivers/vtx_rtc6705_soft_spi.c +++ b/src/main/drivers/vtx_rtc6705_soft_spi.c @@ -65,11 +65,12 @@ void rtc6705IOInit(void) rtc6705LePin = IOGetByTag(IO_TAG(RTC6705_SPILE_PIN)); rtc6705ClkPin = IOGetByTag(IO_TAG(RTC6705_SPICLK_PIN)); - IOInit(rtc6705DataPin, OWNER_SPI_MOSI, RESOURCE_SOFT_OFFSET); - IOConfigGPIO(rtc6705DataPin, IOCFG_OUT_PP); - IOInit(rtc6705LePin, OWNER_SPI_CS, RESOURCE_SOFT_OFFSET); IOConfigGPIO(rtc6705LePin, IOCFG_OUT_PP); + RTC6705_SPILE_ON; + + IOInit(rtc6705DataPin, OWNER_SPI_MOSI, RESOURCE_SOFT_OFFSET); + IOConfigGPIO(rtc6705DataPin, IOCFG_OUT_PP); IOInit(rtc6705ClkPin, OWNER_SPI_SCK, RESOURCE_SOFT_OFFSET); IOConfigGPIO(rtc6705ClkPin, IOCFG_OUT_PP);