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a couple optimizations for dynamic HSE frequency - moved SetSysClock() to run after reset vector + bss init, and changed rcc which used hardcoded HSE_VALUE.
turn off leds/beeper before initializing pins to prevent flash at startup uninitialized errorAngle fix in new PID git-svn-id: https://afrodevices.googlecode.com/svn/trunk/baseflight@362 7c89a4a9-59b9-e629-4cfe-3a2d53b20e61
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3afeb3d1c8
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11 changed files with 3091 additions and 3036 deletions
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@ -6,7 +6,7 @@ uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Cor
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__I uint8_t AHBPrescTable[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 };
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static int SetSysClock(void);
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uint32_t hse_value = 8000000;
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void SystemInit(void)
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{
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@ -29,10 +29,6 @@ void SystemInit(void)
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x009F0000;
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/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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/* Configure the Flash Latency cycles and enable prefetch buffer */
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SetSysClock();
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SCB->VTOR = FLASH_BASE; /* Vector Table Relocation in Internal FLASH. */
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}
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@ -48,7 +44,7 @@ void SystemCoreClockUpdate(void)
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE used as system clock */
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SystemCoreClock = HSE_VALUE;
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SystemCoreClock = hse_value;
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break;
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case 0x08: /* PLL used as system clock */
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@ -64,9 +60,9 @@ void SystemCoreClockUpdate(void)
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} else {
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/* HSE selected as PLL clock entry */
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if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t) RESET) { /* HSE oscillator clock divided by 2 */
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SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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SystemCoreClock = (hse_value >> 1) * pllmull;
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} else {
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SystemCoreClock = HSE_VALUE * pllmull;
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SystemCoreClock = hse_value * pllmull;
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}
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}
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break;
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@ -90,7 +86,7 @@ enum {
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};
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// Set system clock to 72 (HSE) or 64 (HSI) MHz
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static int SetSysClock(void)
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void SetSysClock(void)
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{
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__IO uint32_t StartUpCounter = 0, status = 0, clocksrc = SRC_NONE;
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__IO uint32_t *RCC_CRH = &GPIOC->CRH;
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@ -140,10 +136,11 @@ static int SetSysClock(void)
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*RCC_CRH &= (uint32_t)~((uint32_t)0xF << (RCC_CFGR_PLLMULL9 >> 16));
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// Configure PLL
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hse_value = 8000000;
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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*RCC_CRH |= (uint32_t)0x8 << (RCC_CFGR_PLLMULL9 >> 16);
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GPIOC->ODR &= (uint32_t)~(CAN_MCR_RESET);
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RCC_CFGR_PLLMUL = GPIOC->IDR & CAN_MCR_RESET ? StartUpCounter = 42, RCC_CFGR_PLLMULL6 : RCC_CFGR_PLLMULL9;
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RCC_CFGR_PLLMUL = GPIOC->IDR & CAN_MCR_RESET ? hse_value = 12000000, RCC_CFGR_PLLMULL6 : RCC_CFGR_PLLMULL9;
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switch (clocksrc) {
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case SRC_HSE:
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// PLL configuration: PLLCLK = HSE * 9 = 72 MHz
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@ -164,5 +161,6 @@ static int SetSysClock(void)
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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// Wait till PLL is used as system clock source
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08);
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return StartUpCounter;
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SystemCoreClockUpdate();
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}
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