Mirror/betaflight
1
0
Fork 0
mirror of https://github.com/betaflight/betaflight.git synced 2025-07-20 14:55:21 +03:00
Code Issues Wiki Activity

a couple optimizations for dynamic HSE frequency - moved SetSysClock() to run after reset vector + bss init, and changed rcc which used hardcoded HSE_VALUE.

Browse source 
turn off leds/beeper before initializing pins to prevent flash at startup
uninitialized errorAngle fix in new PID


git-svn-id: https://afrodevices.googlecode.com/svn/trunk/baseflight@362 7c89a4a9-59b9-e629-4cfe-3a2d53b20e61
This commit is contained in:
timecop@gmail.com 2013-07-02 00:58:50 +00:00
parent 3afeb3d1c8
commit 57cbd784a9
11 changed files with 3091 additions and 3036 deletions
Download patch file Download diff file Expand all files Collapse all files

13
lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
View file

@ -192,6 +192,7 @@
static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
extern uint32_t hse_value;
/**
* @}
@ -926,7 +927,7 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock */
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
RCC_Clocks->SYSCLK_Frequency = hse_value;
break;
case 0x08: /* PLL used as system clock */
@ -951,11 +952,11 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
/* HSE selected as PLL clock entry */
if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
{/* HSE oscillator clock divided by 2 */
RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
RCC_Clocks->SYSCLK_Frequency = (hse_value >> 1) * pllmull;
}
else
{
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
RCC_Clocks->SYSCLK_Frequency = hse_value * pllmull;
}
#endif
}
@ -973,7 +974,7 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
if (pllsource == 0x00)
{/* HSI oscillator clock divided by 2 selected as PLL clock entry */
RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
RCC_Clocks->SYSCLK_Frequency = (hse_value >> 1) * pllmull;
}
else
{/* PREDIV1 selected as PLL clock entry */
@ -984,7 +985,7 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
if (prediv1source == 0)
{ /* HSE oscillator clock selected as PREDIV1 clock entry */
RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
RCC_Clocks->SYSCLK_Frequency = (hse_value / prediv1factor) * pllmull;
}
else
{/* PLL2 clock selected as PREDIV1 clock entry */
@ -992,7 +993,7 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
/* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
RCC_Clocks->SYSCLK_Frequency = (((hse_value / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
}
}
#endif /* STM32F10X_CL */