diff --git a/make/mcu/STM32F7.mk b/make/mcu/STM32F7.mk index 9bcb643a92..0cb1eb3fde 100644 --- a/make/mcu/STM32F7.mk +++ b/make/mcu/STM32F7.mk @@ -127,7 +127,12 @@ endif ARCH_FLAGS = -mthumb -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-sp-d16 -fsingle-precision-constant -Wdouble-promotion DEVICE_FLAGS = -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -ifeq ($(TARGET),$(filter $(TARGET),$(F7X5XG_TARGETS))) +ifeq ($(TARGET),$(filter $(TARGET),$(F7X5XI_TARGETS))) +DEVICE_FLAGS += -DSTM32F765xx +LD_SCRIPT = $(LINKER_DIR)/stm32_flash_f765.ld +STARTUP_SRC = startup_stm32f765xx.s +TARGET_FLASH = 2048 +else ifeq ($(TARGET),$(filter $(TARGET),$(F7X5XG_TARGETS))) DEVICE_FLAGS += -DSTM32F745xx LD_SCRIPT = $(LINKER_DIR)/stm32_flash_f74x.ld STARTUP_SRC = startup_stm32f745xx.s diff --git a/src/main/config/config_streamer.c b/src/main/config/config_streamer.c index 3ed646504f..a47f1d4f9b 100644 --- a/src/main/config/config_streamer.c +++ b/src/main/config/config_streamer.c @@ -31,6 +31,7 @@ extern uint8_t __config_start; // configured via linker script when building b extern uint8_t __config_end; #endif +// @todo this is not strictly correct for F4/F7, where sector sizes are variable #if !defined(FLASH_PAGE_SIZE) // F1 # if defined(STM32F10X_MD) @@ -56,6 +57,8 @@ extern uint8_t __config_end; # define FLASH_PAGE_SIZE ((uint32_t)0x8000) // 32K sectors # elif defined(STM32F746xx) # define FLASH_PAGE_SIZE ((uint32_t)0x8000) +# elif defined(STM32F765xx) +# define FLASH_PAGE_SIZE ((uint32_t)0x8000) # elif defined(UNIT_TEST) # define FLASH_PAGE_SIZE (0x400) // SIMULATOR @@ -101,7 +104,7 @@ void config_streamer_start(config_streamer_t *c, uintptr_t base, int size) c->err = 0; } -#if defined(STM32F745xx) || defined(STM32F746xx) +#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F765xx) /* Sector 0 0x08000000 - 0x08007FFF 32 Kbytes Sector 1 0x08008000 - 0x0800FFFF 32 Kbytes @@ -111,6 +114,12 @@ Sector 4 0x08020000 - 0x0803FFFF 128 Kbytes Sector 5 0x08040000 - 0x0807FFFF 256 Kbytes Sector 6 0x08080000 - 0x080BFFFF 256 Kbytes Sector 7 0x080C0000 - 0x080FFFFF 256 Kbytes + +F7X5XI device with 2M flash +Sector 8 0x08100000 - 0x0813FFFF 256 Kbytes +Sector 9 0x08140000 - 0x0817FFFF 256 Kbytes +Sector 10 0x08180000 - 0x081BFFFF 256 Kbytes +Sector 11 0x081C0000 - 0x081FFFFF 256 Kbytes */ static uint32_t getFLASHSectorForEEPROM(void) @@ -131,6 +140,16 @@ static uint32_t getFLASHSectorForEEPROM(void) return FLASH_SECTOR_6; if ((uint32_t)&__config_start <= 0x080FFFFF) return FLASH_SECTOR_7; +#if defined(STM32F765xx) + if ((uint32_t)&__config_start <= 0x0813FFFF) + return FLASH_SECTOR_8; + if ((uint32_t)&__config_start <= 0x0817FFFF) + return FLASH_SECTOR_9; + if ((uint32_t)&__config_start <= 0x081BFFFF) + return FLASH_SECTOR_10; + if ((uint32_t)&__config_start <= 0x081FFFFF) + return FLASH_SECTOR_11; +#endif // Not good while (1) { diff --git a/src/main/drivers/adc_stm32f7xx.c b/src/main/drivers/adc_stm32f7xx.c index 7ce1a08597..83dc3e573d 100644 --- a/src/main/drivers/adc_stm32f7xx.c +++ b/src/main/drivers/adc_stm32f7xx.c @@ -58,9 +58,8 @@ #define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ // These addresses are incorrectly defined in stm32f7xx_ll_adc.h - -#if defined(STM32F745xx) || defined(STM32F746xx) -// F745xx_F746xx +#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F765xx) +// F745xx_F746xx and F765xx_F767xx_F769xx #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF0F44A)) #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF0F44C)) #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF0F44E)) diff --git a/src/main/drivers/serial_uart_impl.h b/src/main/drivers/serial_uart_impl.h index ef8a50c6b9..96602cbcd2 100644 --- a/src/main/drivers/serial_uart_impl.h +++ b/src/main/drivers/serial_uart_impl.h @@ -51,7 +51,7 @@ #endif #elif defined(STM32F7) #define UARTDEV_COUNT_MAX 8 -#define UARTHARDWARE_MAX_PINS 3 +#define UARTHARDWARE_MAX_PINS 4 #ifndef UART_RX_BUFFER_SIZE #define UART_RX_BUFFER_SIZE 128 #endif @@ -114,6 +114,13 @@ #define UARTDEV_COUNT (UARTDEV_COUNT_1 + UARTDEV_COUNT_2 + UARTDEV_COUNT_3 + UARTDEV_COUNT_4 + UARTDEV_COUNT_5 + UARTDEV_COUNT_6 + UARTDEV_COUNT_7 + UARTDEV_COUNT_8) +typedef struct uartPinDef_s { + ioTag_t pin; +#if defined(STM32F7) + uint8_t af; +#endif +} uartPinDef_t; + typedef struct uartHardware_s { UARTDevice_e device; // XXX Not required for full allocation USART_TypeDef* reg; @@ -125,8 +132,8 @@ typedef struct uartHardware_s { DMA_Stream_TypeDef *txDMAStream; DMA_Stream_TypeDef *rxDMAStream; #endif - ioTag_t rxPins[UARTHARDWARE_MAX_PINS]; - ioTag_t txPins[UARTHARDWARE_MAX_PINS]; + uartPinDef_t rxPins[UARTHARDWARE_MAX_PINS]; + uartPinDef_t txPins[UARTHARDWARE_MAX_PINS]; #if defined(STM32F7) uint32_t rcc_ahb1; rccPeriphTag_t rcc_apb2; @@ -134,7 +141,9 @@ typedef struct uartHardware_s { #else rccPeriphTag_t rcc; #endif +#if !defined(STM32F7) uint8_t af; +#endif #if defined(STM32F7) uint8_t txIrq; uint8_t rxIrq; @@ -153,8 +162,8 @@ extern const uartHardware_t uartHardware[]; typedef struct uartDevice_s { uartPort_t port; const uartHardware_t *hardware; - ioTag_t rx; - ioTag_t tx; + uartPinDef_t rx; + uartPinDef_t tx; volatile uint8_t rxBuffer[UART_RX_BUFFER_SIZE]; volatile uint8_t txBuffer[UART_TX_BUFFER_SIZE]; } uartDevice_t; diff --git a/src/main/drivers/serial_uart_pinconfig.c b/src/main/drivers/serial_uart_pinconfig.c index d9d6f9ad90..df0a6277f4 100644 --- a/src/main/drivers/serial_uart_pinconfig.c +++ b/src/main/drivers/serial_uart_pinconfig.c @@ -52,14 +52,16 @@ void uartPinConfigure(const serialPinConfig_t *pSerialPinConfig) const UARTDevice_e device = hardware->device; for (int pindex = 0 ; pindex < UARTHARDWARE_MAX_PINS ; pindex++) { - if (hardware->rxPins[pindex] && (hardware->rxPins[pindex] == pSerialPinConfig->ioTagRx[device])) - uartdev->rx = pSerialPinConfig->ioTagRx[device]; + if (hardware->rxPins[pindex].pin == pSerialPinConfig->ioTagRx[device]) { + uartdev->rx = hardware->rxPins[pindex]; + } - if (hardware->txPins[pindex] && (hardware->txPins[pindex] == pSerialPinConfig->ioTagTx[device])) - uartdev->tx = pSerialPinConfig->ioTagTx[device]; + if (hardware->txPins[pindex].pin == pSerialPinConfig->ioTagTx[device]) { + uartdev->tx = hardware->txPins[pindex]; + } } - if (uartdev->rx || uartdev->tx) { + if (uartdev->rx.pin || uartdev->tx.pin) { uartdev->hardware = hardware; uartDevmap[device] = uartdev++; } diff --git a/src/main/drivers/serial_uart_stm32f10x.c b/src/main/drivers/serial_uart_stm32f10x.c index b6a7ac3c9d..ad2318dd3c 100644 --- a/src/main/drivers/serial_uart_stm32f10x.c +++ b/src/main/drivers/serial_uart_stm32f10x.c @@ -67,8 +67,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { .reg = USART1, .rxDMAChannel = UART1_RX_DMA_CHANNEL, .txDMAChannel = UART1_TX_DMA_CHANNEL, - .rxPins = { DEFIO_TAG_E(PA10), DEFIO_TAG_E(PB7), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PA9), DEFIO_TAG_E(PB6), IO_TAG_NONE }, + .rxPins = { { DEFIO_TAG_E(PA10) }, { DEFIO_TAG_E(PB7) } }, + .txPins = { { DEFIO_TAG_E(PA9) }, { DEFIO_TAG_E(PB6) } }, //.af = GPIO_AF_USART1, .rcc = RCC_APB2(USART1), .irqn = USART1_IRQn, @@ -82,8 +82,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { .reg = USART2, .rxDMAChannel = UART2_RX_DMA_CHANNEL, .txDMAChannel = UART2_TX_DMA_CHANNEL, - .rxPins = { DEFIO_TAG_E(PA3), DEFIO_TAG_E(PD6), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PA2), DEFIO_TAG_E(PD5), IO_TAG_NONE }, + .rxPins = { { DEFIO_TAG_E(PA3) }, { DEFIO_TAG_E(PD6) } }, + .txPins = { { DEFIO_TAG_E(PA2) }, { DEFIO_TAG_E(PD5) } }, //.af = GPIO_AF_USART2, .rcc = RCC_APB1(USART2), .irqn = USART2_IRQn, @@ -97,8 +97,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { .reg = USART3, .rxDMAChannel = UART3_RX_DMA_CHANNEL, .txDMAChannel = UART3_TX_DMA_CHANNEL, - .rxPins = { DEFIO_TAG_E(PB11), DEFIO_TAG_E(PD9), DEFIO_TAG_E(PC11) }, - .txPins = { DEFIO_TAG_E(PB10), DEFIO_TAG_E(PD8), DEFIO_TAG_E(PC10) }, + .rxPins = { { DEFIO_TAG_E(PB11) }, { DEFIO_TAG_E(PD9) }, { DEFIO_TAG_E(PC11) } }, + .txPins = { { DEFIO_TAG_E(PB10) }, { DEFIO_TAG_E(PD8) }, { DEFIO_TAG_E(PC10) } }, //.af = GPIO_AF_USART3, .rcc = RCC_APB1(USART3), .irqn = USART3_IRQn, @@ -157,8 +157,8 @@ uartPort_t *serialUART(UARTDevice_e device, uint32_t baudRate, portMode_e mode, s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR; } - IO_t rxIO = IOGetByTag(uartdev->rx); - IO_t txIO = IOGetByTag(uartdev->tx); + IO_t rxIO = IOGetByTag(uartdev->rx.pin); + IO_t txIO = IOGetByTag(uartdev->tx.pin); if (options & SERIAL_BIDIR) { IOInit(txIO, OWNER_SERIAL_TX, RESOURCE_INDEX(device)); diff --git a/src/main/drivers/serial_uart_stm32f30x.c b/src/main/drivers/serial_uart_stm32f30x.c index 68574d5de3..457058907c 100644 --- a/src/main/drivers/serial_uart_stm32f30x.c +++ b/src/main/drivers/serial_uart_stm32f30x.c @@ -90,8 +90,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { .reg = USART1, .rxDMAChannel = UART1_RX_DMA, .txDMAChannel = UART1_TX_DMA, - .rxPins = { DEFIO_TAG_E(PA10), DEFIO_TAG_E(PB7), DEFIO_TAG_E(PC5), DEFIO_TAG_E(PE1) }, - .txPins = { DEFIO_TAG_E(PA9), DEFIO_TAG_E(PB6), DEFIO_TAG_E(PC4), DEFIO_TAG_E(PE0) }, + .rxPins = { { DEFIO_TAG_E(PA10) }, { DEFIO_TAG_E(PB7) }, { DEFIO_TAG_E(PC5) }, { DEFIO_TAG_E(PE1) } }, + .txPins = { { DEFIO_TAG_E(PA9) }, { DEFIO_TAG_E(PB6) }, { DEFIO_TAG_E(PC4) }, { DEFIO_TAG_E(PE0) } }, .rcc = RCC_APB2(USART1), .af = GPIO_AF_7, .irqn = USART1_IRQn, @@ -106,8 +106,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { .reg = USART2, .rxDMAChannel = UART2_RX_DMA, .txDMAChannel = UART2_TX_DMA, - .rxPins = { DEFIO_TAG_E(PA15), DEFIO_TAG_E(PA3), DEFIO_TAG_E(PB4), DEFIO_TAG_E(PD6) }, - .txPins = { DEFIO_TAG_E(PA14), DEFIO_TAG_E(PA2), DEFIO_TAG_E(PB3), DEFIO_TAG_E(PD5) }, + .rxPins = { { DEFIO_TAG_E(PA15) }, { DEFIO_TAG_E(PA3) }, { DEFIO_TAG_E(PB4) }, { DEFIO_TAG_E(PD6) } }, + .txPins = { { DEFIO_TAG_E(PA14) }, { DEFIO_TAG_E(PA2) }, { DEFIO_TAG_E(PB3) }, { DEFIO_TAG_E(PD5) } }, .rcc = RCC_APB1(USART2), .af = GPIO_AF_7, .irqn = USART2_IRQn, @@ -122,8 +122,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { .reg = USART3, .rxDMAChannel = UART3_RX_DMA, .txDMAChannel = UART3_TX_DMA, - .rxPins = { DEFIO_TAG_E(PB11), DEFIO_TAG_E(PC11), DEFIO_TAG_E(PD9), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PB10), DEFIO_TAG_E(PC10), DEFIO_TAG_E(PD8), IO_TAG_NONE }, + .rxPins = { { DEFIO_TAG_E(PB11) }, { DEFIO_TAG_E(PC11) }, { DEFIO_TAG_E(PD9) } }, + .txPins = { { DEFIO_TAG_E(PB10) }, { DEFIO_TAG_E(PC10) }, { DEFIO_TAG_E(PD8) } }, .rcc = RCC_APB1(USART3), .af = GPIO_AF_7, .irqn = USART3_IRQn, @@ -139,8 +139,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { .reg = UART4, .rxDMAChannel = 0, // XXX UART4_RX_DMA !? .txDMAChannel = 0, // XXX UART4_TX_DMA !? - .rxPins = { DEFIO_TAG_E(PC11), IO_TAG_NONE, IO_TAG_NONE, IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PC10), IO_TAG_NONE, IO_TAG_NONE, IO_TAG_NONE }, + .rxPins = { { DEFIO_TAG_E(PC11) } }, + .txPins = { { DEFIO_TAG_E(PC10) } }, .rcc = RCC_APB1(UART4), .af = GPIO_AF_5, .irqn = UART4_IRQn, @@ -156,8 +156,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { .reg = UART5, .rxDMAChannel = 0, .txDMAChannel = 0, - .rxPins = { DEFIO_TAG_E(PD2), IO_TAG_NONE, IO_TAG_NONE, IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PC12), IO_TAG_NONE, IO_TAG_NONE, IO_TAG_NONE }, + .rxPins = { { DEFIO_TAG_E(PD2) } }, + .txPins = { { DEFIO_TAG_E(PC12) } }, .rcc = RCC_APB1(UART5), .af = GPIO_AF_5, .irqn = UART5_IRQn, @@ -242,7 +242,7 @@ uartPort_t *serialUART(UARTDevice_e device, uint32_t baudRate, portMode_e mode, s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->TDR; } - serialUARTInitIO(IOGetByTag(uartDev->tx), IOGetByTag(uartDev->rx), mode, options, hardware->af, device); + serialUARTInitIO(IOGetByTag(uartDev->tx.pin), IOGetByTag(uartDev->rx.pin), mode, options, hardware->af, device); if (!s->rxDMAChannel || !s->txDMAChannel) { NVIC_InitTypeDef NVIC_InitStructure; diff --git a/src/main/drivers/serial_uart_stm32f4xx.c b/src/main/drivers/serial_uart_stm32f4xx.c index 61ff2b49e9..88503aa3dc 100644 --- a/src/main/drivers/serial_uart_stm32f4xx.c +++ b/src/main/drivers/serial_uart_stm32f4xx.c @@ -51,8 +51,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART1_TX_DMA .txDMAStream = DMA2_Stream7, #endif - .rxPins = { DEFIO_TAG_E(PA10), DEFIO_TAG_E(PB7), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PA9), DEFIO_TAG_E(PB6), IO_TAG_NONE }, + .rxPins = { { DEFIO_TAG_E(PA10) }, { DEFIO_TAG_E(PB7) } }, + .txPins = { { DEFIO_TAG_E(PA9) }, { DEFIO_TAG_E(PB6) } }, .af = GPIO_AF_USART1, .rcc = RCC_APB2(USART1), .irqn = USART1_IRQn, @@ -72,8 +72,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART2_TX_DMA .txDMAStream = DMA1_Stream6, #endif - .rxPins = { DEFIO_TAG_E(PA3), DEFIO_TAG_E(PD6), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PA2), DEFIO_TAG_E(PD5), IO_TAG_NONE }, + .rxPins = { { DEFIO_TAG_E(PA3) }, { DEFIO_TAG_E(PD6) } }, + .txPins = { { DEFIO_TAG_E(PA2) }, { DEFIO_TAG_E(PD5) } }, .af = GPIO_AF_USART2, .rcc = RCC_APB1(USART2), .irqn = USART2_IRQn, @@ -93,8 +93,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART3_TX_DMA .txDMAStream = DMA1_Stream3, #endif - .rxPins = { DEFIO_TAG_E(PB11), DEFIO_TAG_E(PC11), DEFIO_TAG_E(PD9) }, - .txPins = { DEFIO_TAG_E(PB10), DEFIO_TAG_E(PC10), DEFIO_TAG_E(PD8) }, + .rxPins = { { DEFIO_TAG_E(PB11) }, { DEFIO_TAG_E(PC11) }, { DEFIO_TAG_E(PD9) } }, + .txPins = { { DEFIO_TAG_E(PB10) }, { DEFIO_TAG_E(PC10) }, { DEFIO_TAG_E(PD8) } }, .af = GPIO_AF_USART3, .rcc = RCC_APB1(USART3), .irqn = USART3_IRQn, @@ -114,8 +114,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART4_TX_DMA .txDMAStream = DMA1_Stream4, #endif - .rxPins = { DEFIO_TAG_E(PA1), DEFIO_TAG_E(PC11), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PA0), DEFIO_TAG_E(PC10), IO_TAG_NONE }, + .rxPins = { { DEFIO_TAG_E(PA1) }, { DEFIO_TAG_E(PC11) } }, + .txPins = { { DEFIO_TAG_E(PA0) }, { DEFIO_TAG_E(PC10) } }, .af = GPIO_AF_UART4, .rcc = RCC_APB1(UART4), .irqn = UART4_IRQn, @@ -135,8 +135,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART5_TX_DMA .txDMAStream = DMA1_Stream7, #endif - .rxPins = { DEFIO_TAG_E(PD2), IO_TAG_NONE, IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PC12), IO_TAG_NONE, IO_TAG_NONE }, + .rxPins = { { DEFIO_TAG_E(PD2) } }, + .txPins = { { DEFIO_TAG_E(PC12) } }, .af = GPIO_AF_UART5, .rcc = RCC_APB1(UART5), .irqn = UART5_IRQn, @@ -156,8 +156,8 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART6_TX_DMA .txDMAStream = DMA2_Stream6, #endif - .rxPins = { DEFIO_TAG_E(PC7), DEFIO_TAG_E(PG9), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PC6), DEFIO_TAG_E(PG14), IO_TAG_NONE }, + .rxPins = { { DEFIO_TAG_E(PC7) }, { DEFIO_TAG_E(PG9) } }, + .txPins = { { DEFIO_TAG_E(PC6) }, { DEFIO_TAG_E(PG14) } }, .af = GPIO_AF_USART6, .rcc = RCC_APB2(USART6), .irqn = USART6_IRQn, @@ -234,8 +234,8 @@ uartPort_t *serialUART(UARTDevice_e device, uint32_t baudRate, portMode_e mode, s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR; } - IO_t txIO = IOGetByTag(uart->tx); - IO_t rxIO = IOGetByTag(uart->rx); + IO_t txIO = IOGetByTag(uart->tx.pin); + IO_t rxIO = IOGetByTag(uart->rx.pin); if (hardware->rcc) { RCC_ClockCmd(hardware->rcc, ENABLE); diff --git a/src/main/drivers/serial_uart_stm32f7xx.c b/src/main/drivers/serial_uart_stm32f7xx.c index 6cc4517be6..bbafc556f2 100644 --- a/src/main/drivers/serial_uart_stm32f7xx.c +++ b/src/main/drivers/serial_uart_stm32f7xx.c @@ -53,9 +53,20 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART1_TX_DMA .txDMAStream = DMA2_Stream7, #endif - .rxPins = { DEFIO_TAG_E(PA10), DEFIO_TAG_E(PB7), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PA9), DEFIO_TAG_E(PB6), IO_TAG_NONE }, - .af = GPIO_AF7_USART1, + .rxPins = { + { DEFIO_TAG_E(PA10), GPIO_AF7_USART1 }, + { DEFIO_TAG_E(PB7), GPIO_AF7_USART1 }, +#ifdef STM32F765xx + { DEFIO_TAG_E(PB15), GPIO_AF4_USART1 } +#endif + }, + .txPins = { + { DEFIO_TAG_E(PA9), GPIO_AF7_USART1 }, + { DEFIO_TAG_E(PB6), GPIO_AF7_USART1 }, +#ifdef STM32F765xx + { DEFIO_TAG_E(PB14), GPIO_AF4_USART1 } +#endif + }, #ifdef UART1_AHB1_PERIPHERALS .rcc_ahb1 = UART1_AHB1_PERIPHERALS, #endif @@ -78,9 +89,14 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART2_TX_DMA .txDMAStream = DMA1_Stream6, #endif - .rxPins = { DEFIO_TAG_E(PA3), DEFIO_TAG_E(PD6), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PA2), DEFIO_TAG_E(PD5), IO_TAG_NONE }, - .af = GPIO_AF7_USART2, + .rxPins = { + { DEFIO_TAG_E(PA3), GPIO_AF7_USART2 }, + { DEFIO_TAG_E(PD6), GPIO_AF7_USART2 } + }, + .txPins = { + { DEFIO_TAG_E(PA2), GPIO_AF7_USART2 }, + { DEFIO_TAG_E(PD5), GPIO_AF7_USART2 } + }, #ifdef UART2_AHB1_PERIPHERALS .rcc_ahb1 = UART2_AHB1_PERIPHERALS, #endif @@ -103,9 +119,16 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART3_TX_DMA .txDMAStream = DMA1_Stream3, #endif - .rxPins = { DEFIO_TAG_E(PB11), DEFIO_TAG_E(PC11), DEFIO_TAG_E(PD9) }, - .txPins = { DEFIO_TAG_E(PB10), DEFIO_TAG_E(PC10), DEFIO_TAG_E(PD8) }, - .af = GPIO_AF7_USART3, + .rxPins = { + { DEFIO_TAG_E(PB11), GPIO_AF7_USART3 }, + { DEFIO_TAG_E(PC11), GPIO_AF7_USART3 }, + { DEFIO_TAG_E(PD9), GPIO_AF7_USART3 } + }, + .txPins = { + { DEFIO_TAG_E(PB10), GPIO_AF7_USART3 }, + { DEFIO_TAG_E(PC10), GPIO_AF7_USART3 }, + { DEFIO_TAG_E(PD8), GPIO_AF7_USART3 } + }, #ifdef UART3_AHB1_PERIPHERALS .rcc_ahb1 = UART3_AHB1_PERIPHERALS, #endif @@ -128,9 +151,22 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART4_TX_DMA .txDMAStream = DMA1_Stream4, #endif - .rxPins = { DEFIO_TAG_E(PA1), DEFIO_TAG_E(PC11), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PA0), DEFIO_TAG_E(PC10), IO_TAG_NONE }, - .af = GPIO_AF8_UART4, + .rxPins = { + { DEFIO_TAG_E(PA1), GPIO_AF8_UART4 }, + { DEFIO_TAG_E(PC11), GPIO_AF8_UART4 }, +#ifdef STM32F765xx + { DEFIO_TAG_E(PA11), GPIO_AF6_UART4 }, + { DEFIO_TAG_E(PD0), GPIO_AF8_UART4 } +#endif + }, + .txPins = { + { DEFIO_TAG_E(PA0), GPIO_AF8_UART4 }, + { DEFIO_TAG_E(PC10), GPIO_AF8_UART4 }, +#ifdef STM32F765xx + { DEFIO_TAG_E(PA12), GPIO_AF6_UART4 }, + { DEFIO_TAG_E(PD1), GPIO_AF8_UART4 } +#endif + }, #ifdef UART4_AHB1_PERIPHERALS .rcc_ahb1 = UART4_AHB1_PERIPHERALS, #endif @@ -153,9 +189,22 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART5_TX_DMA .txDMAStream = DMA1_Stream7, #endif - .rxPins = { DEFIO_TAG_E(PD2), IO_TAG_NONE, IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PC12), IO_TAG_NONE, IO_TAG_NONE }, - .af = GPIO_AF8_UART5, + .rxPins = { + { DEFIO_TAG_E(PD2), GPIO_AF8_UART5 }, +#ifdef STM32F765xx + { DEFIO_TAG_E(PB5), GPIO_AF1_UART5 }, + { DEFIO_TAG_E(PB8), GPIO_AF7_UART5 }, + { DEFIO_TAG_E(PB12), GPIO_AF8_UART5 } +#endif + }, + .txPins = { + { DEFIO_TAG_E(PC12), GPIO_AF8_UART5 }, +#ifdef STM32F765xx + { DEFIO_TAG_E(PB6), GPIO_AF1_UART5 }, + { DEFIO_TAG_E(PB9), GPIO_AF7_UART5 }, + { DEFIO_TAG_E(PB13), GPIO_AF8_UART5 } +#endif + }, #ifdef UART5_AHB1_PERIPHERALS .rcc_ahb1 = UART5_AHB1_PERIPHERALS, #endif @@ -178,9 +227,14 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART6_TX_DMA .txDMAStream = DMA2_Stream6, #endif - .rxPins = { DEFIO_TAG_E(PC7), DEFIO_TAG_E(PG9), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PC6), DEFIO_TAG_E(PG14), IO_TAG_NONE }, - .af = GPIO_AF8_USART6, + .rxPins = { + { DEFIO_TAG_E(PC7), GPIO_AF8_USART6 }, + { DEFIO_TAG_E(PG9), GPIO_AF8_USART6 } + }, + .txPins = { + { DEFIO_TAG_E(PC6), GPIO_AF8_USART6 }, + { DEFIO_TAG_E(PG14), GPIO_AF8_USART6 } + }, #ifdef UART6_AHB1_PERIPHERALS .rcc_ahb1 = UART6_AHB1_PERIPHERALS, #endif @@ -203,9 +257,22 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART7_TX_DMA .txDMAStream = DMA1_Stream1, #endif - .rxPins = { DEFIO_TAG_E(PE7), DEFIO_TAG_E(PF6), IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PE8), DEFIO_TAG_E(PF7), IO_TAG_NONE }, - .af = GPIO_AF8_UART7, + .rxPins = { + { DEFIO_TAG_E(PE7), GPIO_AF8_UART7 }, + { DEFIO_TAG_E(PF6), GPIO_AF8_UART7 }, +#ifdef STM32F765xx + { DEFIO_TAG_E(PA8), GPIO_AF12_UART7 }, + { DEFIO_TAG_E(PB3), GPIO_AF12_UART7 } +#endif + }, + .txPins = { + { DEFIO_TAG_E(PE8), GPIO_AF8_UART7 }, + { DEFIO_TAG_E(PF7), GPIO_AF8_UART7 }, +#ifdef STM32F765xx + { DEFIO_TAG_E(PA15), GPIO_AF12_UART7 }, + { DEFIO_TAG_E(PB4), GPIO_AF12_UART7 } +#endif + }, #ifdef UART7_AHB1_PERIPHERALS .rcc_ahb1 = UART7_AHB1_PERIPHERALS, #endif @@ -228,9 +295,12 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { #ifdef USE_UART8_TX_DMA .txDMAStream = DMA1_Stream0, #endif - .rxPins = { DEFIO_TAG_E(PE0), IO_TAG_NONE, IO_TAG_NONE }, - .txPins = { DEFIO_TAG_E(PE1), IO_TAG_NONE, IO_TAG_NONE }, - .af = GPIO_AF8_UART8, + .rxPins = { + { DEFIO_TAG_E(PE0), GPIO_AF8_UART8 } + }, + .txPins = { + { DEFIO_TAG_E(PE1), GPIO_AF8_UART8 } + }, #ifdef UART8_AHB1_PERIPHERALS .rcc_ahb1 = UART8_AHB1_PERIPHERALS, #endif @@ -371,8 +441,8 @@ uartPort_t *serialUART(UARTDevice_e device, uint32_t baudRate, portMode_e mode, s->Handle.Instance = hardware->reg; - IO_t txIO = IOGetByTag(uartdev->tx); - IO_t rxIO = IOGetByTag(uartdev->rx); + IO_t txIO = IOGetByTag(uartdev->tx.pin); + IO_t rxIO = IOGetByTag(uartdev->rx.pin); if ((options & SERIAL_BIDIR) && txIO) { ioConfig_t ioCfg = IO_CONFIG( @@ -382,17 +452,17 @@ uartPort_t *serialUART(UARTDevice_e device, uint32_t baudRate, portMode_e mode, ); IOInit(txIO, OWNER_SERIAL_TX, RESOURCE_INDEX(device)); - IOConfigGPIOAF(txIO, ioCfg, hardware->af); + IOConfigGPIOAF(txIO, ioCfg, uartdev->tx.af); } else { if ((mode & MODE_TX) && txIO) { IOInit(txIO, OWNER_SERIAL_TX, RESOURCE_INDEX(device)); - IOConfigGPIOAF(txIO, IOCFG_AF_PP, hardware->af); + IOConfigGPIOAF(txIO, IOCFG_AF_PP, uartdev->tx.af); } if ((mode & MODE_RX) && rxIO) { IOInit(rxIO, OWNER_SERIAL_RX, RESOURCE_INDEX(device)); - IOConfigGPIOAF(rxIO, IOCFG_AF_PP, hardware->af); + IOConfigGPIOAF(rxIO, IOCFG_AF_PP, uartdev->rx.af); } } diff --git a/src/main/platform.h b/src/main/platform.h index dda24d52b7..d297a8a159 100644 --- a/src/main/platform.h +++ b/src/main/platform.h @@ -26,7 +26,7 @@ #pragma GCC poison sprintf snprintf #endif -#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F722xx) +#if defined(STM32F722xx) || defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F765xx) #include "stm32f7xx.h" #include "stm32f7xx_hal.h" #include "system_stm32f7xx.h" diff --git a/src/main/startup/startup_stm32f765xx.s b/src/main/startup/startup_stm32f765xx.s new file mode 100644 index 0000000000..07f79cc0b6 --- /dev/null +++ b/src/main/startup/startup_stm32f765xx.s @@ -0,0 +1,654 @@ +/** + ****************************************************************************** + * @file startup_stm32f765xx.s + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief STM32F765xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* start address for the .fastram_bss section. defined in linker script */ +.word _sfastram_bss +/* end address for the .fastram_bss section. defined in linker script */ +.word _efastram_bss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + + ldr r2, =_ssram2 + b LoopFillZerosram2 +/* Zero fill the sram2 segment. */ +FillZerosram2: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerosram2: + ldr r3, = _esram2 + cmp r2, r3 + bcc FillZerosram2 + + ldr r2, =_sfastram_bss + b LoopFillZerofastram_bss +/* Zero fill the fastram_bss segment. */ +FillZerofastram_bss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerofastram_bss: + ldr r3, = _efastram_bss + cmp r2, r3 + bcc FillZerofastram_bss + +/* Call the clock system initialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word 0 /* Reserved */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word CAN3_TX_IRQHandler /* CAN3 TX */ + .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ + .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ + .word CAN3_SCE_IRQHandler /* CAN3 SCE */ + .word 0 /* Reserved */ + .word MDIOS_IRQHandler /* MDIOS */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak CAN3_TX_IRQHandler + .thumb_set CAN3_TX_IRQHandler,Default_Handler + + .weak CAN3_RX0_IRQHandler + .thumb_set CAN3_RX0_IRQHandler,Default_Handler + + .weak CAN3_RX1_IRQHandler + .thumb_set CAN3_RX1_IRQHandler,Default_Handler + + .weak CAN3_SCE_IRQHandler + .thumb_set CAN3_SCE_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/src/main/target/link/stm32_flash_f765.ld b/src/main/target/link/stm32_flash_f765.ld new file mode 100644 index 0000000000..f5faee1612 --- /dev/null +++ b/src/main/target/link/stm32_flash_f765.ld @@ -0,0 +1,51 @@ +/* +***************************************************************************** +** +** File : stm32_flash_f765.ld +** +** Abstract : Linker script for STM32F765xITx Device with +** 2048KByte FLASH, 512KByte RAM +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* +0x00000000 to 0x00003FFF 16K TCM RAM, + +0x08000000 to 0x081FFFFF 2048K full flash, +0x08000000 to 0x08007FFF 32K isr vector, startup code, +0x08008000 to 0x0800FFFF 32K config, +0x08010000 to 0x081FFFFF 1984K firmware, +*/ + +/* Specify the memory areas */ +MEMORY +{ + ITCM_RAM (rx) : ORIGIN = 0x00000000, LENGTH = 16K + + ITCM_FLASH (rx) : ORIGIN = 0x00200000, LENGTH = 32K + ITCM_FLASH_CONFIG (r) : ORIGIN = 0x00208000, LENGTH = 32K + ITCM_FLASH1 (rx) : ORIGIN = 0x00210000, LENGTH = 1984K + + AXIM_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K + AXIM_FLASH_CONFIG (r) : ORIGIN = 0x08008000, LENGTH = 32K + AXIM_FLASH1 (rx) : ORIGIN = 0x08010000, LENGTH = 1984K + + DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K + SRAM1 (rwx) : ORIGIN = 0x20020000, LENGTH = 368K + SRAM2 (rwx) : ORIGIN = 0x2007C000, LENGTH = 16K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +REGION_ALIAS("FLASH", AXIM_FLASH) +REGION_ALIAS("FLASH_CONFIG", AXIM_FLASH_CONFIG) +REGION_ALIAS("FLASH1", AXIM_FLASH1) + +REGION_ALIAS("STACKRAM", DTCM_RAM) +REGION_ALIAS("FASTRAM", DTCM_RAM) +REGION_ALIAS("RAM", DTCM_RAM) + +INCLUDE "stm32_flash_f7_split.ld"