diff --git a/src/main/target/CJMCU/target.h b/src/main/target/CJMCU/target.h
index 6952ce9c12..bd4360ab45 100644
--- a/src/main/target/CJMCU/target.h
+++ b/src/main/target/CJMCU/target.h
@@ -67,15 +67,13 @@
 // Nordic Semiconductor uses 'CSN', STM uses 'NSS'
 #define RX_CE_PIN               PA4
 #define RX_NSS_PIN              PA11
-#define RX_SCK_PIN              PA5
-#define RX_MISO_PIN             PA6
-#define RX_MOSI_PIN             PA7
 #define RX_IRQ_PIN              PA8
 // CJMCU has NSS on PA11, rather than the standard PA4
 #define SPI1_NSS_PIN            RX_NSS_PIN
-#define SPI1_SCK_PIN            RX_SCK_PIN
-#define SPI1_MISO_PIN           RX_MISO_PIN
-#define SPI1_MOSI_PIN           RX_MOSI_PIN
+
+#define SPI1_SCK_PIN            PA5
+#define SPI1_MISO_PIN           PA6
+#define SPI1_MOSI_PIN           PA7
 
 #define USE_RX_NRF24
 #define USE_RX_CX10
diff --git a/src/main/target/CRAZYBEEF3FR/target.h b/src/main/target/CRAZYBEEF3FR/target.h
index c6ebce2134..057487ad1d 100644
--- a/src/main/target/CRAZYBEEF3FR/target.h
+++ b/src/main/target/CRAZYBEEF3FR/target.h
@@ -137,9 +137,6 @@
 #define RX_SPI_DEFAULT_PROTOCOL RX_SPI_FRSKY_X
 #define RX_SPI_INSTANCE         SPI2
 #define RX_NSS_PIN              SPI2_NSS_PIN
-#define RX_SCK_PIN              SPI2_SCK_PIN
-#define RX_MISO_PIN             SPI2_MISO_PIN
-#define RX_MOSI_PIN             SPI2_MOSI_PIN
 #define RX_FRSKY_SPI_GDO_0_PIN  PA8
 #define RX_FRSKY_SPI_LED_PIN    PA10
 #define BINDPLUG_PIN            PA9
diff --git a/src/main/target/MATEKF411RX/target.h b/src/main/target/MATEKF411RX/target.h
index ac541410d9..780d2a3701 100644
--- a/src/main/target/MATEKF411RX/target.h
+++ b/src/main/target/MATEKF411RX/target.h
@@ -67,15 +67,10 @@
 #define SPI3_SCK_PIN            PB3
 #define SPI3_MISO_PIN           PB4
 #define SPI3_MOSI_PIN           PB5
-#define SPI3_NSS_PIN            PA15
 
 #define USE_RX_SPI
 #define RX_SPI_INSTANCE         SPI3
-
-#define RX_SCK_PIN              SPI3_SCK_PIN
-#define RX_MISO_PIN             SPI3_MISO_PIN
-#define RX_MOSI_PIN             SPI3_MOSI_PIN
-#define RX_NSS_PIN              SPI3_NSS_PIN
+#define RX_NSS_PIN              PA15
 
 #define RX_FRSKY_SPI_DISABLE_CHIP_DETECTION
 #define RX_FRSKY_SPI_GDO_0_PIN     PC14
diff --git a/src/main/target/MIDELICF3/target.h b/src/main/target/MIDELICF3/target.h
index 2ec8f8a47c..8ecf651940 100644
--- a/src/main/target/MIDELICF3/target.h
+++ b/src/main/target/MIDELICF3/target.h
@@ -72,21 +72,19 @@
 #define USE_SPI
 
 #define USE_SPI_DEVICE_1
-#define SPI1_NSS_PIN            PA4
 #define SPI1_SCK_PIN            PA5
 #define SPI1_MISO_PIN           PA6
 #define SPI1_MOSI_PIN           PA7
 
 #define USE_SPI_DEVICE_2
-#define SPI2_NSS_PIN            PB12
 #define SPI2_SCK_PIN            PB13
 #define SPI2_MISO_PIN           PB14
 #define SPI2_MOSI_PIN           PB15
 
 #define USE_SDCARD
-#define SDCARD_SPI_INSTANCE                 SPI2
-#define SDCARD_SPI_CS_PIN                   SPI2_NSS_PIN
-#define SDCARD_DMA_CHANNEL_TX               DMA1_Channel5
+#define SDCARD_SPI_INSTANCE     SPI2
+#define SDCARD_SPI_CS_PIN       PB12
+#define SDCARD_DMA_CHANNEL_TX   DMA1_Channel5
 
 #define USE_ADC
 #define ADC_INSTANCE            ADC1
@@ -109,10 +107,7 @@
 #define RX_SPI_DEFAULT_PROTOCOL RX_SPI_FRSKY_X
 #define USE_RX_FRSKY_SPI_TELEMETRY
 
-#define RX_NSS_PIN               SPI1_NSS_PIN
-#define RX_SCK_PIN               SPI1_SCK_PIN
-#define RX_MISO_PIN              SPI1_MISO_PIN
-#define RX_MOSI_PIN              SPI1_MOSI_PIN
+#define RX_NSS_PIN               PA4
 
 #define RX_FRSKY_SPI_GDO_0_PIN   PB0
 
diff --git a/src/main/target/NUCLEOF446RE/target.h b/src/main/target/NUCLEOF446RE/target.h
index 876780909f..1b386ecffc 100644
--- a/src/main/target/NUCLEOF446RE/target.h
+++ b/src/main/target/NUCLEOF446RE/target.h
@@ -91,14 +91,12 @@
 // Nordic Semiconductor uses 'CSN', STM uses 'NSS'
 #define RX_CE_PIN               PC7 // D9
 #define RX_NSS_PIN              PB6 // D10
-#define RX_SCK_PIN              PA5 // D13
-#define RX_MISO_PIN             PA6 // D12
-#define RX_MOSI_PIN             PA7 // D11
 // NUCLEO has NSS on PB6, rather than the standard PA4
+
 #define SPI1_NSS_PIN            RX_NSS_PIN
-#define SPI1_SCK_PIN            RX_SCK_PIN
-#define SPI1_MISO_PIN           RX_MISO_PIN
-#define SPI1_MOSI_PIN           RX_MOSI_PIN
+#define SPI1_SCK_PIN            PA5 // D13
+#define SPI1_MISO_PIN           PA6 // D12
+#define SPI1_MOSI_PIN           PA7 // D11
 
 #define USE_RX_NRF24
 #define USE_RX_CX10