Preparations for release of H563 target (#13657)

Adding H5 middle ware

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h523xx.h

@@ -0,0 +1,660 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32h523xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H523xx Device Header File for Initial Setup for Secure /
+  *          Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
+  *          Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************
+  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+  * Copyright (c) 2023 STMicroelectronics. All rights reserved.  
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  ******************************************************************************
+  */
+
+#ifndef PARTITION_STM32H523XX_H
+#define PARTITION_STM32H523XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          1
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   0
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS    1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x0C03E000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x0C03FFFF      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       1
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x08040000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x0807FFFF      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x20034000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x20043FFF      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x40000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x4FFFFFFF      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x60000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x9FFFFFFF      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x0BF90000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x0BFA8FFF      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL      0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL          0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL     0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  WWDG_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.1>  PVD_AVD_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  RTC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RTC_S_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TAMP_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.5>  RAMCFG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.6>  FLASH_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FLASH_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  GTZC_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.9>  RCC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.10> RCC_S_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.11> EXTI0_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.12> EXTI1_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.13> EXTI2_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> EXTI3_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.15> EXTI4_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.16> EXTI5_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.17> EXTI6_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.18> EXTI7_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.19> EXTI8_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI9_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI10_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI11_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI12_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI13_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI14_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI15_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA1_Channel0_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA1_Channel1_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA1_Channel2_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA1_Channel3_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA1_Channel4_IRQn   <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  GPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  IWDG_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.6>  DAC1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FDCAN1_IT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FDCAN1_IT1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.9>  TIM1_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> TIM1_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> TIM1_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.12> TIM1_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> TIM2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.14> TIM3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.15> TIM4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM7_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.19> I2C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> I2C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> I2C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.22> I2C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> SPI1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.24> SPI2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> SPI3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> USART1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> USART2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> USART3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> UART4_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.30> UART5_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.31> LPUART1_IRQn          <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  LPTIM1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  TIM8_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  TIM8_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  TIM8_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TIM8_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.6>  LPTIM2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM15_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.10> USB_DRD_FS_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.11> CRS_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.12> UCPD1_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.13> FMC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.14> OCTOSPI1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> SDMMC1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.16> I2C3_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> I2C3_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> SPI4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.21> USART6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> GPDMA2_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA2_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA2_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA2_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA2_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA2_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..127
+//   <o.0>  GPDMA2_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA2_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FPU_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.8>  ICACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.9>  DCACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.12> DCMI_PSSI_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.13> FDCAN2_IT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.14> FDCAN2_IT1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.17> DTS_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.18> RNG_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.21> HASH_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.23> CEC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.24> TIM12_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.27> I3C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> I3C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 131..132)
+*/
+#define NVIC_INIT_ITNS4    1
+
+/*
+// Interrupts 131..132
+//   <o.3>  I3C2_EV_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.4>  I3C2_ER_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+}
+
+#endif  /* PARTITION_STM32H523XX_H */

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h533xx.h

@@ -0,0 +1,664 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32h533xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H533xx Device Header File for Initial Setup for Secure /
+  *          Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
+  *          Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************
+  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+  * Copyright (c) 2023 STMicroelectronics. All rights reserved.  
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  ******************************************************************************
+  */
+
+#ifndef PARTITION_STM32H533XX_H
+#define PARTITION_STM32H533XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          1
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   0
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS    1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x0C03E000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x0C03FFFF      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       1
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x08040000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x0807FFFF      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x20034000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x20043FFF      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x40000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x4FFFFFFF      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x60000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x9FFFFFFF      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x0BF90000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x0BFA8FFF      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL      0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL          0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL     0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  WWDG_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.1>  PVD_AVD_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  RTC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RTC_S_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TAMP_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.5>  RAMCFG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.6>  FLASH_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FLASH_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  GTZC_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.9>  RCC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.10> RCC_S_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.11> EXTI0_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.12> EXTI1_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.13> EXTI2_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> EXTI3_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.15> EXTI4_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.16> EXTI5_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.17> EXTI6_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.18> EXTI7_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.19> EXTI8_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI9_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI10_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI11_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI12_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI13_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI14_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI15_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA1_Channel0_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA1_Channel1_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA1_Channel2_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA1_Channel3_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA1_Channel4_IRQn   <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  GPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  IWDG_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.4>  SAES_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.6>  DAC1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FDCAN1_IT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FDCAN1_IT1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.9>  TIM1_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> TIM1_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> TIM1_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.12> TIM1_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> TIM2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.14> TIM3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.15> TIM4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM7_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.19> I2C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> I2C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> I2C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.22> I2C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> SPI1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.24> SPI2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> SPI3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> USART1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> USART2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> USART3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> UART4_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.30> UART5_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.31> LPUART1_IRQn          <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  LPTIM1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  TIM8_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  TIM8_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  TIM8_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TIM8_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.6>  LPTIM2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM15_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.10> USB_DRD_FS_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.11> CRS_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.12> UCPD1_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.13> FMC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.14> OCTOSPI1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> SDMMC1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.16> I2C3_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> I2C3_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> SPI4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.21> USART6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> GPDMA2_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA2_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA2_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA2_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA2_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA2_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..127
+//   <o.0>  GPDMA2_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA2_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FPU_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.8>  ICACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.9>  DCACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.12> DCMI_PSSI_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.13> FDCAN2_IT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.14> FDCAN2_IT1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.17> DTS_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.18> RNG_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.19> OTFDEC1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> AES_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.21> HASH_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.22> PKA_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.23> CEC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.24> TIM12_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.27> I3C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> I3C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 131..132)
+*/
+#define NVIC_INIT_ITNS4    1
+
+/*
+// Interrupts 131..132
+//   <o.3>  I3C2_EV_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.4>  I3C2_ER_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+}
+
+#endif  /* PARTITION_STM32H533XX_H */

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h562xx.h

@@ -0,0 +1,678 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32h562xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H562xx Device Header File for Initial Setup for Secure /
+  *          Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
+  *          Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************
+  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+  * Copyright (c) 2023 STMicroelectronics. All rights reserved.  
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  ******************************************************************************
+  */
+
+#ifndef PARTITION_STM32H562XX_H
+#define PARTITION_STM32H562XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          1
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   0
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS    1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x0C0FE000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x0C0FFFFF      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       1
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x08100000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x081FFFFF      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x20050000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x2009FFFF      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x40000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x4FFFFFFF      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x60000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x9FFFFFFF      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x0BF90000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x0BFA8FFF      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL      0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL          0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL     0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  WWDG_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.1>  PVD_AVD_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  RTC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RTC_S_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TAMP_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.5>  RAMCFG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.6>  FLASH_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FLASH_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  GTZC_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.9>  RCC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.10> RCC_S_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.11> EXTI0_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.12> EXTI1_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.13> EXTI2_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> EXTI3_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.15> EXTI4_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.16> EXTI5_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.17> EXTI6_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.18> EXTI7_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.19> EXTI8_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI9_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI10_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI11_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI12_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI13_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI14_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI15_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA1_Channel0_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA1_Channel1_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA1_Channel2_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA1_Channel3_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA1_Channel4_IRQn   <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  GPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  IWDG_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.6>  DAC1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FDCAN1_IT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FDCAN1_IT1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.9>  TIM1_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> TIM1_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> TIM1_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.12> TIM1_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> TIM2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.14> TIM3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.15> TIM4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM7_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.19> I2C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> I2C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> I2C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.22> I2C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> SPI1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.24> SPI2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> SPI3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> USART1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> USART2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> USART3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> UART4_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.30> UART5_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.31> LPUART1_IRQn          <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  LPTIM1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  TIM8_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  TIM8_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  TIM8_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TIM8_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.6>  LPTIM2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM15_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.8>  TIM16_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  TIM17_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.10> USB_DRD_FS_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.11> CRS_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.12> UCPD1_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.13> FMC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.14> OCTOSPI1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> SDMMC1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.16> I2C3_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> I2C3_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> SPI4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.19> SPI5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.20> SPI6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.21> USART6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> USART10_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> USART11_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.24> SAI1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> SAI2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> GPDMA2_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA2_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA2_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA2_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA2_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA2_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..127
+//   <o.0>  GPDMA2_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA2_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  UART7_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.3>  UART8_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  UART9_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.5>  UART12_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FPU_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.8>  ICACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.9>  DCACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.12> DCMI_PSSI_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.15> CORDIC_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.16> FMAC_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.17> DTS_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.18> RNG_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.21> HASH_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.23> CEC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.24> TIM12_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.25> TIM13_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.26> TIM14_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.27> I3C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> I3C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> I2C4_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> I2C4_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.31> LPTIM3_IRQn           <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 128..130)
+*/
+#define NVIC_INIT_ITNS4    1
+
+/*
+// Interrupts 128..130
+//   <o.0>  LPTIM4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.1>  LPTIM5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LPTIM6_IRQn          <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+}
+
+#endif  /* PARTITION_STM32H562XX_H */

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h563xx.h

@@ -0,0 +1,683 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32h563xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H563xx Device Header File for Initial Setup for Secure /
+  *          Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
+  *          Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************
+  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+  * Copyright (c) 2023 STMicroelectronics. All rights reserved.  
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  ******************************************************************************
+  */
+
+#ifndef PARTITION_STM32H563XX_H
+#define PARTITION_STM32H563XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          1
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   0
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS    1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x0C0FE000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x0C0FFFFF      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       1
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x08100000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x081FFFFF      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x20050000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x2009FFFF      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x40000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x4FFFFFFF      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x60000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x9FFFFFFF      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x0BF90000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x0BFA8FFF      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL      0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL          0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL     0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  WWDG_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.1>  PVD_AVD_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  RTC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RTC_S_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TAMP_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.5>  RAMCFG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.6>  FLASH_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FLASH_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  GTZC_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.9>  RCC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.10> RCC_S_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.11> EXTI0_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.12> EXTI1_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.13> EXTI2_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> EXTI3_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.15> EXTI4_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.16> EXTI5_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.17> EXTI6_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.18> EXTI7_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.19> EXTI8_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI9_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI10_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI11_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI12_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI13_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI14_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI15_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA1_Channel0_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA1_Channel1_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA1_Channel2_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA1_Channel3_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA1_Channel4_IRQn   <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  GPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  IWDG_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.6>  DAC1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FDCAN1_IT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FDCAN1_IT1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.9>  TIM1_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> TIM1_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> TIM1_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.12> TIM1_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> TIM2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.14> TIM3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.15> TIM4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM7_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.19> I2C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> I2C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> I2C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.22> I2C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> SPI1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.24> SPI2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> SPI3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> USART1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> USART2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> USART3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> UART4_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.30> UART5_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.31> LPUART1_IRQn          <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  LPTIM1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  TIM8_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  TIM8_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  TIM8_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TIM8_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.6>  LPTIM2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM15_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.8>  TIM16_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  TIM17_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.10> USB_DRD_FS_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.11> CRS_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.12> UCPD1_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.13> FMC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.14> OCTOSPI1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> SDMMC1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.16> I2C3_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> I2C3_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> SPI4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.19> SPI5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.20> SPI6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.21> USART6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> USART10_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> USART11_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.24> SAI1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> SAI2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> GPDMA2_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA2_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA2_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA2_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA2_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA2_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..127
+//   <o.0>  GPDMA2_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA2_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  UART7_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.3>  UART8_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  UART9_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.5>  UART12_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.6>  SDMMC2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FPU_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.8>  ICACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.9>  DCACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.10> ETH_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.11> ETH_WKUP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.12> DCMI_PSSI_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.13> FDCAN2_IT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.14> FDCAN2_IT1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.15> CORDIC_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.16> FMAC_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.17> DTS_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.18> RNG_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.21> HASH_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.23> CEC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.24> TIM12_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.25> TIM13_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.26> TIM14_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.27> I3C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> I3C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> I2C4_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> I2C4_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.31> LPTIM3_IRQn           <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 128..130)
+*/
+#define NVIC_INIT_ITNS4    1
+
+/*
+// Interrupts 128..130
+//   <o.0>  LPTIM4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.1>  LPTIM5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LPTIM6_IRQn          <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+}
+
+#endif  /* PARTITION_STM32H563XX_H */

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h573xx.h

@@ -0,0 +1,687 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32h573xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H573xx Device Header File for Initial Setup for Secure /
+  *          Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
+  *          Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************
+  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+  * Copyright (c) 2023 STMicroelectronics. All rights reserved.  
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  ******************************************************************************
+  */
+
+#ifndef PARTITION_STM32H573XX_H
+#define PARTITION_STM32H573XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          1
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   0
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS    1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x0C0FE000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x0C0FFFFF      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       1
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x08100000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x081FFFFF      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x20050000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x2009FFFF      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x40000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x4FFFFFFF      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x60000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x9FFFFFFF      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x0BF90000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x0BFA8FFF      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL      0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL          0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL     0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  WWDG_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.1>  PVD_AVD_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  RTC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RTC_S_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TAMP_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.5>  RAMCFG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.6>  FLASH_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FLASH_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  GTZC_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.9>  RCC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.10> RCC_S_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.11> EXTI0_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.12> EXTI1_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.13> EXTI2_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> EXTI3_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.15> EXTI4_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.16> EXTI5_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.17> EXTI6_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.18> EXTI7_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.19> EXTI8_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI9_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI10_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI11_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI12_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI13_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI14_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI15_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA1_Channel0_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA1_Channel1_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA1_Channel2_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA1_Channel3_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA1_Channel4_IRQn   <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  GPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  IWDG_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.4>  SAES_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.6>  DAC1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FDCAN1_IT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FDCAN1_IT1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.9>  TIM1_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> TIM1_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> TIM1_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.12> TIM1_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> TIM2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.14> TIM3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.15> TIM4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM7_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.19> I2C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> I2C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> I2C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.22> I2C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> SPI1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.24> SPI2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> SPI3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> USART1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> USART2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> USART3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> UART4_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.30> UART5_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.31> LPUART1_IRQn          <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  LPTIM1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  TIM8_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  TIM8_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  TIM8_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TIM8_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.6>  LPTIM2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM15_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.8>  TIM16_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  TIM17_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.10> USB_DRD_FS_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.11> CRS_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.12> UCPD1_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.13> FMC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.14> OCTOSPI1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> SDMMC1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.16> I2C3_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> I2C3_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> SPI4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.19> SPI5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.20> SPI6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.21> USART6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> USART10_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> USART11_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.24> SAI1_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> SAI2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> GPDMA2_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA2_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA2_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA2_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA2_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA2_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..127
+//   <o.0>  GPDMA2_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA2_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  UART7_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.3>  UART8_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  UART9_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.5>  UART12_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.6>  SDMMC2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FPU_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.8>  ICACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.9>  DCACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.10> ETH_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.11> ETH_WKUP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.12> DCMI_PSSI_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.13> FDCAN2_IT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.14> FDCAN2_IT1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.15> CORDIC_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.16> FMAC_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.17> DTS_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.18> RNG_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.19> OTFDEC1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> AES_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.21> HASH_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.22> PKA_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.23> CEC_IRQn              <0=> Secure state <1=> Non-Secure state
+//   <o.24> TIM12_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.25> TIM13_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.26> TIM14_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.27> I3C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> I3C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> I2C4_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> I2C4_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.31> LPTIM3_IRQn           <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 128..130)
+*/
+#define NVIC_INIT_ITNS4    1
+
+/*
+// Interrupts 128..130
+//   <o.0>  LPTIM4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.1>  LPTIM5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LPTIM6_IRQn          <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+}
+
+#endif  /* PARTITION_STM32H573XX_H */

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h

@@ -0,0 +1,79 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32h5xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H5xx Device Header File for Initial Setup for Secure /
+  *          Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
+  *          Template.
+  *
+  *          The file is included in system_stm32h5xx_s.c in secure application.
+  *          It includes the configuration section that allows to select the
+  *          STM32H5xx device partitioning file for system core secure attributes
+  *          and interrupt secure and non-secure assignment.
+  *
+  ******************************************************************************
+  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+  * Copyright (c) 2023 STMicroelectronics. All rights reserved.  
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h5xx
+  * @{
+  */
+
+#ifndef PARTITION_STM32H5XX_H
+#define PARTITION_STM32H5XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Secure_configuration_section
+  * @{
+  */
+
+#if defined(STM32H573xx)
+  #include "partition_stm32h573xx.h"
+#elif defined(STM32H563xx)
+  #include "partition_stm32h563xx.h"
+#elif defined(STM32H562xx)
+  #include "partition_stm32h562xx.h"
+#elif defined(STM32H533xx)
+  #include "partition_stm32h533xx.h"
+#elif defined(STM32H523xx)
+  #include "partition_stm32h523xx.h"
+#else
+  #error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)"
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* PARTITION_STM32H5XX_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h

@@ -0,0 +1,245 @@
+/**
+  ******************************************************************************
+  * @file    stm32h5xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H5xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32H5xx device used in the target application
+  *              - To use or not the peripheral<EFBFBD>s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral<EFBFBD>s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h5xx
+  * @{
+  */
+
+#ifndef STM32H5xx_H
+#define STM32H5xx_H
+#include "math.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32H5)
+#define STM32H5
+#endif /* STM32H5 */
+
+/* Uncomment the line below according to the target STM32H5 device used in your
+   application
+  */
+
+#if !defined (STM32H573xx)  && !defined (STM32H563xx) \
+    && !defined (STM32H562xx) && !defined (STM32H503xx) \
+    && !defined (STM32H533xx) && !defined (STM32H523xx)
+  /* #define STM32H573xx  */   /*!< STM32H5753xx Devices  */
+  /* #define STM32H563xx  */   /*!< STM32H563xx Devices   */
+  /* #define STM32H562xx  */   /*!< STM32H562xx Devices   */
+  /* #define STM32H503xx  */   /*!< STM32H503xx Devices   */
+  /* #define STM32H533xx  */   /*!< STM32H533xx Devices   */
+  /* #define STM32H523xx  */   /*!< STM32H523xx Devices   */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number 1.2.0
+  */
+#define __STM32H5_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32H5_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
+#define __STM32H5_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32H5_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32H5_CMSIS_VERSION        ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\
+                                       |(__STM32H5_CMSIS_VERSION_SUB1 << 16U)\
+                                       |(__STM32H5_CMSIS_VERSION_SUB2 << 8U )\
+                                       |(__STM32H5_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32H573xx)
+  #include "stm32h573xx.h"
+#elif defined(STM32H563xx)
+  #include "stm32h563xx.h"
+#elif defined(STM32H562xx)
+  #include "stm32h562xx.h"
+#elif defined(STM32H503xx)
+  #include "stm32h503xx.h"
+#elif defined(STM32H523xx)
+  #include "stm32h523xx.h"
+#elif defined(STM32H533xx)
+  #include "stm32h533xx.h"
+#else
+  #error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)"
+#endif
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT)                             \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
+  do {                                                                     \
+    uint32_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
+  } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT)                            \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
+  do {                                                                     \
+    uint16_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
+  } while(0)
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32h5xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H5xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h

@@ -0,0 +1,107 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h5xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M33 Device System Source File for STM32H5xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h5xx_system
+  * @{
+  */
+
+#ifndef SYSTEM_STM32H5XX_H
+#define SYSTEM_STM32H5XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32H5xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+   */
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32H5xx_System_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief Setup the microcontroller system.
+  *
+  * Initialize the System and update the SystemCoreClock variable.
+  */
+extern void SystemInit (void);
+
+
+/**
+  * @brief  Update SystemCoreClock variable.
+  *
+  * Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+  */
+extern void SystemCoreClockUpdate (void);
+
+
+/**
+  * @brief Update SystemCoreClock variable from secure application and return its value
+  *        when security is implemented in the system (Non-secure callable function).
+  *
+  * Returns the SystemCoreClock value with current core Clock retrieved from cpu registers.
+  */
+extern uint32_t SECURE_SystemCoreClockUpdate(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_STM32H5XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.txt

@@ -0,0 +1,6 @@
+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the Apache-2.0 license shall apply. 
+You may obtain a copy of the Apache-2.0 at:
+https://opensource.org/licenses/Apache-2.0

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/README.md

@@ -0,0 +1,36 @@
+# STM32CubeH5 CMSIS Device MCU Component
+
+## Overview
+
+**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
+
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
+   * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+   * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
+   * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
+   * A consistent set of middleware libraries such as FileX, USBX, TheadX ...
+   * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
+
+Two models of publication are proposed for the STM32Cube embedded software:
+   * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
+   * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
+   
+## Description
+
+This **cmsis_device_h5** MCU component repo is one element of the STM32CubeH5 MCU embedded software package, providing the **cmsis device** part.
+
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_h5/blob/main/Release_Notes.html).
+
+## Compatibility information
+
+It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeH5/blob/main/Release_Notes.html) release note.
+
+The full **STM32CubeH5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH5).
+
+## Troubleshooting
+
+If you have any issue with the software content of this repository, you can file an issue [here](https://github.com/STMicroelectronics/cmsis_device_h5/issues/new).
+
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html

@@ -0,0 +1,77 @@
+<!DOCTYPE html>
+<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
+<head>
+  <meta charset="utf-8" />
+  <meta name="generator" content="pandoc" />
+  <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
+  <title>Release Notes for STM32H5xx CMSIS</title>
+  <style type="text/css">
+      code{white-space: pre-wrap;}
+      span.smallcaps{font-variant: small-caps;}
+      span.underline{text-decoration: underline;}
+      div.column{display: inline-block; vertical-align: top; width: 50%;}
+  </style>
+  <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
+  <!--[if lt IE 9]>
+    <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
+  <![endif]-->
+  <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
+</head>
+<body>
+<div class="row">
+<div class="col-sm-12 col-lg-4">
+<center>
+<h1 id="release-notes-for-stm32h5xx-cmsis">Release Notes for <mark> STM32H5xx CMSIS </mark></h1>
+<p>Copyright © 2023 STMicroelectronics<br />
+</p>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
+</center>
+</div>
+<div class="col-sm-12 col-lg-8">
+<h1 id="update-history"><strong>Update History</strong></h1>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3" Checked aria-hidden="true"> <label for="collapse-section3" checked aria-hidden="true"><strong>V1.2.0 / 09-February-2024</strong></label>
+<div>
+<h2 id="main-changes">Main Changes</h2>
+<ul>
+<li>First official release of STM32H5xx CMSIS drivers to support <strong>STM32H533xx and STM32H523xx</strong> devices</li>
+<li>Add bit definition for I3C_BCR register</li>
+<li>Add IS_DMA_PFREQ_INSTANCE macro</li>
+<li>Fix Ticket 163445: [FLASH][CMSIS] Wrong EDATA_STRT start sectors mask size</li>
+<li>Fix Ticket 163090: [FOSS-Audit] Licensing issues: Missing copyright from Arm Limited and original header not retained</li>
+<li>Update CubeIDE projects to be compliant with GCC12 diagnostics</li>
+<li>Fix Ticket 165407: [H5][GTZC][CMSIS]: wrong Flash illegal access bit definition</li>
+<li>Fix Ticket 147880: [STM32H5]|FLASH_HAL] Some option bytes are missing in stm32h5xx_hal_flash_ex.h</li>
+<li>Set FMC_SDCMR_MODE_2 bit field definition to 0x4</li>
+<li>Fix Ticket 162902: [GitHub] Wrong declaration of g_pfnVectors size in gcc/startup files</li>
+<li>Fix: Ticket 167776: [CMSIS] Missing TIM option register related definitions</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" checked aria-hidden="true"><strong>V1.1.0 / 07-June-2023</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>Add DUA addresses constants definitions for STM32H573xx devices only</li>
+<li>Fix wrong definition of IS_TIM_CLOCKSOURCE_TIX_INSTANCE &amp; IS_TIM_TISEL_INSTANCE macros</li>
+<li>Update possible values of the ATCKSEL field of TAMP active tamper control register and update the mask accordingly.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 10-February-2023</strong></label>
+<div>
+<h2 id="main-changes-2">Main Changes</h2>
+<ul>
+<li>First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals)</li>
+</ul>
+</div>
+</div>
+</div>
+</div>
+<footer class="sticky">
+For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>
+</footer>
+</body>
+</html>

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/arm/startup_stm32h503xx.s

@@ -0,0 +1,479 @@
+;*******************************************************************************
+;* File Name          : startup_stm32h503xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H503xx Non Crypto devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                     ; Top of Stack
+                DCD     Reset_Handler                    ; Reset Handler
+                DCD     NMI_Handler                      ; NMI Handler
+                DCD     HardFault_Handler                ; Hard Fault Handler
+                DCD     MemManage_Handler                ; MPU Fault Handler
+                DCD     BusFault_Handler                 ; Bus Fault Handler
+                DCD     UsageFault_Handler               ; Usage Fault Handler
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     SVC_Handler                      ; SVCall Handler
+                DCD     DebugMon_Handler                 ; Debug Monitor Handler
+                DCD     0                                ; Reserved
+                DCD     PendSV_Handler                   ; PendSV Handler
+                DCD     SysTick_Handler                  ; SysTick Handler
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                  ; Window WatchDog
+                DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+                DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+                DCD     0                                ; Reserved
+                DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+                DCD     RAMCFG_IRQHandler                ; RAMCFG global
+                DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+                DCD     0                                ; Reserved
+                DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+                DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+                DCD     0                                ; Reserved
+                DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+                DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+                DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+                DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+                DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+                DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+                DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+                DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+                DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+                DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+                DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+                DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+                DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+                DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+                DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+                DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+                DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+                DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+                DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+                DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+                DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+                DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+                DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+                DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+                DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+                DCD     0                                ; Reserved
+                DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+                DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+                DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+                DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+                DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+                DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+                DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+                DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+                DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+                DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+                DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+                DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+                DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+                DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+                DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+                DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+                DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+                DCD     USART1_IRQHandler                ; USART1 global interrupt
+                DCD     USART2_IRQHandler                ; USART2 global interrupt
+                DCD     USART3_IRQHandler                ; USART3 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+                DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+                DCD     CRS_IRQHandler                   ; CRS global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+                DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+                DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+                DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+                DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+                DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+                DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+                DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     FPU_IRQHandler                   ; FPU global interrupt
+                DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     DTS_IRQHandler                   ; DTS global interrupt
+                DCD     RNG_IRQHandler                   ; RNG global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     HASH_IRQHandler                  ; HASH global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+                DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     I3C2_EV_IRQHandler               ; I3C2 Event interrupt
+                DCD     I3C2_ER_IRQHandler               ; I3C2 Error interrupt
+                DCD     COMP1_IRQHandler                 ; COMP1 global interrupt
+
+
+__Vectors_End
+
+__Vectors_Size  EQU    __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SecureFault_Handler\
+                PROC
+                EXPORT  SecureFault_Handler       [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                  [WEAK]
+                EXPORT  PVD_AVD_IRQHandler               [WEAK]
+                EXPORT  RTC_IRQHandler                   [WEAK]
+                EXPORT  TAMP_IRQHandler                  [WEAK]
+                EXPORT  RAMCFG_IRQHandler                [WEAK]
+                EXPORT  FLASH_IRQHandler                 [WEAK]
+                EXPORT  GTZC_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                   [WEAK]
+                EXPORT  EXTI0_IRQHandler                 [WEAK]
+                EXPORT  EXTI1_IRQHandler                 [WEAK]
+                EXPORT  EXTI2_IRQHandler                 [WEAK]
+                EXPORT  EXTI3_IRQHandler                 [WEAK]
+                EXPORT  EXTI4_IRQHandler                 [WEAK]
+                EXPORT  EXTI5_IRQHandler                 [WEAK]
+                EXPORT  EXTI6_IRQHandler                 [WEAK]
+                EXPORT  EXTI7_IRQHandler                 [WEAK]
+                EXPORT  EXTI8_IRQHandler                 [WEAK]
+                EXPORT  EXTI9_IRQHandler                 [WEAK]
+                EXPORT  EXTI10_IRQHandler                [WEAK]
+                EXPORT  EXTI11_IRQHandler                [WEAK]
+                EXPORT  EXTI12_IRQHandler                [WEAK]
+                EXPORT  EXTI13_IRQHandler                [WEAK]
+                EXPORT  EXTI14_IRQHandler                [WEAK]
+                EXPORT  EXTI15_IRQHandler                [WEAK]
+                EXPORT  GPDMA1_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel7_IRQHandler       [WEAK]
+                EXPORT  IWDG_IRQHandler                  [WEAK]
+                EXPORT  ADC1_IRQHandler                  [WEAK]
+                EXPORT  DAC1_IRQHandler                  [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler            [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler            [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM1_UP_IRQHandler               [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM1_CC_IRQHandler               [WEAK]
+                EXPORT  TIM2_IRQHandler                  [WEAK]
+                EXPORT  TIM3_IRQHandler                  [WEAK]
+                EXPORT  TIM6_IRQHandler                  [WEAK]
+                EXPORT  TIM7_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler               [WEAK]
+                EXPORT  I2C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C2_EV_IRQHandler               [WEAK]
+                EXPORT  I2C2_ER_IRQHandler               [WEAK]
+                EXPORT  SPI1_IRQHandler                  [WEAK]
+                EXPORT  SPI2_IRQHandler                  [WEAK]
+                EXPORT  SPI3_IRQHandler                  [WEAK]
+                EXPORT  USART1_IRQHandler                [WEAK]
+                EXPORT  USART2_IRQHandler                [WEAK]
+                EXPORT  USART3_IRQHandler                [WEAK]
+                EXPORT  LPUART1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                [WEAK]
+                EXPORT  LPTIM2_IRQHandler                [WEAK]
+                EXPORT  USB_DRD_FS_IRQHandler            [WEAK]
+                EXPORT  CRS_IRQHandler                   [WEAK]
+                EXPORT  GPDMA2_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel7_IRQHandler       [WEAK]
+                EXPORT  COMP1_IRQHandler                 [WEAK]
+                EXPORT  I3C2_EV_IRQHandler               [WEAK]
+                EXPORT  I3C2_ER_IRQHandler               [WEAK]
+                EXPORT  FPU_IRQHandler                   [WEAK]
+                EXPORT  ICACHE_IRQHandler                [WEAK]
+                EXPORT  DTS_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                   [WEAK]
+                EXPORT  HASH_IRQHandler                  [WEAK]
+                EXPORT  I3C1_EV_IRQHandler               [WEAK]
+                EXPORT  I3C1_ER_IRQHandler               [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+RTC_IRQHandler
+TAMP_IRQHandler
+RAMCFG_IRQHandler
+FLASH_IRQHandler
+GTZC_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+EXTI8_IRQHandler
+EXTI9_IRQHandler
+EXTI10_IRQHandler
+EXTI11_IRQHandler
+EXTI12_IRQHandler
+EXTI13_IRQHandler
+EXTI14_IRQHandler
+EXTI15_IRQHandler
+GPDMA1_Channel0_IRQHandler
+GPDMA1_Channel1_IRQHandler
+GPDMA1_Channel2_IRQHandler
+GPDMA1_Channel3_IRQHandler
+GPDMA1_Channel4_IRQHandler
+GPDMA1_Channel5_IRQHandler
+GPDMA1_Channel6_IRQHandler
+GPDMA1_Channel7_IRQHandler
+IWDG_IRQHandler
+ADC1_IRQHandler
+DAC1_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+SPI3_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+USB_DRD_FS_IRQHandler
+CRS_IRQHandler
+GPDMA2_Channel0_IRQHandler
+GPDMA2_Channel1_IRQHandler
+GPDMA2_Channel2_IRQHandler
+GPDMA2_Channel3_IRQHandler
+GPDMA2_Channel4_IRQHandler
+GPDMA2_Channel5_IRQHandler
+GPDMA2_Channel6_IRQHandler
+GPDMA2_Channel7_IRQHandler
+COMP1_IRQHandler
+I3C2_EV_IRQHandler
+I3C2_ER_IRQHandler
+FPU_IRQHandler
+ICACHE_IRQHandler
+DTS_IRQHandler
+RNG_IRQHandler
+HASH_IRQHandler
+I3C1_EV_IRQHandler
+I3C1_ER_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END
+

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/arm/startup_stm32h523xx.s

@@ -0,0 +1,528 @@
+;*******************************************************************************
+;* File Name          : startup_stm32h523xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H523xx Non Crypto devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                     ; Top of Stack
+                DCD     Reset_Handler                    ; Reset Handler
+                DCD     NMI_Handler                      ; NMI Handler
+                DCD     HardFault_Handler                ; Hard Fault Handler
+                DCD     MemManage_Handler                ; MPU Fault Handler
+                DCD     BusFault_Handler                 ; Bus Fault Handler
+                DCD     UsageFault_Handler               ; Usage Fault Handler
+                DCD     SecureFault_Handler              ; Secure Fault Handler
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     SVC_Handler                      ; SVCall Handler
+                DCD     DebugMon_Handler                 ; Debug Monitor Handler
+                DCD     0                                ; Reserved
+                DCD     PendSV_Handler                   ; PendSV Handler
+                DCD     SysTick_Handler                  ; SysTick Handler
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                  ; Window WatchDog
+                DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+                DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+                DCD     RTC_S_IRQHandler                 ; RTC secure interrupt
+                DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+                DCD     RAMCFG_IRQHandler                ; RAMCFG global
+                DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+                DCD     FLASH_S_IRQHandler               ; FLASH secure global interrupt
+                DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+                DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+                DCD     RCC_S_IRQHandler                 ; RCC secure global interrupt
+                DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+                DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+                DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+                DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+                DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+                DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+                DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+                DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+                DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+                DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+                DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+                DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+                DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+                DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+                DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+                DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+                DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+                DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+                DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+                DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+                DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+                DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+                DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+                DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+                DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+                DCD     0                                ; Reserved
+                DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+                DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+                DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+                DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+                DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+                DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+                DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+                DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+                DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+                DCD     TIM4_IRQHandler                  ; TIM4 global interrupt
+                DCD     TIM5_IRQHandler                  ; TIM5 global interrupt
+                DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+                DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+                DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+                DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+                DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+                DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+                DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+                DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+                DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+                DCD     USART1_IRQHandler                ; USART1 global interrupt
+                DCD     USART2_IRQHandler                ; USART2 global interrupt
+                DCD     USART3_IRQHandler                ; USART3 global interrupt
+                DCD     UART4_IRQHandler                 ; UART4 global interrupt
+                DCD     UART5_IRQHandler                 ; UART5 global interrupt
+                DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+                DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+                DCD     TIM8_BRK_IRQHandler              ; TIM8 Break interrupt
+                DCD     TIM8_UP_IRQHandler               ; TIM8 Update interrupt
+                DCD     TIM8_TRG_COM_IRQHandler          ; TIM8 Trigger and Commutation interrupt
+                DCD     TIM8_CC_IRQHandler               ; TIM8 Capture Compare interrupt
+                DCD     ADC2_IRQHandler                  ; ADC2 global interrupt
+                DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+                DCD     TIM15_IRQHandler                 ; TIM15 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+                DCD     CRS_IRQHandler                   ; CRS global interrupt
+                DCD     UCPD1_IRQHandler                 ; UCPD1 global interrupt
+                DCD     FMC_IRQHandler                   ; FMC global interrupt
+                DCD     OCTOSPI1_IRQHandler              ; OctoSPI1 global interrupt
+                DCD     SDMMC1_IRQHandler                ; SDMMC1 global interrupt
+                DCD     I2C3_EV_IRQHandler               ; I2C2 Event interrupt
+                DCD     I2C3_ER_IRQHandler               ; I2C2 Error interrupt
+                DCD     SPI4_IRQHandler                  ; SPI4 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     USART6_IRQHandler                ; USART6 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+                DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+                DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+                DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+                DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+                DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+                DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+                DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     FPU_IRQHandler                   ; FPU global interrupt
+                DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+                DCD     DCACHE1_IRQHandler               ; DCACHE1 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     DCMI_PSSI_IRQHandler             ; DCMI PSSI global interrupt
+                DCD     FDCAN2_IT0_IRQHandler            ; FDCAN2 interrupt 0
+                DCD     FDCAN2_IT1_IRQHandler            ; FDCAN2 interrupt 1
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     DTS_IRQHandler                   ; DTS global interrupt
+                DCD     RNG_IRQHandler                   ; RNG global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     HASH_IRQHandler                  ; HASH global interrupt
+                DCD     0                                ; Reserved
+                DCD     CEC_IRQHandler                   ; CEC global interrupt
+                DCD     TIM12_IRQHandler                 ; TIM12 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+                DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     I3C2_EV_IRQHandler               ; I3C2 Event interrupt
+                DCD     I3C2_ER_IRQHandler               ; I3C2 Error interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU    __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SecureFault_Handler\
+                PROC
+                EXPORT  SecureFault_Handler       [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                  [WEAK]
+                EXPORT  PVD_AVD_IRQHandler               [WEAK]
+                EXPORT  RTC_IRQHandler                   [WEAK]
+                EXPORT  RTC_S_IRQHandler                 [WEAK]
+                EXPORT  TAMP_IRQHandler                  [WEAK]
+                EXPORT  RAMCFG_IRQHandler                [WEAK]
+                EXPORT  FLASH_IRQHandler                 [WEAK]
+                EXPORT  FLASH_S_IRQHandler               [WEAK]
+                EXPORT  GTZC_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                   [WEAK]
+                EXPORT  RCC_S_IRQHandler                 [WEAK]
+                EXPORT  EXTI0_IRQHandler                 [WEAK]
+                EXPORT  EXTI1_IRQHandler                 [WEAK]
+                EXPORT  EXTI2_IRQHandler                 [WEAK]
+                EXPORT  EXTI3_IRQHandler                 [WEAK]
+                EXPORT  EXTI4_IRQHandler                 [WEAK]
+                EXPORT  EXTI5_IRQHandler                 [WEAK]
+                EXPORT  EXTI6_IRQHandler                 [WEAK]
+                EXPORT  EXTI7_IRQHandler                 [WEAK]
+                EXPORT  EXTI8_IRQHandler                 [WEAK]
+                EXPORT  EXTI9_IRQHandler                 [WEAK]
+                EXPORT  EXTI10_IRQHandler                [WEAK]
+                EXPORT  EXTI11_IRQHandler                [WEAK]
+                EXPORT  EXTI12_IRQHandler                [WEAK]
+                EXPORT  EXTI13_IRQHandler                [WEAK]
+                EXPORT  EXTI14_IRQHandler                [WEAK]
+                EXPORT  EXTI15_IRQHandler                [WEAK]
+                EXPORT  GPDMA1_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel7_IRQHandler       [WEAK]
+                EXPORT  IWDG_IRQHandler                  [WEAK]
+                EXPORT  ADC1_IRQHandler                  [WEAK]
+                EXPORT  DAC1_IRQHandler                  [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler            [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler            [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM1_UP_IRQHandler               [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM1_CC_IRQHandler               [WEAK]
+                EXPORT  TIM2_IRQHandler                  [WEAK]
+                EXPORT  TIM3_IRQHandler                  [WEAK]
+                EXPORT  TIM4_IRQHandler                  [WEAK]
+                EXPORT  TIM5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_IRQHandler                  [WEAK]
+                EXPORT  TIM7_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler               [WEAK]
+                EXPORT  I2C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C2_EV_IRQHandler               [WEAK]
+                EXPORT  I2C2_ER_IRQHandler               [WEAK]
+                EXPORT  SPI1_IRQHandler                  [WEAK]
+                EXPORT  SPI2_IRQHandler                  [WEAK]
+                EXPORT  SPI3_IRQHandler                  [WEAK]
+                EXPORT  USART1_IRQHandler                [WEAK]
+                EXPORT  USART2_IRQHandler                [WEAK]
+                EXPORT  USART3_IRQHandler                [WEAK]
+                EXPORT  UART4_IRQHandler                 [WEAK]
+                EXPORT  UART5_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM8_UP_IRQHandler               [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM8_CC_IRQHandler               [WEAK]
+                EXPORT  ADC2_IRQHandler                  [WEAK]
+                EXPORT  LPTIM2_IRQHandler                [WEAK]
+                EXPORT  TIM15_IRQHandler                 [WEAK]
+                EXPORT  USB_DRD_FS_IRQHandler            [WEAK]
+                EXPORT  CRS_IRQHandler                   [WEAK]
+                EXPORT  UCPD1_IRQHandler                 [WEAK]
+                EXPORT  FMC_IRQHandler                   [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler              [WEAK]
+                EXPORT  SDMMC1_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler               [WEAK]
+                EXPORT  I2C3_ER_IRQHandler               [WEAK]
+                EXPORT  SPI4_IRQHandler                  [WEAK]
+                EXPORT  USART6_IRQHandler                [WEAK]
+                EXPORT  GPDMA2_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel7_IRQHandler       [WEAK]
+                EXPORT  FPU_IRQHandler                   [WEAK]
+                EXPORT  ICACHE_IRQHandler                [WEAK]
+                EXPORT  DCACHE1_IRQHandler               [WEAK]
+                EXPORT  DCMI_PSSI_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT0_IRQHandler            [WEAK]
+                EXPORT  FDCAN2_IT1_IRQHandler            [WEAK]
+                EXPORT  DTS_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                   [WEAK]
+                EXPORT  HASH_IRQHandler                  [WEAK]
+                EXPORT  CEC_IRQHandler                   [WEAK]
+                EXPORT  TIM12_IRQHandler                 [WEAK]
+                EXPORT  I3C1_EV_IRQHandler               [WEAK]
+                EXPORT  I3C1_ER_IRQHandler               [WEAK]
+                EXPORT  I3C2_EV_IRQHandler               [WEAK]
+                EXPORT  I3C2_ER_IRQHandler               [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+RTC_IRQHandler
+RTC_S_IRQHandler
+TAMP_IRQHandler
+RAMCFG_IRQHandler
+FLASH_IRQHandler
+FLASH_S_IRQHandler
+GTZC_IRQHandler
+RCC_IRQHandler
+RCC_S_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+EXTI8_IRQHandler
+EXTI9_IRQHandler
+EXTI10_IRQHandler
+EXTI11_IRQHandler
+EXTI12_IRQHandler
+EXTI13_IRQHandler
+EXTI14_IRQHandler
+EXTI15_IRQHandler
+GPDMA1_Channel0_IRQHandler
+GPDMA1_Channel1_IRQHandler
+GPDMA1_Channel2_IRQHandler
+GPDMA1_Channel3_IRQHandler
+GPDMA1_Channel4_IRQHandler
+GPDMA1_Channel5_IRQHandler
+GPDMA1_Channel6_IRQHandler
+GPDMA1_Channel7_IRQHandler
+IWDG_IRQHandler
+ADC1_IRQHandler
+DAC1_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+SPI3_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC2_IRQHandler
+LPTIM2_IRQHandler
+TIM15_IRQHandler
+USB_DRD_FS_IRQHandler
+CRS_IRQHandler
+UCPD1_IRQHandler
+FMC_IRQHandler
+OCTOSPI1_IRQHandler
+SDMMC1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI4_IRQHandler
+USART6_IRQHandler
+GPDMA2_Channel0_IRQHandler
+GPDMA2_Channel1_IRQHandler
+GPDMA2_Channel2_IRQHandler
+GPDMA2_Channel3_IRQHandler
+GPDMA2_Channel4_IRQHandler
+GPDMA2_Channel5_IRQHandler
+GPDMA2_Channel6_IRQHandler
+GPDMA2_Channel7_IRQHandler
+FPU_IRQHandler
+ICACHE_IRQHandler
+DCACHE1_IRQHandler
+DCMI_PSSI_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN2_IT1_IRQHandler
+DTS_IRQHandler
+RNG_IRQHandler
+HASH_IRQHandler
+CEC_IRQHandler
+TIM12_IRQHandler
+I3C1_EV_IRQHandler
+I3C1_ER_IRQHandler
+I3C2_EV_IRQHandler
+I3C2_ER_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/arm/startup_stm32h533xx.s

@@ -0,0 +1,536 @@
+;*******************************************************************************
+;* File Name          : startup_stm32h533xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H533xx Crypto devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                     ; Top of Stack
+                DCD     Reset_Handler                    ; Reset Handler
+                DCD     NMI_Handler                      ; NMI Handler
+                DCD     HardFault_Handler                ; Hard Fault Handler
+                DCD     MemManage_Handler                ; MPU Fault Handler
+                DCD     BusFault_Handler                 ; Bus Fault Handler
+                DCD     UsageFault_Handler               ; Usage Fault Handler
+                DCD     SecureFault_Handler              ; Secure Fault Handler
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     SVC_Handler                      ; SVCall Handler
+                DCD     DebugMon_Handler                 ; Debug Monitor Handler
+                DCD     0                                ; Reserved
+                DCD     PendSV_Handler                   ; PendSV Handler
+                DCD     SysTick_Handler                  ; SysTick Handler
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                  ; Window WatchDog
+                DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+                DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+                DCD     RTC_S_IRQHandler                 ; RTC secure interrupt
+                DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+                DCD     RAMCFG_IRQHandler                ; RAMCFG global
+                DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+                DCD     FLASH_S_IRQHandler               ; FLASH secure global interrupt
+                DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+                DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+                DCD     RCC_S_IRQHandler                 ; RCC secure global interrupt
+                DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+                DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+                DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+                DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+                DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+                DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+                DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+                DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+                DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+                DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+                DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+                DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+                DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+                DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+                DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+                DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+                DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+                DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+                DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+                DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+                DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+                DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+                DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+                DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+                DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+                DCD     SAES_IRQHandler                  ; SAES global interrupt
+                DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+                DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+                DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+                DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+                DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+                DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+                DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+                DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+                DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+                DCD     TIM4_IRQHandler                  ; TIM4 global interrupt
+                DCD     TIM5_IRQHandler                  ; TIM5 global interrupt
+                DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+                DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+                DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+                DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+                DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+                DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+                DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+                DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+                DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+                DCD     USART1_IRQHandler                ; USART1 global interrupt
+                DCD     USART2_IRQHandler                ; USART2 global interrupt
+                DCD     USART3_IRQHandler                ; USART3 global interrupt
+                DCD     UART4_IRQHandler                 ; UART4 global interrupt
+                DCD     UART5_IRQHandler                 ; UART5 global interrupt
+                DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+                DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+                DCD     TIM8_BRK_IRQHandler              ; TIM8 Break interrupt
+                DCD     TIM8_UP_IRQHandler               ; TIM8 Update interrupt
+                DCD     TIM8_TRG_COM_IRQHandler          ; TIM8 Trigger and Commutation interrupt
+                DCD     TIM8_CC_IRQHandler               ; TIM8 Capture Compare interrupt
+                DCD     ADC2_IRQHandler                  ; ADC2 global interrupt
+                DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+                DCD     TIM15_IRQHandler                 ; TIM15 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+                DCD     CRS_IRQHandler                   ; CRS global interrupt
+                DCD     UCPD1_IRQHandler                 ; UCPD1 global interrupt
+                DCD     FMC_IRQHandler                   ; FMC global interrupt
+                DCD     OCTOSPI1_IRQHandler              ; OctoSPI1 global interrupt
+                DCD     SDMMC1_IRQHandler                ; SDMMC1 global interrupt
+                DCD     I2C3_EV_IRQHandler               ; I2C2 Event interrupt
+                DCD     I2C3_ER_IRQHandler               ; I2C2 Error interrupt
+                DCD     SPI4_IRQHandler                  ; SPI4 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     USART6_IRQHandler                ; USART6 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+                DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+                DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+                DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+                DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+                DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+                DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+                DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     FPU_IRQHandler                   ; FPU global interrupt
+                DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+                DCD     DCACHE1_IRQHandler               ; DCACHE1 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     DCMI_PSSI_IRQHandler             ; DCMI PSSI global interrupt
+                DCD     FDCAN2_IT0_IRQHandler            ; FDCAN2 interrupt 0
+                DCD     FDCAN2_IT1_IRQHandler            ; FDCAN2 interrupt 1
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     DTS_IRQHandler                   ; DTS global interrupt
+                DCD     RNG_IRQHandler                   ; RNG global interrupt
+                DCD     OTFDEC1_IRQHandler               ; OTFDEC1 global interrupt
+                DCD     AES_IRQHandler                   ; AES global interrupt
+                DCD     HASH_IRQHandler                  ; HASH global interrupt
+                DCD     PKA_IRQHandler                   ; PKA global interrupt
+                DCD     CEC_IRQHandler                   ; CEC global interrupt
+                DCD     TIM12_IRQHandler                 ; TIM12 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+                DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     I3C2_EV_IRQHandler               ; I3C2 Event interrupt
+                DCD     I3C2_ER_IRQHandler               ; I3C2 Error interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU    __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SecureFault_Handler\
+                PROC
+                EXPORT  SecureFault_Handler       [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                  [WEAK]
+                EXPORT  PVD_AVD_IRQHandler               [WEAK]
+                EXPORT  RTC_IRQHandler                   [WEAK]
+                EXPORT  RTC_S_IRQHandler                 [WEAK]
+                EXPORT  TAMP_IRQHandler                  [WEAK]
+                EXPORT  RAMCFG_IRQHandler                [WEAK]
+                EXPORT  FLASH_IRQHandler                 [WEAK]
+                EXPORT  FLASH_S_IRQHandler               [WEAK]
+                EXPORT  GTZC_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                   [WEAK]
+                EXPORT  RCC_S_IRQHandler                 [WEAK]
+                EXPORT  EXTI0_IRQHandler                 [WEAK]
+                EXPORT  EXTI1_IRQHandler                 [WEAK]
+                EXPORT  EXTI2_IRQHandler                 [WEAK]
+                EXPORT  EXTI3_IRQHandler                 [WEAK]
+                EXPORT  EXTI4_IRQHandler                 [WEAK]
+                EXPORT  EXTI5_IRQHandler                 [WEAK]
+                EXPORT  EXTI6_IRQHandler                 [WEAK]
+                EXPORT  EXTI7_IRQHandler                 [WEAK]
+                EXPORT  EXTI8_IRQHandler                 [WEAK]
+                EXPORT  EXTI9_IRQHandler                 [WEAK]
+                EXPORT  EXTI10_IRQHandler                [WEAK]
+                EXPORT  EXTI11_IRQHandler                [WEAK]
+                EXPORT  EXTI12_IRQHandler                [WEAK]
+                EXPORT  EXTI13_IRQHandler                [WEAK]
+                EXPORT  EXTI14_IRQHandler                [WEAK]
+                EXPORT  EXTI15_IRQHandler                [WEAK]
+                EXPORT  GPDMA1_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel7_IRQHandler       [WEAK]
+                EXPORT  IWDG_IRQHandler                  [WEAK]
+                EXPORT  SAES_IRQHandler                  [WEAK]
+                EXPORT  ADC1_IRQHandler                  [WEAK]
+                EXPORT  DAC1_IRQHandler                  [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler            [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler            [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM1_UP_IRQHandler               [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM1_CC_IRQHandler               [WEAK]
+                EXPORT  TIM2_IRQHandler                  [WEAK]
+                EXPORT  TIM3_IRQHandler                  [WEAK]
+                EXPORT  TIM4_IRQHandler                  [WEAK]
+                EXPORT  TIM5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_IRQHandler                  [WEAK]
+                EXPORT  TIM7_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler               [WEAK]
+                EXPORT  I2C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C2_EV_IRQHandler               [WEAK]
+                EXPORT  I2C2_ER_IRQHandler               [WEAK]
+                EXPORT  SPI1_IRQHandler                  [WEAK]
+                EXPORT  SPI2_IRQHandler                  [WEAK]
+                EXPORT  SPI3_IRQHandler                  [WEAK]
+                EXPORT  USART1_IRQHandler                [WEAK]
+                EXPORT  USART2_IRQHandler                [WEAK]
+                EXPORT  USART3_IRQHandler                [WEAK]
+                EXPORT  UART4_IRQHandler                 [WEAK]
+                EXPORT  UART5_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM8_UP_IRQHandler               [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM8_CC_IRQHandler               [WEAK]
+                EXPORT  ADC2_IRQHandler                  [WEAK]
+                EXPORT  LPTIM2_IRQHandler                [WEAK]
+                EXPORT  TIM15_IRQHandler                 [WEAK]
+                EXPORT  USB_DRD_FS_IRQHandler            [WEAK]
+                EXPORT  CRS_IRQHandler                   [WEAK]
+                EXPORT  UCPD1_IRQHandler                 [WEAK]
+                EXPORT  FMC_IRQHandler                   [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler              [WEAK]
+                EXPORT  SDMMC1_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler               [WEAK]
+                EXPORT  I2C3_ER_IRQHandler               [WEAK]
+                EXPORT  SPI4_IRQHandler                  [WEAK]
+                EXPORT  USART6_IRQHandler                [WEAK]
+                EXPORT  GPDMA2_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel7_IRQHandler       [WEAK]
+                EXPORT  FPU_IRQHandler                   [WEAK]
+                EXPORT  ICACHE_IRQHandler                [WEAK]
+                EXPORT  DCACHE1_IRQHandler               [WEAK]
+                EXPORT  DCMI_PSSI_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT0_IRQHandler            [WEAK]
+                EXPORT  FDCAN2_IT1_IRQHandler            [WEAK]
+                EXPORT  DTS_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                   [WEAK]
+                EXPORT  OTFDEC1_IRQHandler               [WEAK]
+                EXPORT  AES_IRQHandler                   [WEAK]
+                EXPORT  HASH_IRQHandler                  [WEAK]
+                EXPORT  PKA_IRQHandler                   [WEAK]
+                EXPORT  CEC_IRQHandler                   [WEAK]
+                EXPORT  TIM12_IRQHandler                 [WEAK]
+                EXPORT  I3C1_EV_IRQHandler               [WEAK]
+                EXPORT  I3C1_ER_IRQHandler               [WEAK]
+                EXPORT  I3C2_EV_IRQHandler               [WEAK]
+                EXPORT  I3C2_ER_IRQHandler               [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+RTC_IRQHandler
+RTC_S_IRQHandler
+TAMP_IRQHandler
+RAMCFG_IRQHandler
+FLASH_IRQHandler
+FLASH_S_IRQHandler
+GTZC_IRQHandler
+RCC_IRQHandler
+RCC_S_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+EXTI8_IRQHandler
+EXTI9_IRQHandler
+EXTI10_IRQHandler
+EXTI11_IRQHandler
+EXTI12_IRQHandler
+EXTI13_IRQHandler
+EXTI14_IRQHandler
+EXTI15_IRQHandler
+GPDMA1_Channel0_IRQHandler
+GPDMA1_Channel1_IRQHandler
+GPDMA1_Channel2_IRQHandler
+GPDMA1_Channel3_IRQHandler
+GPDMA1_Channel4_IRQHandler
+GPDMA1_Channel5_IRQHandler
+GPDMA1_Channel6_IRQHandler
+GPDMA1_Channel7_IRQHandler
+IWDG_IRQHandler
+SAES_IRQHandler
+ADC1_IRQHandler
+DAC1_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+SPI3_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC2_IRQHandler
+LPTIM2_IRQHandler
+TIM15_IRQHandler
+USB_DRD_FS_IRQHandler
+CRS_IRQHandler
+UCPD1_IRQHandler
+FMC_IRQHandler
+OCTOSPI1_IRQHandler
+SDMMC1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI4_IRQHandler
+USART6_IRQHandler
+GPDMA2_Channel0_IRQHandler
+GPDMA2_Channel1_IRQHandler
+GPDMA2_Channel2_IRQHandler
+GPDMA2_Channel3_IRQHandler
+GPDMA2_Channel4_IRQHandler
+GPDMA2_Channel5_IRQHandler
+GPDMA2_Channel6_IRQHandler
+GPDMA2_Channel7_IRQHandler
+FPU_IRQHandler
+ICACHE_IRQHandler
+DCACHE1_IRQHandler
+DCMI_PSSI_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN2_IT1_IRQHandler
+DTS_IRQHandler
+RNG_IRQHandler
+OTFDEC1_IRQHandler
+AES_IRQHandler
+HASH_IRQHandler
+PKA_IRQHandler
+CEC_IRQHandler
+TIM12_IRQHandler
+I3C1_EV_IRQHandler
+I3C1_ER_IRQHandler
+I3C2_EV_IRQHandler
+I3C2_ER_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/arm/startup_stm32h562xx.s

@@ -0,0 +1,563 @@
+;*******************************************************************************
+;* File Name          : startup_stm32h562xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H562xx Non Crypto devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                     ; Top of Stack
+                DCD     Reset_Handler                    ; Reset Handler
+                DCD     NMI_Handler                      ; NMI Handler
+                DCD     HardFault_Handler                ; Hard Fault Handler
+                DCD     MemManage_Handler                ; MPU Fault Handler
+                DCD     BusFault_Handler                 ; Bus Fault Handler
+                DCD     UsageFault_Handler               ; Usage Fault Handler
+                DCD     SecureFault_Handler              ; Secure Fault Handler
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     SVC_Handler                      ; SVCall Handler
+                DCD     DebugMon_Handler                 ; Debug Monitor Handler
+                DCD     0                                ; Reserved
+                DCD     PendSV_Handler                   ; PendSV Handler
+                DCD     SysTick_Handler                  ; SysTick Handler
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                  ; Window WatchDog
+                DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+                DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+                DCD     RTC_S_IRQHandler                 ; RTC secure interrupt
+                DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+                DCD     RAMCFG_IRQHandler                ; RAMCFG global
+                DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+                DCD     FLASH_S_IRQHandler               ; FLASH secure global interrupt
+                DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+                DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+                DCD     RCC_S_IRQHandler                 ; RCC secure global interrupt
+                DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+                DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+                DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+                DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+                DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+                DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+                DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+                DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+                DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+                DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+                DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+                DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+                DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+                DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+                DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+                DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+                DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+                DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+                DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+                DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+                DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+                DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+                DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+                DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+                DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+                DCD     0                                ; Reserved
+                DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+                DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+                DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+                DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+                DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+                DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+                DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+                DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+                DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+                DCD     TIM4_IRQHandler                  ; TIM4 global interrupt
+                DCD     TIM5_IRQHandler                  ; TIM5 global interrupt
+                DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+                DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+                DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+                DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+                DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+                DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+                DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+                DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+                DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+                DCD     USART1_IRQHandler                ; USART1 global interrupt
+                DCD     USART2_IRQHandler                ; USART2 global interrupt
+                DCD     USART3_IRQHandler                ; USART3 global interrupt
+                DCD     UART4_IRQHandler                 ; UART4 global interrupt
+                DCD     UART5_IRQHandler                 ; UART5 global interrupt
+                DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+                DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+                DCD     TIM8_BRK_IRQHandler              ; TIM8 Break interrupt
+                DCD     TIM8_UP_IRQHandler               ; TIM8 Update interrupt
+                DCD     TIM8_TRG_COM_IRQHandler          ; TIM8 Trigger and Commutation interrupt
+                DCD     TIM8_CC_IRQHandler               ; TIM8 Capture Compare interrupt
+                DCD     ADC2_IRQHandler                  ; ADC2 global interrupt
+                DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+                DCD     TIM15_IRQHandler                 ; TIM15 global interrupt
+                DCD     TIM16_IRQHandler                 ; TIM16 global interrupt
+                DCD     TIM17_IRQHandler                 ; TIM17 global interrupt
+                DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+                DCD     CRS_IRQHandler                   ; CRS global interrupt
+                DCD     UCPD1_IRQHandler                 ; UCPD1 global interrupt
+                DCD     FMC_IRQHandler                   ; FMC global interrupt
+                DCD     OCTOSPI1_IRQHandler              ; OctoSPI1 global interrupt
+                DCD     SDMMC1_IRQHandler                ; SDMMC1 global interrupt
+                DCD     I2C3_EV_IRQHandler               ; I2C2 Event interrupt
+                DCD     I2C3_ER_IRQHandler               ; I2C2 Error interrupt
+                DCD     SPI4_IRQHandler                  ; SPI4 global interrupt
+                DCD     SPI5_IRQHandler                  ; SPI5 global interrupt
+                DCD     SPI6_IRQHandler                  ; SPI6 global interrupt
+                DCD     USART6_IRQHandler                ; USART6 global interrupt
+                DCD     USART10_IRQHandler               ; USART10 global interrupt
+                DCD     USART11_IRQHandler               ; USART11 global interrupt
+                DCD     SAI1_IRQHandler                  ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                  ; Serial Audio Interface 2 global interrupt
+                DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+                DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+                DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+                DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+                DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+                DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+                DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+                DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+                DCD     UART7_IRQHandler                 ; UART7 global interrupt
+                DCD     UART8_IRQHandler                 ; UART8 global interrupt
+                DCD     UART9_IRQHandler                 ; UART9 global interrupt
+                DCD     UART12_IRQHandler                ; UART12 global interrupt
+                DCD     0                                ; Reserved
+                DCD     FPU_IRQHandler                   ; FPU global interrupt
+                DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+                DCD     DCACHE1_IRQHandler               ; DCACHE1 global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     DCMI_PSSI_IRQHandler             ; DCMI PSSI global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     CORDIC_IRQHandler                ; CORDIC global interrupt
+                DCD     FMAC_IRQHandler                  ; FMAC global interrupt
+                DCD     DTS_IRQHandler                   ; DTS global interrupt
+                DCD     RNG_IRQHandler                   ; RNG global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     HASH_IRQHandler                  ; HASH global interrupt
+                DCD     0                                ; Reserved
+                DCD     CEC_IRQHandler                   ; CEC global interrupt
+                DCD     TIM12_IRQHandler                 ; TIM12 global interrupt
+                DCD     TIM13_IRQHandler                 ; TIM13 global interrupt
+                DCD     TIM14_IRQHandler                 ; TIM14 global interrupt
+                DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+                DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+                DCD     I2C4_EV_IRQHandler               ; I2C4 Event interrupt
+                DCD     I2C4_ER_IRQHandler               ; I2C4 Error interrupt
+                DCD     LPTIM3_IRQHandler                ; LPTIM3 global interrupt
+                DCD     LPTIM4_IRQHandler                ; LPTIM4 global interrupt
+                DCD     LPTIM5_IRQHandler                ; LPTIM5 global interrupt
+                DCD     LPTIM6_IRQHandler                ; LPTIM6 global interrupt
+
+
+__Vectors_End
+
+__Vectors_Size  EQU    __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SecureFault_Handler\
+                PROC
+                EXPORT  SecureFault_Handler       [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                  [WEAK]
+                EXPORT  PVD_AVD_IRQHandler               [WEAK]
+                EXPORT  RTC_IRQHandler                   [WEAK]
+                EXPORT  RTC_S_IRQHandler                 [WEAK]
+                EXPORT  TAMP_IRQHandler                  [WEAK]
+                EXPORT  RAMCFG_IRQHandler                [WEAK]
+                EXPORT  FLASH_IRQHandler                 [WEAK]
+                EXPORT  FLASH_S_IRQHandler               [WEAK]
+                EXPORT  GTZC_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                   [WEAK]
+                EXPORT  RCC_S_IRQHandler                 [WEAK]
+                EXPORT  EXTI0_IRQHandler                 [WEAK]
+                EXPORT  EXTI1_IRQHandler                 [WEAK]
+                EXPORT  EXTI2_IRQHandler                 [WEAK]
+                EXPORT  EXTI3_IRQHandler                 [WEAK]
+                EXPORT  EXTI4_IRQHandler                 [WEAK]
+                EXPORT  EXTI5_IRQHandler                 [WEAK]
+                EXPORT  EXTI6_IRQHandler                 [WEAK]
+                EXPORT  EXTI7_IRQHandler                 [WEAK]
+                EXPORT  EXTI8_IRQHandler                 [WEAK]
+                EXPORT  EXTI9_IRQHandler                 [WEAK]
+                EXPORT  EXTI10_IRQHandler                [WEAK]
+                EXPORT  EXTI11_IRQHandler                [WEAK]
+                EXPORT  EXTI12_IRQHandler                [WEAK]
+                EXPORT  EXTI13_IRQHandler                [WEAK]
+                EXPORT  EXTI14_IRQHandler                [WEAK]
+                EXPORT  EXTI15_IRQHandler                [WEAK]
+                EXPORT  GPDMA1_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel7_IRQHandler       [WEAK]
+                EXPORT  IWDG_IRQHandler                  [WEAK]
+                EXPORT  ADC1_IRQHandler                  [WEAK]
+                EXPORT  DAC1_IRQHandler                  [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler            [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler            [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM1_UP_IRQHandler               [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM1_CC_IRQHandler               [WEAK]
+                EXPORT  TIM2_IRQHandler                  [WEAK]
+                EXPORT  TIM3_IRQHandler                  [WEAK]
+                EXPORT  TIM4_IRQHandler                  [WEAK]
+                EXPORT  TIM5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_IRQHandler                  [WEAK]
+                EXPORT  TIM7_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler               [WEAK]
+                EXPORT  I2C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C2_EV_IRQHandler               [WEAK]
+                EXPORT  I2C2_ER_IRQHandler               [WEAK]
+                EXPORT  SPI1_IRQHandler                  [WEAK]
+                EXPORT  SPI2_IRQHandler                  [WEAK]
+                EXPORT  SPI3_IRQHandler                  [WEAK]
+                EXPORT  USART1_IRQHandler                [WEAK]
+                EXPORT  USART2_IRQHandler                [WEAK]
+                EXPORT  USART3_IRQHandler                [WEAK]
+                EXPORT  UART4_IRQHandler                 [WEAK]
+                EXPORT  UART5_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM8_UP_IRQHandler               [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM8_CC_IRQHandler               [WEAK]
+                EXPORT  ADC2_IRQHandler                  [WEAK]
+                EXPORT  LPTIM2_IRQHandler                [WEAK]
+                EXPORT  TIM15_IRQHandler                 [WEAK]
+                EXPORT  TIM16_IRQHandler                 [WEAK]
+                EXPORT  TIM17_IRQHandler                 [WEAK]
+                EXPORT  USB_DRD_FS_IRQHandler            [WEAK]
+                EXPORT  CRS_IRQHandler                   [WEAK]
+                EXPORT  UCPD1_IRQHandler                 [WEAK]
+                EXPORT  FMC_IRQHandler                   [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler              [WEAK]
+                EXPORT  SDMMC1_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler               [WEAK]
+                EXPORT  I2C3_ER_IRQHandler               [WEAK]
+                EXPORT  SPI4_IRQHandler                  [WEAK]
+                EXPORT  SPI5_IRQHandler                  [WEAK]
+                EXPORT  SPI6_IRQHandler                  [WEAK]
+                EXPORT  USART6_IRQHandler                [WEAK]
+                EXPORT  USART10_IRQHandler               [WEAK]
+                EXPORT  USART11_IRQHandler               [WEAK]
+                EXPORT  SAI1_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                  [WEAK]
+                EXPORT  GPDMA2_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel7_IRQHandler       [WEAK]
+                EXPORT  UART7_IRQHandler                 [WEAK]
+                EXPORT  UART8_IRQHandler                 [WEAK]
+                EXPORT  UART9_IRQHandler                 [WEAK]
+                EXPORT  UART12_IRQHandler                [WEAK]
+                EXPORT  FPU_IRQHandler                   [WEAK]
+                EXPORT  ICACHE_IRQHandler                [WEAK]
+                EXPORT  DCACHE1_IRQHandler               [WEAK]
+                EXPORT  DCMI_PSSI_IRQHandler             [WEAK]
+                EXPORT  CORDIC_IRQHandler                [WEAK]
+                EXPORT  FMAC_IRQHandler                  [WEAK]
+                EXPORT  DTS_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                   [WEAK]
+                EXPORT  HASH_IRQHandler                  [WEAK]
+                EXPORT  CEC_IRQHandler                   [WEAK]
+                EXPORT  TIM12_IRQHandler                 [WEAK]
+                EXPORT  TIM13_IRQHandler                 [WEAK]
+                EXPORT  TIM14_IRQHandler                 [WEAK]
+                EXPORT  I3C1_EV_IRQHandler               [WEAK]
+                EXPORT  I3C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C4_EV_IRQHandler               [WEAK]
+                EXPORT  I2C4_ER_IRQHandler               [WEAK]
+                EXPORT  LPTIM3_IRQHandler                [WEAK]
+                EXPORT  LPTIM4_IRQHandler                [WEAK]
+                EXPORT  LPTIM5_IRQHandler                [WEAK]
+                EXPORT  LPTIM6_IRQHandler                [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+RTC_IRQHandler
+RTC_S_IRQHandler
+TAMP_IRQHandler
+RAMCFG_IRQHandler
+FLASH_IRQHandler
+FLASH_S_IRQHandler
+GTZC_IRQHandler
+RCC_IRQHandler
+RCC_S_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+EXTI8_IRQHandler
+EXTI9_IRQHandler
+EXTI10_IRQHandler
+EXTI11_IRQHandler
+EXTI12_IRQHandler
+EXTI13_IRQHandler
+EXTI14_IRQHandler
+EXTI15_IRQHandler
+GPDMA1_Channel0_IRQHandler
+GPDMA1_Channel1_IRQHandler
+GPDMA1_Channel2_IRQHandler
+GPDMA1_Channel3_IRQHandler
+GPDMA1_Channel4_IRQHandler
+GPDMA1_Channel5_IRQHandler
+GPDMA1_Channel6_IRQHandler
+GPDMA1_Channel7_IRQHandler
+IWDG_IRQHandler
+ADC1_IRQHandler
+DAC1_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+SPI3_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC2_IRQHandler
+LPTIM2_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+USB_DRD_FS_IRQHandler
+CRS_IRQHandler
+UCPD1_IRQHandler
+FMC_IRQHandler
+OCTOSPI1_IRQHandler
+SDMMC1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+USART6_IRQHandler
+USART10_IRQHandler
+USART11_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+GPDMA2_Channel0_IRQHandler
+GPDMA2_Channel1_IRQHandler
+GPDMA2_Channel2_IRQHandler
+GPDMA2_Channel3_IRQHandler
+GPDMA2_Channel4_IRQHandler
+GPDMA2_Channel5_IRQHandler
+GPDMA2_Channel6_IRQHandler
+GPDMA2_Channel7_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+UART9_IRQHandler
+UART12_IRQHandler
+FPU_IRQHandler
+ICACHE_IRQHandler
+DCACHE1_IRQHandler
+DCMI_PSSI_IRQHandler
+CORDIC_IRQHandler
+FMAC_IRQHandler
+DTS_IRQHandler
+RNG_IRQHandler
+HASH_IRQHandler
+CEC_IRQHandler
+TIM12_IRQHandler
+TIM13_IRQHandler
+TIM14_IRQHandler
+I3C1_EV_IRQHandler
+I3C1_ER_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPTIM6_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/arm/startup_stm32h563xx.s

@@ -0,0 +1,573 @@
+;*******************************************************************************
+;* File Name          : startup_stm32h563xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H563xx Non Crypto devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                     ; Top of Stack
+                DCD     Reset_Handler                    ; Reset Handler
+                DCD     NMI_Handler                      ; NMI Handler
+                DCD     HardFault_Handler                ; Hard Fault Handler
+                DCD     MemManage_Handler                ; MPU Fault Handler
+                DCD     BusFault_Handler                 ; Bus Fault Handler
+                DCD     UsageFault_Handler               ; Usage Fault Handler
+                DCD     SecureFault_Handler              ; Secure Fault Handler
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     SVC_Handler                      ; SVCall Handler
+                DCD     DebugMon_Handler                 ; Debug Monitor Handler
+                DCD     0                                ; Reserved
+                DCD     PendSV_Handler                   ; PendSV Handler
+                DCD     SysTick_Handler                  ; SysTick Handler
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                  ; Window WatchDog
+                DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+                DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+                DCD     RTC_S_IRQHandler                 ; RTC secure interrupt
+                DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+                DCD     RAMCFG_IRQHandler                ; RAMCFG global
+                DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+                DCD     FLASH_S_IRQHandler               ; FLASH secure global interrupt
+                DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+                DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+                DCD     RCC_S_IRQHandler                 ; RCC secure global interrupt
+                DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+                DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+                DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+                DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+                DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+                DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+                DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+                DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+                DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+                DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+                DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+                DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+                DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+                DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+                DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+                DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+                DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+                DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+                DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+                DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+                DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+                DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+                DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+                DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+                DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+                DCD     0                                ; Reserved
+                DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+                DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+                DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+                DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+                DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+                DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+                DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+                DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+                DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+                DCD     TIM4_IRQHandler                  ; TIM4 global interrupt
+                DCD     TIM5_IRQHandler                  ; TIM5 global interrupt
+                DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+                DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+                DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+                DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+                DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+                DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+                DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+                DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+                DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+                DCD     USART1_IRQHandler                ; USART1 global interrupt
+                DCD     USART2_IRQHandler                ; USART2 global interrupt
+                DCD     USART3_IRQHandler                ; USART3 global interrupt
+                DCD     UART4_IRQHandler                 ; UART4 global interrupt
+                DCD     UART5_IRQHandler                 ; UART5 global interrupt
+                DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+                DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+                DCD     TIM8_BRK_IRQHandler              ; TIM8 Break interrupt
+                DCD     TIM8_UP_IRQHandler               ; TIM8 Update interrupt
+                DCD     TIM8_TRG_COM_IRQHandler          ; TIM8 Trigger and Commutation interrupt
+                DCD     TIM8_CC_IRQHandler               ; TIM8 Capture Compare interrupt
+                DCD     ADC2_IRQHandler                  ; ADC2 global interrupt
+                DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+                DCD     TIM15_IRQHandler                 ; TIM15 global interrupt
+                DCD     TIM16_IRQHandler                 ; TIM16 global interrupt
+                DCD     TIM17_IRQHandler                 ; TIM17 global interrupt
+                DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+                DCD     CRS_IRQHandler                   ; CRS global interrupt
+                DCD     UCPD1_IRQHandler                 ; UCPD1 global interrupt
+                DCD     FMC_IRQHandler                   ; FMC global interrupt
+                DCD     OCTOSPI1_IRQHandler              ; OctoSPI1 global interrupt
+                DCD     SDMMC1_IRQHandler                ; SDMMC1 global interrupt
+                DCD     I2C3_EV_IRQHandler               ; I2C2 Event interrupt
+                DCD     I2C3_ER_IRQHandler               ; I2C2 Error interrupt
+                DCD     SPI4_IRQHandler                  ; SPI4 global interrupt
+                DCD     SPI5_IRQHandler                  ; SPI5 global interrupt
+                DCD     SPI6_IRQHandler                  ; SPI6 global interrupt
+                DCD     USART6_IRQHandler                ; USART6 global interrupt
+                DCD     USART10_IRQHandler               ; USART10 global interrupt
+                DCD     USART11_IRQHandler               ; USART11 global interrupt
+                DCD     SAI1_IRQHandler                  ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                  ; Serial Audio Interface 2 global interrupt
+                DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+                DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+                DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+                DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+                DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+                DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+                DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+                DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+                DCD     UART7_IRQHandler                 ; UART7 global interrupt
+                DCD     UART8_IRQHandler                 ; UART8 global interrupt
+                DCD     UART9_IRQHandler                 ; UART9 global interrupt
+                DCD     UART12_IRQHandler                ; UART12 global interrupt
+                DCD     SDMMC2_IRQHandler                ; SDMMC2 global interrupt
+                DCD     FPU_IRQHandler                   ; FPU global interrupt
+                DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+                DCD     DCACHE1_IRQHandler               ; DCACHE1 global interrupt
+                DCD     ETH_IRQHandler                   ; Ethernet global interrupt
+                DCD     ETH_WKUP_IRQHandler              ; Ethernet Wakeup global interrupt
+                DCD     DCMI_PSSI_IRQHandler             ; DCMI PSSI global interrupt
+                DCD     FDCAN2_IT0_IRQHandler            ; FDCAN2 interrupt 0
+                DCD     FDCAN2_IT1_IRQHandler            ; FDCAN2 interrupt 1
+                DCD     CORDIC_IRQHandler                ; CORDIC global interrupt
+                DCD     FMAC_IRQHandler                  ; FMAC global interrupt
+                DCD     DTS_IRQHandler                   ; DTS global interrupt
+                DCD     RNG_IRQHandler                   ; RNG global interrupt
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     HASH_IRQHandler                  ; HASH global interrupt
+                DCD     0                                ; Reserved
+                DCD     CEC_IRQHandler                   ; CEC global interrupt
+                DCD     TIM12_IRQHandler                 ; TIM12 global interrupt
+                DCD     TIM13_IRQHandler                 ; TIM13 global interrupt
+                DCD     TIM14_IRQHandler                 ; TIM14 global interrupt
+                DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+                DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+                DCD     I2C4_EV_IRQHandler               ; I2C4 Event interrupt
+                DCD     I2C4_ER_IRQHandler               ; I2C4 Error interrupt
+                DCD     LPTIM3_IRQHandler                ; LPTIM3 global interrupt
+                DCD     LPTIM4_IRQHandler                ; LPTIM4 global interrupt
+                DCD     LPTIM5_IRQHandler                ; LPTIM5 global interrupt
+                DCD     LPTIM6_IRQHandler                ; LPTIM6 global interrupt
+
+
+__Vectors_End
+
+__Vectors_Size  EQU    __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SecureFault_Handler\
+                PROC
+                EXPORT  SecureFault_Handler       [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                  [WEAK]
+                EXPORT  PVD_AVD_IRQHandler               [WEAK]
+                EXPORT  RTC_IRQHandler                   [WEAK]
+                EXPORT  RTC_S_IRQHandler                 [WEAK]
+                EXPORT  TAMP_IRQHandler                  [WEAK]
+                EXPORT  RAMCFG_IRQHandler                [WEAK]
+                EXPORT  FLASH_IRQHandler                 [WEAK]
+                EXPORT  FLASH_S_IRQHandler               [WEAK]
+                EXPORT  GTZC_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                   [WEAK]
+                EXPORT  RCC_S_IRQHandler                 [WEAK]
+                EXPORT  EXTI0_IRQHandler                 [WEAK]
+                EXPORT  EXTI1_IRQHandler                 [WEAK]
+                EXPORT  EXTI2_IRQHandler                 [WEAK]
+                EXPORT  EXTI3_IRQHandler                 [WEAK]
+                EXPORT  EXTI4_IRQHandler                 [WEAK]
+                EXPORT  EXTI5_IRQHandler                 [WEAK]
+                EXPORT  EXTI6_IRQHandler                 [WEAK]
+                EXPORT  EXTI7_IRQHandler                 [WEAK]
+                EXPORT  EXTI8_IRQHandler                 [WEAK]
+                EXPORT  EXTI9_IRQHandler                 [WEAK]
+                EXPORT  EXTI10_IRQHandler                [WEAK]
+                EXPORT  EXTI11_IRQHandler                [WEAK]
+                EXPORT  EXTI12_IRQHandler                [WEAK]
+                EXPORT  EXTI13_IRQHandler                [WEAK]
+                EXPORT  EXTI14_IRQHandler                [WEAK]
+                EXPORT  EXTI15_IRQHandler                [WEAK]
+                EXPORT  GPDMA1_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel7_IRQHandler       [WEAK]
+                EXPORT  IWDG_IRQHandler                  [WEAK]
+                EXPORT  ADC1_IRQHandler                  [WEAK]
+                EXPORT  DAC1_IRQHandler                  [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler            [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler            [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM1_UP_IRQHandler               [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM1_CC_IRQHandler               [WEAK]
+                EXPORT  TIM2_IRQHandler                  [WEAK]
+                EXPORT  TIM3_IRQHandler                  [WEAK]
+                EXPORT  TIM4_IRQHandler                  [WEAK]
+                EXPORT  TIM5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_IRQHandler                  [WEAK]
+                EXPORT  TIM7_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler               [WEAK]
+                EXPORT  I2C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C2_EV_IRQHandler               [WEAK]
+                EXPORT  I2C2_ER_IRQHandler               [WEAK]
+                EXPORT  SPI1_IRQHandler                  [WEAK]
+                EXPORT  SPI2_IRQHandler                  [WEAK]
+                EXPORT  SPI3_IRQHandler                  [WEAK]
+                EXPORT  USART1_IRQHandler                [WEAK]
+                EXPORT  USART2_IRQHandler                [WEAK]
+                EXPORT  USART3_IRQHandler                [WEAK]
+                EXPORT  UART4_IRQHandler                 [WEAK]
+                EXPORT  UART5_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM8_UP_IRQHandler               [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM8_CC_IRQHandler               [WEAK]
+                EXPORT  ADC2_IRQHandler                  [WEAK]
+                EXPORT  LPTIM2_IRQHandler                [WEAK]
+                EXPORT  TIM15_IRQHandler                 [WEAK]
+                EXPORT  TIM16_IRQHandler                 [WEAK]
+                EXPORT  TIM17_IRQHandler                 [WEAK]
+                EXPORT  USB_DRD_FS_IRQHandler            [WEAK]
+                EXPORT  CRS_IRQHandler                   [WEAK]
+                EXPORT  UCPD1_IRQHandler                 [WEAK]
+                EXPORT  FMC_IRQHandler                   [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler              [WEAK]
+                EXPORT  SDMMC1_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler               [WEAK]
+                EXPORT  I2C3_ER_IRQHandler               [WEAK]
+                EXPORT  SPI4_IRQHandler                  [WEAK]
+                EXPORT  SPI5_IRQHandler                  [WEAK]
+                EXPORT  SPI6_IRQHandler                  [WEAK]
+                EXPORT  USART6_IRQHandler                [WEAK]
+                EXPORT  USART10_IRQHandler               [WEAK]
+                EXPORT  USART11_IRQHandler               [WEAK]
+                EXPORT  SAI1_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                  [WEAK]
+                EXPORT  GPDMA2_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel7_IRQHandler       [WEAK]
+                EXPORT  UART7_IRQHandler                 [WEAK]
+                EXPORT  UART8_IRQHandler                 [WEAK]
+                EXPORT  UART9_IRQHandler                 [WEAK]
+                EXPORT  UART12_IRQHandler                [WEAK]
+                EXPORT  SDMMC2_IRQHandler                [WEAK]
+                EXPORT  FPU_IRQHandler                   [WEAK]
+                EXPORT  ICACHE_IRQHandler                [WEAK]
+                EXPORT  DCACHE1_IRQHandler               [WEAK]
+                EXPORT  ETH_IRQHandler                   [WEAK]
+                EXPORT  ETH_WKUP_IRQHandler              [WEAK]
+                EXPORT  DCMI_PSSI_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT0_IRQHandler            [WEAK]
+                EXPORT  FDCAN2_IT1_IRQHandler            [WEAK]
+                EXPORT  CORDIC_IRQHandler                [WEAK]
+                EXPORT  FMAC_IRQHandler                  [WEAK]
+                EXPORT  DTS_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                   [WEAK]
+                EXPORT  HASH_IRQHandler                  [WEAK]
+                EXPORT  CEC_IRQHandler                   [WEAK]
+                EXPORT  TIM12_IRQHandler                 [WEAK]
+                EXPORT  TIM13_IRQHandler                 [WEAK]
+                EXPORT  TIM14_IRQHandler                 [WEAK]
+                EXPORT  I3C1_EV_IRQHandler               [WEAK]
+                EXPORT  I3C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C4_EV_IRQHandler               [WEAK]
+                EXPORT  I2C4_ER_IRQHandler               [WEAK]
+                EXPORT  LPTIM3_IRQHandler                [WEAK]
+                EXPORT  LPTIM4_IRQHandler                [WEAK]
+                EXPORT  LPTIM5_IRQHandler                [WEAK]
+                EXPORT  LPTIM6_IRQHandler                [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+RTC_IRQHandler
+RTC_S_IRQHandler
+TAMP_IRQHandler
+RAMCFG_IRQHandler
+FLASH_IRQHandler
+FLASH_S_IRQHandler
+GTZC_IRQHandler
+RCC_IRQHandler
+RCC_S_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+EXTI8_IRQHandler
+EXTI9_IRQHandler
+EXTI10_IRQHandler
+EXTI11_IRQHandler
+EXTI12_IRQHandler
+EXTI13_IRQHandler
+EXTI14_IRQHandler
+EXTI15_IRQHandler
+GPDMA1_Channel0_IRQHandler
+GPDMA1_Channel1_IRQHandler
+GPDMA1_Channel2_IRQHandler
+GPDMA1_Channel3_IRQHandler
+GPDMA1_Channel4_IRQHandler
+GPDMA1_Channel5_IRQHandler
+GPDMA1_Channel6_IRQHandler
+GPDMA1_Channel7_IRQHandler
+IWDG_IRQHandler
+ADC1_IRQHandler
+DAC1_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+SPI3_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC2_IRQHandler
+LPTIM2_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+USB_DRD_FS_IRQHandler
+CRS_IRQHandler
+UCPD1_IRQHandler
+FMC_IRQHandler
+OCTOSPI1_IRQHandler
+SDMMC1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+USART6_IRQHandler
+USART10_IRQHandler
+USART11_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+GPDMA2_Channel0_IRQHandler
+GPDMA2_Channel1_IRQHandler
+GPDMA2_Channel2_IRQHandler
+GPDMA2_Channel3_IRQHandler
+GPDMA2_Channel4_IRQHandler
+GPDMA2_Channel5_IRQHandler
+GPDMA2_Channel6_IRQHandler
+GPDMA2_Channel7_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+UART9_IRQHandler
+UART12_IRQHandler
+SDMMC2_IRQHandler
+FPU_IRQHandler
+ICACHE_IRQHandler
+DCACHE1_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+DCMI_PSSI_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN2_IT1_IRQHandler
+CORDIC_IRQHandler
+FMAC_IRQHandler
+DTS_IRQHandler
+RNG_IRQHandler
+HASH_IRQHandler
+CEC_IRQHandler
+TIM12_IRQHandler
+TIM13_IRQHandler
+TIM14_IRQHandler
+I3C1_EV_IRQHandler
+I3C1_ER_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPTIM6_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/arm/startup_stm32h573xx.s

@@ -0,0 +1,581 @@
+;*******************************************************************************
+;* File Name          : startup_stm32h573xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H573xx Crypto devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                     ; Top of Stack
+                DCD     Reset_Handler                    ; Reset Handler
+                DCD     NMI_Handler                      ; NMI Handler
+                DCD     HardFault_Handler                ; Hard Fault Handler
+                DCD     MemManage_Handler                ; MPU Fault Handler
+                DCD     BusFault_Handler                 ; Bus Fault Handler
+                DCD     UsageFault_Handler               ; Usage Fault Handler
+                DCD     SecureFault_Handler              ; Secure Fault Handler
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     SVC_Handler                      ; SVCall Handler
+                DCD     DebugMon_Handler                 ; Debug Monitor Handler
+                DCD     0                                ; Reserved
+                DCD     PendSV_Handler                   ; PendSV Handler
+                DCD     SysTick_Handler                  ; SysTick Handler
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                  ; Window WatchDog
+                DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+                DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+                DCD     RTC_S_IRQHandler                 ; RTC secure interrupt
+                DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+                DCD     RAMCFG_IRQHandler                ; RAMCFG global
+                DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+                DCD     FLASH_S_IRQHandler               ; FLASH secure global interrupt
+                DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+                DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+                DCD     RCC_S_IRQHandler                 ; RCC secure global interrupt
+                DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+                DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+                DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+                DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+                DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+                DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+                DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+                DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+                DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+                DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+                DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+                DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+                DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+                DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+                DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+                DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+                DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+                DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+                DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+                DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+                DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+                DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+                DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+                DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+                DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+                DCD     SAES_IRQHandler                  ; SAES global interrupt
+                DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+                DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+                DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+                DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+                DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+                DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+                DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+                DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+                DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+                DCD     TIM4_IRQHandler                  ; TIM4 global interrupt
+                DCD     TIM5_IRQHandler                  ; TIM5 global interrupt
+                DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+                DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+                DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+                DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+                DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+                DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+                DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+                DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+                DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+                DCD     USART1_IRQHandler                ; USART1 global interrupt
+                DCD     USART2_IRQHandler                ; USART2 global interrupt
+                DCD     USART3_IRQHandler                ; USART3 global interrupt
+                DCD     UART4_IRQHandler                 ; UART4 global interrupt
+                DCD     UART5_IRQHandler                 ; UART5 global interrupt
+                DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+                DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+                DCD     TIM8_BRK_IRQHandler              ; TIM8 Break interrupt
+                DCD     TIM8_UP_IRQHandler               ; TIM8 Update interrupt
+                DCD     TIM8_TRG_COM_IRQHandler          ; TIM8 Trigger and Commutation interrupt
+                DCD     TIM8_CC_IRQHandler               ; TIM8 Capture Compare interrupt
+                DCD     ADC2_IRQHandler                  ; ADC2 global interrupt
+                DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+                DCD     TIM15_IRQHandler                 ; TIM15 global interrupt
+                DCD     TIM16_IRQHandler                 ; TIM16 global interrupt
+                DCD     TIM17_IRQHandler                 ; TIM17 global interrupt
+                DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+                DCD     CRS_IRQHandler                   ; CRS global interrupt
+                DCD     UCPD1_IRQHandler                 ; UCPD1 global interrupt
+                DCD     FMC_IRQHandler                   ; FMC global interrupt
+                DCD     OCTOSPI1_IRQHandler              ; OctoSPI1 global interrupt
+                DCD     SDMMC1_IRQHandler                ; SDMMC1 global interrupt
+                DCD     I2C3_EV_IRQHandler               ; I2C2 Event interrupt
+                DCD     I2C3_ER_IRQHandler               ; I2C2 Error interrupt
+                DCD     SPI4_IRQHandler                  ; SPI4 global interrupt
+                DCD     SPI5_IRQHandler                  ; SPI5 global interrupt
+                DCD     SPI6_IRQHandler                  ; SPI6 global interrupt
+                DCD     USART6_IRQHandler                ; USART6 global interrupt
+                DCD     USART10_IRQHandler               ; USART10 global interrupt
+                DCD     USART11_IRQHandler               ; USART11 global interrupt
+                DCD     SAI1_IRQHandler                  ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                  ; Serial Audio Interface 2 global interrupt
+                DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+                DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+                DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+                DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+                DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+                DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+                DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+                DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+                DCD     UART7_IRQHandler                 ; UART7 global interrupt
+                DCD     UART8_IRQHandler                 ; UART8 global interrupt
+                DCD     UART9_IRQHandler                 ; UART9 global interrupt
+                DCD     UART12_IRQHandler                ; UART12 global interrupt
+                DCD     SDMMC2_IRQHandler                ; SDMMC2 global interrupt
+                DCD     FPU_IRQHandler                   ; FPU global interrupt
+                DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+                DCD     DCACHE1_IRQHandler               ; DCACHE1 global interrupt
+                DCD     ETH_IRQHandler                   ; Ethernet global interrupt
+                DCD     ETH_WKUP_IRQHandler              ; Ethernet Wakeup global interrupt
+                DCD     DCMI_PSSI_IRQHandler             ; DCMI PSSI global interrupt
+                DCD     FDCAN2_IT0_IRQHandler            ; FDCAN2 interrupt 0
+                DCD     FDCAN2_IT1_IRQHandler            ; FDCAN2 interrupt 1
+                DCD     CORDIC_IRQHandler                ; CORDIC global interrupt
+                DCD     FMAC_IRQHandler                  ; FMAC global interrupt
+                DCD     DTS_IRQHandler                   ; DTS global interrupt
+                DCD     RNG_IRQHandler                   ; RNG global interrupt
+                DCD     OTFDEC1_IRQHandler               ; OTFDEC1 global interrupt
+                DCD     AES_IRQHandler                   ; AES global interrupt
+                DCD     HASH_IRQHandler                  ; HASH global interrupt
+                DCD     PKA_IRQHandler                   ; PKA global interrupt
+                DCD     CEC_IRQHandler                   ; CEC global interrupt
+                DCD     TIM12_IRQHandler                 ; TIM12 global interrupt
+                DCD     TIM13_IRQHandler                 ; TIM13 global interrupt
+                DCD     TIM14_IRQHandler                 ; TIM14 global interrupt
+                DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+                DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+                DCD     I2C4_EV_IRQHandler               ; I2C4 Event interrupt
+                DCD     I2C4_ER_IRQHandler               ; I2C4 Error interrupt
+                DCD     LPTIM3_IRQHandler                ; LPTIM3 global interrupt
+                DCD     LPTIM4_IRQHandler                ; LPTIM4 global interrupt
+                DCD     LPTIM5_IRQHandler                ; LPTIM5 global interrupt
+                DCD     LPTIM6_IRQHandler                ; LPTIM6 global interrupt
+
+
+__Vectors_End
+
+__Vectors_Size  EQU    __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SecureFault_Handler\
+                PROC
+                EXPORT  SecureFault_Handler       [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                  [WEAK]
+                EXPORT  PVD_AVD_IRQHandler               [WEAK]
+                EXPORT  RTC_IRQHandler                   [WEAK]
+                EXPORT  RTC_S_IRQHandler                 [WEAK]
+                EXPORT  TAMP_IRQHandler                  [WEAK]
+                EXPORT  RAMCFG_IRQHandler                [WEAK]
+                EXPORT  FLASH_IRQHandler                 [WEAK]
+                EXPORT  FLASH_S_IRQHandler               [WEAK]
+                EXPORT  GTZC_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                   [WEAK]
+                EXPORT  RCC_S_IRQHandler                 [WEAK]
+                EXPORT  EXTI0_IRQHandler                 [WEAK]
+                EXPORT  EXTI1_IRQHandler                 [WEAK]
+                EXPORT  EXTI2_IRQHandler                 [WEAK]
+                EXPORT  EXTI3_IRQHandler                 [WEAK]
+                EXPORT  EXTI4_IRQHandler                 [WEAK]
+                EXPORT  EXTI5_IRQHandler                 [WEAK]
+                EXPORT  EXTI6_IRQHandler                 [WEAK]
+                EXPORT  EXTI7_IRQHandler                 [WEAK]
+                EXPORT  EXTI8_IRQHandler                 [WEAK]
+                EXPORT  EXTI9_IRQHandler                 [WEAK]
+                EXPORT  EXTI10_IRQHandler                [WEAK]
+                EXPORT  EXTI11_IRQHandler                [WEAK]
+                EXPORT  EXTI12_IRQHandler                [WEAK]
+                EXPORT  EXTI13_IRQHandler                [WEAK]
+                EXPORT  EXTI14_IRQHandler                [WEAK]
+                EXPORT  EXTI15_IRQHandler                [WEAK]
+                EXPORT  GPDMA1_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA1_Channel7_IRQHandler       [WEAK]
+                EXPORT  IWDG_IRQHandler                  [WEAK]
+                EXPORT  SAES_IRQHandler                  [WEAK]
+                EXPORT  ADC1_IRQHandler                  [WEAK]
+                EXPORT  DAC1_IRQHandler                  [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler            [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler            [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM1_UP_IRQHandler               [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM1_CC_IRQHandler               [WEAK]
+                EXPORT  TIM2_IRQHandler                  [WEAK]
+                EXPORT  TIM3_IRQHandler                  [WEAK]
+                EXPORT  TIM4_IRQHandler                  [WEAK]
+                EXPORT  TIM5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_IRQHandler                  [WEAK]
+                EXPORT  TIM7_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler               [WEAK]
+                EXPORT  I2C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C2_EV_IRQHandler               [WEAK]
+                EXPORT  I2C2_ER_IRQHandler               [WEAK]
+                EXPORT  SPI1_IRQHandler                  [WEAK]
+                EXPORT  SPI2_IRQHandler                  [WEAK]
+                EXPORT  SPI3_IRQHandler                  [WEAK]
+                EXPORT  USART1_IRQHandler                [WEAK]
+                EXPORT  USART2_IRQHandler                [WEAK]
+                EXPORT  USART3_IRQHandler                [WEAK]
+                EXPORT  UART4_IRQHandler                 [WEAK]
+                EXPORT  UART5_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM8_UP_IRQHandler               [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM8_CC_IRQHandler               [WEAK]
+                EXPORT  ADC2_IRQHandler                  [WEAK]
+                EXPORT  LPTIM2_IRQHandler                [WEAK]
+                EXPORT  TIM15_IRQHandler                 [WEAK]
+                EXPORT  TIM16_IRQHandler                 [WEAK]
+                EXPORT  TIM17_IRQHandler                 [WEAK]
+                EXPORT  USB_DRD_FS_IRQHandler            [WEAK]
+                EXPORT  CRS_IRQHandler                   [WEAK]
+                EXPORT  UCPD1_IRQHandler                 [WEAK]
+                EXPORT  FMC_IRQHandler                   [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler              [WEAK]
+                EXPORT  SDMMC1_IRQHandler                [WEAK]
+                EXPORT  I2C3_EV_IRQHandler               [WEAK]
+                EXPORT  I2C3_ER_IRQHandler               [WEAK]
+                EXPORT  SPI4_IRQHandler                  [WEAK]
+                EXPORT  SPI5_IRQHandler                  [WEAK]
+                EXPORT  SPI6_IRQHandler                  [WEAK]
+                EXPORT  USART6_IRQHandler                [WEAK]
+                EXPORT  USART10_IRQHandler               [WEAK]
+                EXPORT  USART11_IRQHandler               [WEAK]
+                EXPORT  SAI1_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                  [WEAK]
+                EXPORT  GPDMA2_Channel0_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel1_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel2_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel3_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel4_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel5_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel6_IRQHandler       [WEAK]
+                EXPORT  GPDMA2_Channel7_IRQHandler       [WEAK]
+                EXPORT  UART7_IRQHandler                 [WEAK]
+                EXPORT  UART8_IRQHandler                 [WEAK]
+                EXPORT  UART9_IRQHandler                 [WEAK]
+                EXPORT  UART12_IRQHandler                [WEAK]
+                EXPORT  SDMMC2_IRQHandler                [WEAK]
+                EXPORT  FPU_IRQHandler                   [WEAK]
+                EXPORT  ICACHE_IRQHandler                [WEAK]
+                EXPORT  DCACHE1_IRQHandler               [WEAK]
+                EXPORT  ETH_IRQHandler                   [WEAK]
+                EXPORT  ETH_WKUP_IRQHandler              [WEAK]
+                EXPORT  DCMI_PSSI_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT0_IRQHandler            [WEAK]
+                EXPORT  FDCAN2_IT1_IRQHandler            [WEAK]
+                EXPORT  CORDIC_IRQHandler                [WEAK]
+                EXPORT  FMAC_IRQHandler                  [WEAK]
+                EXPORT  DTS_IRQHandler                   [WEAK]
+                EXPORT  RNG_IRQHandler                   [WEAK]
+                EXPORT  OTFDEC1_IRQHandler               [WEAK]
+                EXPORT  AES_IRQHandler                   [WEAK]
+                EXPORT  HASH_IRQHandler                  [WEAK]
+                EXPORT  PKA_IRQHandler                   [WEAK]
+                EXPORT  CEC_IRQHandler                   [WEAK]
+                EXPORT  TIM12_IRQHandler                 [WEAK]
+                EXPORT  TIM13_IRQHandler                 [WEAK]
+                EXPORT  TIM14_IRQHandler                 [WEAK]
+                EXPORT  I3C1_EV_IRQHandler               [WEAK]
+                EXPORT  I3C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C4_EV_IRQHandler               [WEAK]
+                EXPORT  I2C4_ER_IRQHandler               [WEAK]
+                EXPORT  LPTIM3_IRQHandler                [WEAK]
+                EXPORT  LPTIM4_IRQHandler                [WEAK]
+                EXPORT  LPTIM5_IRQHandler                [WEAK]
+                EXPORT  LPTIM6_IRQHandler                [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+RTC_IRQHandler
+RTC_S_IRQHandler
+TAMP_IRQHandler
+RAMCFG_IRQHandler
+FLASH_IRQHandler
+FLASH_S_IRQHandler
+GTZC_IRQHandler
+RCC_IRQHandler
+RCC_S_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+EXTI8_IRQHandler
+EXTI9_IRQHandler
+EXTI10_IRQHandler
+EXTI11_IRQHandler
+EXTI12_IRQHandler
+EXTI13_IRQHandler
+EXTI14_IRQHandler
+EXTI15_IRQHandler
+GPDMA1_Channel0_IRQHandler
+GPDMA1_Channel1_IRQHandler
+GPDMA1_Channel2_IRQHandler
+GPDMA1_Channel3_IRQHandler
+GPDMA1_Channel4_IRQHandler
+GPDMA1_Channel5_IRQHandler
+GPDMA1_Channel6_IRQHandler
+GPDMA1_Channel7_IRQHandler
+IWDG_IRQHandler
+SAES_IRQHandler
+ADC1_IRQHandler
+DAC1_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+SPI3_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC2_IRQHandler
+LPTIM2_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+USB_DRD_FS_IRQHandler
+CRS_IRQHandler
+UCPD1_IRQHandler
+FMC_IRQHandler
+OCTOSPI1_IRQHandler
+SDMMC1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+USART6_IRQHandler
+USART10_IRQHandler
+USART11_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+GPDMA2_Channel0_IRQHandler
+GPDMA2_Channel1_IRQHandler
+GPDMA2_Channel2_IRQHandler
+GPDMA2_Channel3_IRQHandler
+GPDMA2_Channel4_IRQHandler
+GPDMA2_Channel5_IRQHandler
+GPDMA2_Channel6_IRQHandler
+GPDMA2_Channel7_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+UART9_IRQHandler
+UART12_IRQHandler
+SDMMC2_IRQHandler
+FPU_IRQHandler
+ICACHE_IRQHandler
+DCACHE1_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+DCMI_PSSI_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN2_IT1_IRQHandler
+CORDIC_IRQHandler
+FMAC_IRQHandler
+DTS_IRQHandler
+RNG_IRQHandler
+OTFDEC1_IRQHandler
+AES_IRQHandler
+HASH_IRQHandler
+PKA_IRQHandler
+CEC_IRQHandler
+TIM12_IRQHandler
+TIM13_IRQHandler
+TIM14_IRQHandler
+I3C1_EV_IRQHandler
+I3C1_ER_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPTIM6_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H503xx_FLASH.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H503xx Device from STM32H5 series
+ **                      128Kbytes FLASH
+ **                      32Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 32K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 128K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H503xx_RAM.ld

@@ -0,0 +1,185 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H503xx Device from STM32H5 series
+ **                      32Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 32K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H523xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 272K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH_ns.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H523xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20034000,    LENGTH = 64K    /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */
+  FLASH    (rx)    : ORIGIN = 0x8040000,    LENGTH = 256K    /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH_s.ld

@@ -0,0 +1,195 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H523xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x30000000,    LENGTH = 208K    /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */
+  FLASH    (rx)    : ORIGIN = 0xc000000,    LENGTH = 248K    /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */
+  FLASH_NSC    (rx)    : ORIGIN = 0xc03e000,    LENGTH = 8K    /* Non-Secure Call-able region */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(4);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(4);
+  } >FLASH_NSC
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H523xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 272K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM_ns.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H523xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20020000,    LENGTH = 144K    /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */
+  FLASH    (rx)    : ORIGIN = 0x8040000,    LENGTH = 256K    /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM_s.ld

@@ -0,0 +1,195 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H523xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x30000000,    LENGTH = 120K    /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */
+  RAM_NSC    (xrw)    : ORIGIN = 0x3001e000,    LENGTH = 8K    /* Non-Secure Call-able region */
+  FLASH    (rx)    : ORIGIN = 0xc000000,    LENGTH = 256K    /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(4);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(4);
+  } >RAM_NSC
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H533xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 272K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH_ns.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H533xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20034000,    LENGTH = 64K    /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */
+  FLASH    (rx)    : ORIGIN = 0x8040000,    LENGTH = 256K    /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH_s.ld

@@ -0,0 +1,195 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H533xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x30000000,    LENGTH = 208K    /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */
+  FLASH    (rx)    : ORIGIN = 0xc000000,    LENGTH = 248K    /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */
+  FLASH_NSC    (rx)    : ORIGIN = 0xc03e000,    LENGTH = 8K    /* Non-Secure Call-able region */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(4);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(4);
+  } >FLASH_NSC
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H533xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 272K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM_ns.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H533xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20020000,    LENGTH = 144K    /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */
+  FLASH    (rx)    : ORIGIN = 0x8040000,    LENGTH = 256K    /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM_s.ld

@@ -0,0 +1,195 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H533xx Device from STM32H5 series
+ **                      512Kbytes FLASH
+ **                      272Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x30000000,    LENGTH = 120K    /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */
+  RAM_NSC    (xrw)    : ORIGIN = 0x3001e000,    LENGTH = 8K    /* Non-Secure Call-able region */
+  FLASH    (rx)    : ORIGIN = 0xc000000,    LENGTH = 256K    /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(4);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(4);
+  } >RAM_NSC
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H562xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 640K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH_ns.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H562xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20050000,    LENGTH = 320K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  FLASH    (rx)    : ORIGIN = 0x8100000,    LENGTH = 1024K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH_s.ld

@@ -0,0 +1,195 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H562xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x30000000,    LENGTH = 320K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  FLASH    (rx)    : ORIGIN = 0xc000000,    LENGTH = 1016K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+  FLASH_NSC    (rx)    : ORIGIN = 0xc0fe000,    LENGTH = 8K    /* Non-Secure Call-able region */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(4);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(4);
+  } >FLASH_NSC
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H562xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 640K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM_ns.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H562xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20050000,    LENGTH = 320K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  FLASH    (rx)    : ORIGIN = 0x8100000,    LENGTH = 1024K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM_s.ld

@@ -0,0 +1,195 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H562xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x30000000,    LENGTH = 312K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  RAM_NSC    (xrw)    : ORIGIN = 0x3004e000,    LENGTH = 8K    /* Non-Secure Call-able region */
+  FLASH    (rx)    : ORIGIN = 0xc000000,    LENGTH = 1024K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(4);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(4);
+  } >RAM_NSC
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H563xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM     (xrw)    : ORIGIN = 0x20000000,   LENGTH = 640K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH_ns.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H563xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20050000,    LENGTH = 320K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  FLASH    (rx)    : ORIGIN = 0x8100000,    LENGTH = 1024K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH_s.ld

@@ -0,0 +1,195 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H563xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x30000000,    LENGTH = 320K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  FLASH    (rx)    : ORIGIN = 0xc000000,    LENGTH = 1016K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+  FLASH_NSC    (rx)    : ORIGIN = 0xc0fe000,    LENGTH = 8K    /* Non-Secure Call-able region */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(4);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(4);
+  } >FLASH_NSC
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H563xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 640K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM_ns.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H563xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20050000,    LENGTH = 320K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  FLASH    (rx)    : ORIGIN = 0x8100000,    LENGTH = 1024K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM_s.ld

@@ -0,0 +1,195 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H563xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x30000000,    LENGTH = 312K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  RAM_NSC    (xrw)    : ORIGIN = 0x3004e000,    LENGTH = 8K    /* Non-Secure Call-able region */
+  FLASH    (rx)    : ORIGIN = 0xc000000,    LENGTH = 1024K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(4);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(4);
+  } >RAM_NSC
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H573xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 640K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH_ns.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H573xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20050000,    LENGTH = 320K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  FLASH    (rx)    : ORIGIN = 0x8100000,    LENGTH = 1024K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH_s.ld

@@ -0,0 +1,195 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H573xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x30000000,    LENGTH = 320K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  FLASH    (rx)    : ORIGIN = 0xc000000,    LENGTH = 1016K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+  FLASH_NSC    (rx)    : ORIGIN = 0xc0fe000,    LENGTH = 8K    /* Non-Secure Call-able region */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(4);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(4);
+  } >FLASH_NSC
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H573xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 640K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM_ns.ld

@@ -0,0 +1,187 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H573xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20050000,    LENGTH = 320K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  FLASH    (rx)    : ORIGIN = 0x8100000,    LENGTH = 1024K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM_s.ld

@@ -0,0 +1,195 @@
+/*
+ ******************************************************************************
+ **
+ ** @file        : LinkerScript.ld (debug in RAM dedicated)
+ **
+ ** @author      : Auto-generated by STM32CubeIDE
+ **
+ ** @brief       : Linker script for STM32H573xx Device from STM32H5 series
+ **                      2048Kbytes FLASH
+ **                      640Kbytes RAM
+ **
+ **                Set heap size, stack size and stack location according
+ **                to application requirements.
+ **
+ **                Set memory bank area and size if external memory is used
+ **
+ **  Target      : STMicroelectronics STM32
+ **
+ **  Distribution: The file is distributed as is, without any warranty
+ **                of any kind.
+ **
+ ******************************************************************************
+ ** @attention
+ **
+ ** Copyright (c) 2023 STMicroelectronics.
+ ** All rights reserved.
+ **
+ ** This software is licensed under terms that can be found in the LICENSE file
+ ** in the root directory of this software component.
+ ** If no LICENSE file comes with this software, it is provided AS-IS.
+ **
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x30000000,    LENGTH = 312K    /* Memory is divided. Actual start is 0x20000000 and actual length is 640K */
+  RAM_NSC    (xrw)    : ORIGIN = 0x3004e000,    LENGTH = 8K    /* Non-Secure Call-able region */
+  FLASH    (rx)    : ORIGIN = 0xc000000,    LENGTH = 1024K    /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(4);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(4);
+  } >RAM_NSC
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h503xx.s

@@ -0,0 +1,548 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h503xx.s
+  * @author    MCD Application Team
+  * @brief     STM32H503xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M33 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m33
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+  * @brief  This is the code that gets called when the processor first
+  *          starts execution following a reset event. Only the absolutely
+  *          necessary set is performed, after which the application
+  *          supplied main() routine is called.
+  * @param  None
+  * @retval : None
+  */
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+	bl	main
+
+LoopForever:
+    b LoopForever
+
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M33.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_AVD_IRQHandler
+	.word	RTC_IRQHandler
+	.word	0
+	.word	TAMP_IRQHandler
+	.word	RAMCFG_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	0
+	.word	GTZC_IRQHandler
+	.word	RCC_IRQHandler
+	.word	0
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	EXTI5_IRQHandler
+	.word	EXTI6_IRQHandler
+	.word	EXTI7_IRQHandler
+	.word	EXTI8_IRQHandler
+	.word	EXTI9_IRQHandler
+	.word	EXTI10_IRQHandler
+	.word	EXTI11_IRQHandler
+	.word	EXTI12_IRQHandler
+	.word	EXTI13_IRQHandler
+	.word	EXTI14_IRQHandler
+	.word	EXTI15_IRQHandler
+	.word	GPDMA1_Channel0_IRQHandler
+	.word	GPDMA1_Channel1_IRQHandler
+	.word	GPDMA1_Channel2_IRQHandler
+	.word	GPDMA1_Channel3_IRQHandler
+	.word	GPDMA1_Channel4_IRQHandler
+	.word	GPDMA1_Channel5_IRQHandler
+	.word	GPDMA1_Channel6_IRQHandler
+	.word	GPDMA1_Channel7_IRQHandler
+	.word	IWDG_IRQHandler
+	.word	0	
+	.word	ADC1_IRQHandler
+	.word	DAC1_IRQHandler
+	.word	FDCAN1_IT0_IRQHandler
+	.word	FDCAN1_IT1_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	0
+	.word	0
+	.word	TIM6_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	SPI3_IRQHandler	
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	0
+	.word	0
+	.word	LPUART1_IRQHandler
+	.word	LPTIM1_IRQHandler
+    .word	0
+    .word	0
+    .word	0
+    .word	0
+    .word	0
+	.word	LPTIM2_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	USB_DRD_FS_IRQHandler
+	.word	CRS_IRQHandler
+    .word	0
+    .word	0
+    .word	0
+    .word	0
+    .word	0
+    .word	0	
+    .word	0	
+    .word	0	
+    .word	0	
+    .word	0	
+    .word	0	
+    .word	0	
+    .word	0	
+    .word	0	
+	.word	GPDMA2_Channel0_IRQHandler
+	.word	GPDMA2_Channel1_IRQHandler
+	.word	GPDMA2_Channel2_IRQHandler
+	.word	GPDMA2_Channel3_IRQHandler
+	.word	GPDMA2_Channel4_IRQHandler
+	.word	GPDMA2_Channel5_IRQHandler
+	.word	GPDMA2_Channel6_IRQHandler
+	.word	GPDMA2_Channel7_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	FPU_IRQHandler
+	.word	ICACHE_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0	
+	.word	DTS_IRQHandler	
+	.word	RNG_IRQHandler
+	.word	0
+	.word	0
+	.word	HASH_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0	
+	.word	I3C1_EV_IRQHandler
+	.word	I3C1_ER_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0	
+	.word	I3C2_EV_IRQHandler
+	.word	I3C2_ER_IRQHandler
+	.word	COMP1_IRQHandler
+
+	.size	g_pfnVectors, .-g_pfnVectors
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+	.weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+	
+	.weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+	.weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+	.weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_AVD_IRQHandler
+	.thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	TAMP_IRQHandler
+	.thumb_set TAMP_IRQHandler,Default_Handler
+
+	.weak	RAMCFG_IRQHandler
+	.thumb_set RAMCFG_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	GTZC_IRQHandler
+	.thumb_set GTZC_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	EXTI5_IRQHandler
+	.thumb_set EXTI5_IRQHandler,Default_Handler
+
+	.weak	EXTI6_IRQHandler
+	.thumb_set EXTI6_IRQHandler,Default_Handler
+
+	.weak	EXTI7_IRQHandler
+	.thumb_set EXTI7_IRQHandler,Default_Handler
+
+	.weak	EXTI8_IRQHandler
+	.thumb_set EXTI8_IRQHandler,Default_Handler
+
+	.weak	EXTI9_IRQHandler
+	.thumb_set EXTI9_IRQHandler,Default_Handler
+
+	.weak	EXTI10_IRQHandler
+	.thumb_set EXTI10_IRQHandler,Default_Handler
+
+	.weak	EXTI11_IRQHandler
+	.thumb_set EXTI11_IRQHandler,Default_Handler
+
+	.weak	EXTI12_IRQHandler
+	.thumb_set EXTI12_IRQHandler,Default_Handler
+
+	.weak	EXTI13_IRQHandler
+	.thumb_set EXTI13_IRQHandler,Default_Handler
+
+	.weak	EXTI14_IRQHandler
+	.thumb_set EXTI14_IRQHandler,Default_Handler
+
+	.weak	EXTI15_IRQHandler
+	.thumb_set EXTI15_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel0_IRQHandler
+	.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel1_IRQHandler
+	.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
+	
+	.weak	GPDMA1_Channel2_IRQHandler
+	.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
+	
+	.weak	GPDMA1_Channel3_IRQHandler
+	.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel4_IRQHandler
+	.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel5_IRQHandler
+	.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel6_IRQHandler
+	.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel7_IRQHandler
+	.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	IWDG_IRQHandler	
+	.thumb_set IWDG_IRQHandler,Default_Handler
+
+	.weak	ADC1_IRQHandler
+	.thumb_set ADC1_IRQHandler,Default_Handler
+
+	.weak	DAC1_IRQHandler
+	.thumb_set DAC1_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT0_IRQHandler
+	.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT1_IRQHandler
+	.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM6_IRQHandler
+	.thumb_set TIM6_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler
+
+	.weak	USB_DRD_FS_IRQHandler
+	.thumb_set USB_DRD_FS_IRQHandler,Default_Handler
+
+	.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel0_IRQHandler
+	.thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel1_IRQHandler
+	.thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel2_IRQHandler
+	.thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel3_IRQHandler
+	.thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel4_IRQHandler
+	.thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel5_IRQHandler
+	.thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel6_IRQHandler
+	.thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel7_IRQHandler
+	.thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler
+
+	.weak	FPU_IRQHandler	
+	.thumb_set FPU_IRQHandler,Default_Handler
+	.weak	ICACHE_IRQHandler	
+	.thumb_set ICACHE_IRQHandler,Default_Handler
+
+	.weak	DTS_IRQHandler	
+	.thumb_set DTS_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	HASH_IRQHandler	
+	.thumb_set HASH_IRQHandler,Default_Handler
+
+	.weak	I3C1_EV_IRQHandler
+	.thumb_set I3C1_EV_IRQHandler,Default_Handler
+
+	.weak	I3C1_ER_IRQHandler	
+	.thumb_set I3C1_ER_IRQHandler,Default_Handler
+
+	.weak	I3C2_EV_IRQHandler
+	.thumb_set I3C2_EV_IRQHandler,Default_Handler
+
+	.weak	I3C2_ER_IRQHandler
+	.thumb_set I3C2_ER_IRQHandler,Default_Handler
+
+	.weak	COMP1_IRQHandler
+	.thumb_set COMP1_IRQHandler,Default_Handler

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h523xx.s

@@ -0,0 +1,634 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h523xx.s
+  * @author    MCD Application Team
+  * @brief     STM32h523xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M33 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m33
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+  * @brief  This is the code that gets called when the processor first
+  *          starts execution following a reset event. Only the absolutely
+  *          necessary set is performed, after which the application
+  *          supplied main() routine is called.
+  * @param  None
+  * @retval : None
+  */
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+
+LoopForever:
+    b LoopForever
+
+  .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32h523xx vector table.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	SecureFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_AVD_IRQHandler
+	.word	RTC_IRQHandler
+	.word	RTC_S_IRQHandler
+	.word	TAMP_IRQHandler
+	.word	RAMCFG_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	FLASH_S_IRQHandler
+	.word	GTZC_IRQHandler
+	.word	RCC_IRQHandler
+	.word	RCC_S_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	EXTI5_IRQHandler
+	.word	EXTI6_IRQHandler
+	.word	EXTI7_IRQHandler
+	.word	EXTI8_IRQHandler
+	.word	EXTI9_IRQHandler
+	.word	EXTI10_IRQHandler
+	.word	EXTI11_IRQHandler
+	.word	EXTI12_IRQHandler
+	.word	EXTI13_IRQHandler
+	.word	EXTI14_IRQHandler
+	.word	EXTI15_IRQHandler
+	.word	GPDMA1_Channel0_IRQHandler
+	.word	GPDMA1_Channel1_IRQHandler
+	.word	GPDMA1_Channel2_IRQHandler
+	.word	GPDMA1_Channel3_IRQHandler
+	.word	GPDMA1_Channel4_IRQHandler
+	.word	GPDMA1_Channel5_IRQHandler
+	.word	GPDMA1_Channel6_IRQHandler
+	.word	GPDMA1_Channel7_IRQHandler
+	.word	IWDG_IRQHandler
+	.word	0
+	.word	ADC1_IRQHandler
+	.word	DAC1_IRQHandler
+	.word	FDCAN1_IT0_IRQHandler
+	.word	FDCAN1_IT1_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	TIM5_IRQHandler
+	.word	TIM6_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	ADC2_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	TIM15_IRQHandler
+	.word	0
+	.word	0
+	.word	USB_DRD_FS_IRQHandler
+	.word	CRS_IRQHandler
+	.word	UCPD1_IRQHandler
+	.word	FMC_IRQHandler
+	.word	OCTOSPI1_IRQHandler
+	.word	SDMMC1_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SPI4_IRQHandler
+	.word	0
+	.word	0
+	.word	USART6_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	GPDMA2_Channel0_IRQHandler
+	.word	GPDMA2_Channel1_IRQHandler
+	.word	GPDMA2_Channel2_IRQHandler
+	.word	GPDMA2_Channel3_IRQHandler
+	.word	GPDMA2_Channel4_IRQHandler
+	.word	GPDMA2_Channel5_IRQHandler
+	.word	GPDMA2_Channel6_IRQHandler
+	.word	GPDMA2_Channel7_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	FPU_IRQHandler
+	.word	ICACHE_IRQHandler
+	.word	DCACHE1_IRQHandler
+	.word	0
+	.word	0
+	.word	DCMI_PSSI_IRQHandler
+	.word	FDCAN2_IT0_IRQHandler
+	.word	FDCAN2_IT1_IRQHandler
+	.word	0
+	.word	0
+	.word	DTS_IRQHandler
+	.word	RNG_IRQHandler
+	.word	0
+	.word	0
+	.word	HASH_IRQHandler
+	.word	0
+	.word	CEC_IRQHandler
+	.word	TIM12_IRQHandler
+	.word	0
+	.word	0
+	.word	I3C1_EV_IRQHandler
+	.word	I3C1_ER_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	I3C2_EV_IRQHandler
+	.word	I3C2_ER_IRQHandler
+
+	.size	g_pfnVectors, .-g_pfnVectors
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+	.weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+	.weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+	.weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+	.weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SecureFault_Handler
+	.thumb_set SecureFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_AVD_IRQHandler
+	.thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	RTC_S_IRQHandler
+	.thumb_set RTC_S_IRQHandler,Default_Handler
+
+	.weak	TAMP_IRQHandler
+	.thumb_set TAMP_IRQHandler,Default_Handler
+
+	.weak	RAMCFG_IRQHandler
+	.thumb_set RAMCFG_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	FLASH_S_IRQHandler
+	.thumb_set FLASH_S_IRQHandler,Default_Handler
+
+	.weak	GTZC_IRQHandler
+	.thumb_set GTZC_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	RCC_S_IRQHandler
+	.thumb_set RCC_S_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	EXTI5_IRQHandler
+	.thumb_set EXTI5_IRQHandler,Default_Handler
+
+	.weak	EXTI6_IRQHandler
+	.thumb_set EXTI6_IRQHandler,Default_Handler
+
+	.weak	EXTI7_IRQHandler
+	.thumb_set EXTI7_IRQHandler,Default_Handler
+
+	.weak	EXTI8_IRQHandler
+	.thumb_set EXTI8_IRQHandler,Default_Handler
+
+	.weak	EXTI9_IRQHandler
+	.thumb_set EXTI9_IRQHandler,Default_Handler
+
+	.weak	EXTI10_IRQHandler
+	.thumb_set EXTI10_IRQHandler,Default_Handler
+
+	.weak	EXTI11_IRQHandler
+	.thumb_set EXTI11_IRQHandler,Default_Handler
+
+	.weak	EXTI12_IRQHandler
+	.thumb_set EXTI12_IRQHandler,Default_Handler
+
+	.weak	EXTI13_IRQHandler
+	.thumb_set EXTI13_IRQHandler,Default_Handler
+
+	.weak	EXTI14_IRQHandler
+	.thumb_set EXTI14_IRQHandler,Default_Handler
+
+	.weak	EXTI15_IRQHandler
+	.thumb_set EXTI15_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel0_IRQHandler
+	.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel1_IRQHandler
+	.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel2_IRQHandler
+	.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel3_IRQHandler
+	.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel4_IRQHandler
+	.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel5_IRQHandler
+	.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel6_IRQHandler
+	.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel7_IRQHandler
+	.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	IWDG_IRQHandler
+	.thumb_set IWDG_IRQHandler,Default_Handler
+
+	.weak	ADC1_IRQHandler
+	.thumb_set ADC1_IRQHandler,Default_Handler
+
+	.weak	DAC1_IRQHandler
+	.thumb_set DAC1_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT0_IRQHandler
+	.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT1_IRQHandler
+	.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	TIM6_IRQHandler
+	.thumb_set TIM6_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC2_IRQHandler
+	.thumb_set ADC2_IRQHandler,Default_Handler
+
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler
+
+	.weak	TIM15_IRQHandler
+	.thumb_set TIM15_IRQHandler,Default_Handler
+
+	.weak	USB_DRD_FS_IRQHandler
+	.thumb_set USB_DRD_FS_IRQHandler,Default_Handler
+
+	.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+
+	.weak	UCPD1_IRQHandler
+	.thumb_set UCPD1_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	OCTOSPI1_IRQHandler
+	.thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+	.weak	SPI4_IRQHandler
+	.thumb_set SPI4_IRQHandler,Default_Handler
+
+	.weak	USART6_IRQHandler
+	.thumb_set USART6_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel0_IRQHandler
+	.thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel1_IRQHandler
+	.thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel2_IRQHandler
+	.thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel3_IRQHandler
+	.thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel4_IRQHandler
+	.thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel5_IRQHandler
+	.thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel6_IRQHandler
+	.thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel7_IRQHandler
+	.thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler
+
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+
+	.weak	ICACHE_IRQHandler
+	.thumb_set ICACHE_IRQHandler,Default_Handler
+
+	.weak	DCACHE1_IRQHandler
+	.thumb_set DCACHE1_IRQHandler,Default_Handler
+
+	.weak	DCMI_PSSI_IRQHandler
+	.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+	.weak	FDCAN2_IT0_IRQHandler
+	.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN2_IT1_IRQHandler
+	.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+	.weak	DTS_IRQHandler
+	.thumb_set DTS_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	HASH_IRQHandler
+	.thumb_set HASH_IRQHandler,Default_Handler
+
+	.weak	CEC_IRQHandler
+	.thumb_set CEC_IRQHandler,Default_Handler
+
+	.weak	TIM12_IRQHandler
+	.thumb_set TIM12_IRQHandler,Default_Handler
+
+	.weak	I3C1_EV_IRQHandler
+	.thumb_set I3C1_EV_IRQHandler,Default_Handler
+
+	.weak	I3C1_ER_IRQHandler
+	.thumb_set I3C1_ER_IRQHandler,Default_Handler
+
+	.weak	I3C2_EV_IRQHandler
+	.thumb_set I3C2_EV_IRQHandler,Default_Handler
+
+	.weak	I3C2_ER_IRQHandler
+	.thumb_set I3C2_ER_IRQHandler,Default_Handler

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h533xx.s

@@ -0,0 +1,646 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h533xx.s
+  * @author    MCD Application Team
+  * @brief     STM32h533xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M33 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m33
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+  * @brief  This is the code that gets called when the processor first
+  *          starts execution following a reset event. Only the absolutely
+  *          necessary set is performed, after which the application
+  *          supplied main() routine is called.
+  * @param  None
+  * @retval : None
+  */
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+
+LoopForever:
+    b LoopForever
+
+  .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32h533xx vector table.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	SecureFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_AVD_IRQHandler
+	.word	RTC_IRQHandler
+	.word	RTC_S_IRQHandler
+	.word	TAMP_IRQHandler
+	.word	RAMCFG_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	FLASH_S_IRQHandler
+	.word	GTZC_IRQHandler
+	.word	RCC_IRQHandler
+	.word	RCC_S_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	EXTI5_IRQHandler
+	.word	EXTI6_IRQHandler
+	.word	EXTI7_IRQHandler
+	.word	EXTI8_IRQHandler
+	.word	EXTI9_IRQHandler
+	.word	EXTI10_IRQHandler
+	.word	EXTI11_IRQHandler
+	.word	EXTI12_IRQHandler
+	.word	EXTI13_IRQHandler
+	.word	EXTI14_IRQHandler
+	.word	EXTI15_IRQHandler
+	.word	GPDMA1_Channel0_IRQHandler
+	.word	GPDMA1_Channel1_IRQHandler
+	.word	GPDMA1_Channel2_IRQHandler
+	.word	GPDMA1_Channel3_IRQHandler
+	.word	GPDMA1_Channel4_IRQHandler
+	.word	GPDMA1_Channel5_IRQHandler
+	.word	GPDMA1_Channel6_IRQHandler
+	.word	GPDMA1_Channel7_IRQHandler
+	.word	IWDG_IRQHandler
+	.word	SAES_IRQHandler
+	.word	ADC1_IRQHandler
+	.word	DAC1_IRQHandler
+	.word	FDCAN1_IT0_IRQHandler
+	.word	FDCAN1_IT1_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	TIM5_IRQHandler
+	.word	TIM6_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	ADC2_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	TIM15_IRQHandler
+	.word	0
+	.word	0
+	.word	USB_DRD_FS_IRQHandler
+	.word	CRS_IRQHandler
+	.word	UCPD1_IRQHandler
+	.word	FMC_IRQHandler
+	.word	OCTOSPI1_IRQHandler
+	.word	SDMMC1_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SPI4_IRQHandler
+	.word	0
+	.word	0
+	.word	USART6_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	GPDMA2_Channel0_IRQHandler
+	.word	GPDMA2_Channel1_IRQHandler
+	.word	GPDMA2_Channel2_IRQHandler
+	.word	GPDMA2_Channel3_IRQHandler
+	.word	GPDMA2_Channel4_IRQHandler
+	.word	GPDMA2_Channel5_IRQHandler
+	.word	GPDMA2_Channel6_IRQHandler
+	.word	GPDMA2_Channel7_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	FPU_IRQHandler
+	.word	ICACHE_IRQHandler
+	.word	DCACHE1_IRQHandler
+	.word	0
+	.word	0
+	.word	DCMI_PSSI_IRQHandler
+	.word	FDCAN2_IT0_IRQHandler
+	.word	FDCAN2_IT1_IRQHandler
+	.word	0
+	.word	0
+	.word	DTS_IRQHandler
+	.word	RNG_IRQHandler
+	.word	OTFDEC1_IRQHandler
+	.word	AES_IRQHandler
+	.word	HASH_IRQHandler
+	.word	PKA_IRQHandler
+	.word	CEC_IRQHandler
+	.word	TIM12_IRQHandler
+	.word	0
+	.word	0
+	.word	I3C1_EV_IRQHandler
+	.word	I3C1_ER_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	I3C2_EV_IRQHandler
+	.word	I3C2_ER_IRQHandler
+
+	.size	g_pfnVectors, .-g_pfnVectors
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+	.weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+	.weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+	.weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+	.weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SecureFault_Handler
+	.thumb_set SecureFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_AVD_IRQHandler
+	.thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	RTC_S_IRQHandler
+	.thumb_set RTC_S_IRQHandler,Default_Handler
+
+	.weak	TAMP_IRQHandler
+	.thumb_set TAMP_IRQHandler,Default_Handler
+
+	.weak	RAMCFG_IRQHandler
+	.thumb_set RAMCFG_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	FLASH_S_IRQHandler
+	.thumb_set FLASH_S_IRQHandler,Default_Handler
+
+	.weak	GTZC_IRQHandler
+	.thumb_set GTZC_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	RCC_S_IRQHandler
+	.thumb_set RCC_S_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	EXTI5_IRQHandler
+	.thumb_set EXTI5_IRQHandler,Default_Handler
+
+	.weak	EXTI6_IRQHandler
+	.thumb_set EXTI6_IRQHandler,Default_Handler
+
+	.weak	EXTI7_IRQHandler
+	.thumb_set EXTI7_IRQHandler,Default_Handler
+
+	.weak	EXTI8_IRQHandler
+	.thumb_set EXTI8_IRQHandler,Default_Handler
+
+	.weak	EXTI9_IRQHandler
+	.thumb_set EXTI9_IRQHandler,Default_Handler
+
+	.weak	EXTI10_IRQHandler
+	.thumb_set EXTI10_IRQHandler,Default_Handler
+
+	.weak	EXTI11_IRQHandler
+	.thumb_set EXTI11_IRQHandler,Default_Handler
+
+	.weak	EXTI12_IRQHandler
+	.thumb_set EXTI12_IRQHandler,Default_Handler
+
+	.weak	EXTI13_IRQHandler
+	.thumb_set EXTI13_IRQHandler,Default_Handler
+
+	.weak	EXTI14_IRQHandler
+	.thumb_set EXTI14_IRQHandler,Default_Handler
+
+	.weak	EXTI15_IRQHandler
+	.thumb_set EXTI15_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel0_IRQHandler
+	.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel1_IRQHandler
+	.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel2_IRQHandler
+	.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel3_IRQHandler
+	.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel4_IRQHandler
+	.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel5_IRQHandler
+	.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel6_IRQHandler
+	.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel7_IRQHandler
+	.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	IWDG_IRQHandler
+	.thumb_set IWDG_IRQHandler,Default_Handler
+
+	.weak	SAES_IRQHandler
+	.thumb_set SAES_IRQHandler,Default_Handler
+
+	.weak	ADC1_IRQHandler
+	.thumb_set ADC1_IRQHandler,Default_Handler
+
+	.weak	DAC1_IRQHandler
+	.thumb_set DAC1_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT0_IRQHandler
+	.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT1_IRQHandler
+	.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	TIM6_IRQHandler
+	.thumb_set TIM6_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC2_IRQHandler
+	.thumb_set ADC2_IRQHandler,Default_Handler
+
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler
+
+	.weak	TIM15_IRQHandler
+	.thumb_set TIM15_IRQHandler,Default_Handler
+
+	.weak	USB_DRD_FS_IRQHandler
+	.thumb_set USB_DRD_FS_IRQHandler,Default_Handler
+
+	.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+
+	.weak	UCPD1_IRQHandler
+	.thumb_set UCPD1_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	OCTOSPI1_IRQHandler
+	.thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+	.weak	SPI4_IRQHandler
+	.thumb_set SPI4_IRQHandler,Default_Handler
+
+	.weak	USART6_IRQHandler
+	.thumb_set USART6_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel0_IRQHandler
+	.thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel1_IRQHandler
+	.thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel2_IRQHandler
+	.thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel3_IRQHandler
+	.thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel4_IRQHandler
+	.thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel5_IRQHandler
+	.thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel6_IRQHandler
+	.thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel7_IRQHandler
+	.thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler
+
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+
+	.weak	ICACHE_IRQHandler
+	.thumb_set ICACHE_IRQHandler,Default_Handler
+
+	.weak	DCACHE1_IRQHandler
+	.thumb_set DCACHE1_IRQHandler,Default_Handler
+
+	.weak	DCMI_PSSI_IRQHandler
+	.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+	.weak	FDCAN2_IT0_IRQHandler
+	.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN2_IT1_IRQHandler
+	.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+	.weak	DTS_IRQHandler
+	.thumb_set DTS_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	OTFDEC1_IRQHandler
+	.thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+	.weak	AES_IRQHandler
+	.thumb_set AES_IRQHandler,Default_Handler
+
+	.weak	HASH_IRQHandler
+	.thumb_set HASH_IRQHandler,Default_Handler
+
+	.weak	PKA_IRQHandler
+	.thumb_set PKA_IRQHandler,Default_Handler
+
+	.weak	CEC_IRQHandler
+	.thumb_set CEC_IRQHandler,Default_Handler
+
+	.weak	TIM12_IRQHandler
+	.thumb_set TIM12_IRQHandler,Default_Handler
+
+	.weak	I3C1_EV_IRQHandler
+	.thumb_set I3C1_EV_IRQHandler,Default_Handler
+
+	.weak	I3C1_ER_IRQHandler
+	.thumb_set I3C1_ER_IRQHandler,Default_Handler
+
+	.weak	I3C2_EV_IRQHandler
+	.thumb_set I3C2_EV_IRQHandler,Default_Handler
+
+	.weak	I3C2_ER_IRQHandler
+	.thumb_set I3C2_ER_IRQHandler,Default_Handler

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h562xx.s

@@ -0,0 +1,681 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h573xx.s
+  * @author    MCD Application Team
+  * @brief     STM32H563xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M33 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m33
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+  * @brief  This is the code that gets called when the processor first
+  *          starts execution following a reset event. Only the absolutely
+  *          necessary set is performed, after which the application
+  *          supplied main() routine is called.
+  * @param  None
+  * @retval : None
+  */
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+	bl	main
+
+LoopForever:
+    b LoopForever
+
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M33.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	SecureFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_AVD_IRQHandler
+	.word	RTC_IRQHandler
+	.word	RTC_S_IRQHandler
+	.word	TAMP_IRQHandler
+	.word	RAMCFG_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	FLASH_S_IRQHandler
+	.word	GTZC_IRQHandler
+	.word	RCC_IRQHandler
+	.word	RCC_S_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	EXTI5_IRQHandler
+	.word	EXTI6_IRQHandler
+	.word	EXTI7_IRQHandler
+	.word	EXTI8_IRQHandler
+	.word	EXTI9_IRQHandler
+	.word	EXTI10_IRQHandler
+	.word	EXTI11_IRQHandler
+	.word	EXTI12_IRQHandler
+	.word	EXTI13_IRQHandler
+	.word	EXTI14_IRQHandler
+	.word	EXTI15_IRQHandler
+	.word	GPDMA1_Channel0_IRQHandler
+	.word	GPDMA1_Channel1_IRQHandler
+	.word	GPDMA1_Channel2_IRQHandler
+	.word	GPDMA1_Channel3_IRQHandler
+	.word	GPDMA1_Channel4_IRQHandler
+	.word	GPDMA1_Channel5_IRQHandler
+	.word	GPDMA1_Channel6_IRQHandler
+	.word	GPDMA1_Channel7_IRQHandler
+	.word	IWDG_IRQHandler
+	.word	0
+	.word	ADC1_IRQHandler
+	.word	DAC1_IRQHandler
+	.word	FDCAN1_IT0_IRQHandler
+	.word	FDCAN1_IT1_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	TIM5_IRQHandler
+	.word	TIM6_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	ADC2_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	TIM15_IRQHandler
+	.word	TIM16_IRQHandler
+	.word	TIM17_IRQHandler
+	.word	USB_DRD_FS_IRQHandler
+	.word	CRS_IRQHandler
+	.word	UCPD1_IRQHandler
+	.word	FMC_IRQHandler
+	.word	OCTOSPI1_IRQHandler
+	.word	SDMMC1_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SPI4_IRQHandler
+	.word	SPI5_IRQHandler
+	.word	SPI6_IRQHandler
+	.word	USART6_IRQHandler
+	.word	USART10_IRQHandler
+	.word	USART11_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	SAI2_IRQHandler
+	.word	GPDMA2_Channel0_IRQHandler
+	.word	GPDMA2_Channel1_IRQHandler
+	.word	GPDMA2_Channel2_IRQHandler
+	.word	GPDMA2_Channel3_IRQHandler
+	.word	GPDMA2_Channel4_IRQHandler
+	.word	GPDMA2_Channel5_IRQHandler
+	.word	GPDMA2_Channel6_IRQHandler
+	.word	GPDMA2_Channel7_IRQHandler
+	.word	UART7_IRQHandler
+	.word	UART8_IRQHandler
+	.word	UART9_IRQHandler
+	.word	UART12_IRQHandler
+	.word	0
+	.word	FPU_IRQHandler
+	.word	ICACHE_IRQHandler
+	.word	DCACHE1_IRQHandler
+	.word	0
+	.word	0
+	.word	DCMI_PSSI_IRQHandler
+	.word	0
+	.word	0
+	.word	CORDIC_IRQHandler
+ 	.word	FMAC_IRQHandler
+	.word	DTS_IRQHandler
+	.word	RNG_IRQHandler
+	.word	0
+	.word	0
+	.word	HASH_IRQHandler
+	.word	0
+	.word	CEC_IRQHandler
+	.word	TIM12_IRQHandler
+	.word	TIM13_IRQHandler
+	.word	TIM14_IRQHandler
+	.word	I3C1_EV_IRQHandler
+	.word	I3C1_ER_IRQHandler
+	.word	I2C4_EV_IRQHandler
+	.word	I2C4_ER_IRQHandler
+	.word	LPTIM3_IRQHandler
+	.word	LPTIM4_IRQHandler
+	.word	LPTIM5_IRQHandler
+	.word	LPTIM6_IRQHandler
+
+	.size	g_pfnVectors, .-g_pfnVectors
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+	.weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+	.weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+	.weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+	.weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SecureFault_Handler
+	.thumb_set SecureFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_AVD_IRQHandler
+	.thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	RTC_S_IRQHandler
+	.thumb_set RTC_S_IRQHandler,Default_Handler
+
+	.weak	TAMP_IRQHandler
+	.thumb_set TAMP_IRQHandler,Default_Handler
+
+	.weak	RAMCFG_IRQHandler
+	.thumb_set RAMCFG_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	FLASH_S_IRQHandler
+	.thumb_set FLASH_S_IRQHandler,Default_Handler
+
+	.weak	GTZC_IRQHandler
+	.thumb_set GTZC_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	RCC_S_IRQHandler
+	.thumb_set RCC_S_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	EXTI5_IRQHandler
+	.thumb_set EXTI5_IRQHandler,Default_Handler
+
+	.weak	EXTI6_IRQHandler
+	.thumb_set EXTI6_IRQHandler,Default_Handler
+
+	.weak	EXTI7_IRQHandler
+	.thumb_set EXTI7_IRQHandler,Default_Handler
+
+	.weak	EXTI8_IRQHandler
+	.thumb_set EXTI8_IRQHandler,Default_Handler
+
+	.weak	EXTI9_IRQHandler
+	.thumb_set EXTI9_IRQHandler,Default_Handler
+
+	.weak	EXTI10_IRQHandler
+	.thumb_set EXTI10_IRQHandler,Default_Handler
+
+	.weak	EXTI11_IRQHandler
+	.thumb_set EXTI11_IRQHandler,Default_Handler
+
+	.weak	EXTI12_IRQHandler
+	.thumb_set EXTI12_IRQHandler,Default_Handler
+
+	.weak	EXTI13_IRQHandler
+	.thumb_set EXTI13_IRQHandler,Default_Handler
+
+	.weak	EXTI14_IRQHandler
+	.thumb_set EXTI14_IRQHandler,Default_Handler
+
+	.weak	EXTI15_IRQHandler
+	.thumb_set EXTI15_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel0_IRQHandler
+	.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel1_IRQHandler
+	.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel2_IRQHandler
+	.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel3_IRQHandler
+	.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel4_IRQHandler
+	.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel5_IRQHandler
+	.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel6_IRQHandler
+	.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel7_IRQHandler
+	.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	IWDG_IRQHandler
+	.thumb_set IWDG_IRQHandler,Default_Handler
+
+	.weak	ADC1_IRQHandler
+	.thumb_set ADC1_IRQHandler,Default_Handler
+
+	.weak	DAC1_IRQHandler
+	.thumb_set DAC1_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT0_IRQHandler
+	.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT1_IRQHandler
+	.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	TIM6_IRQHandler
+	.thumb_set TIM6_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC2_IRQHandler
+	.thumb_set ADC2_IRQHandler,Default_Handler
+
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler
+
+	.weak	TIM15_IRQHandler
+	.thumb_set TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM16_IRQHandler
+	.thumb_set TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM17_IRQHandler
+	.thumb_set TIM17_IRQHandler,Default_Handler
+
+	.weak	USB_DRD_FS_IRQHandler
+	.thumb_set USB_DRD_FS_IRQHandler,Default_Handler
+
+	.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+
+	.weak	UCPD1_IRQHandler
+	.thumb_set UCPD1_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	OCTOSPI1_IRQHandler
+	.thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+	.weak	SPI4_IRQHandler
+	.thumb_set SPI4_IRQHandler,Default_Handler
+
+	.weak	SPI5_IRQHandler
+	.thumb_set SPI5_IRQHandler,Default_Handler
+
+	.weak	SPI6_IRQHandler
+	.thumb_set SPI6_IRQHandler,Default_Handler
+
+	.weak	USART6_IRQHandler
+	.thumb_set USART6_IRQHandler,Default_Handler
+
+	.weak	USART10_IRQHandler
+	.thumb_set USART10_IRQHandler,Default_Handler
+
+	.weak	USART11_IRQHandler
+	.thumb_set USART11_IRQHandler,Default_Handler
+
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+
+	.weak	SAI2_IRQHandler
+	.thumb_set SAI2_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel0_IRQHandler
+	.thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel1_IRQHandler
+	.thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel2_IRQHandler
+	.thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel3_IRQHandler
+	.thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel4_IRQHandler
+	.thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel5_IRQHandler
+	.thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel6_IRQHandler
+	.thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel7_IRQHandler
+	.thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler
+
+	.weak	UART7_IRQHandler
+	.thumb_set UART7_IRQHandler,Default_Handler
+
+	.weak	UART8_IRQHandler
+	.thumb_set UART8_IRQHandler,Default_Handler
+
+	.weak	UART9_IRQHandler
+	.thumb_set UART9_IRQHandler,Default_Handler
+
+	.weak	UART12_IRQHandler
+	.thumb_set UART12_IRQHandler,Default_Handler
+
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+
+	.weak	ICACHE_IRQHandler
+	.thumb_set ICACHE_IRQHandler,Default_Handler
+
+	.weak	DCACHE1_IRQHandler
+	.thumb_set DCACHE1_IRQHandler,Default_Handler
+
+	.weak	DCMI_PSSI_IRQHandler
+	.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+	.weak	CORDIC_IRQHandler
+	.thumb_set CORDIC_IRQHandler,Default_Handler
+
+	.weak	FMAC_IRQHandler
+	.thumb_set FMAC_IRQHandler,Default_Handler
+
+	.weak	DTS_IRQHandler
+	.thumb_set DTS_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	HASH_IRQHandler
+	.thumb_set HASH_IRQHandler,Default_Handler
+
+	.weak	CEC_IRQHandler
+	.thumb_set CEC_IRQHandler,Default_Handler
+
+	.weak	TIM12_IRQHandler
+	.thumb_set TIM12_IRQHandler,Default_Handler
+
+	.weak	TIM13_IRQHandler
+	.thumb_set TIM13_IRQHandler,Default_Handler
+
+	.weak	TIM14_IRQHandler
+	.thumb_set TIM14_IRQHandler,Default_Handler
+
+	.weak	I3C1_EV_IRQHandler
+	.thumb_set I3C1_EV_IRQHandler,Default_Handler
+
+	.weak	I3C1_ER_IRQHandler
+	.thumb_set I3C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C4_EV_IRQHandler
+	.thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+	.weak	I2C4_ER_IRQHandler
+	.thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+	.weak	LPTIM3_IRQHandler
+	.thumb_set LPTIM3_IRQHandler,Default_Handler
+
+	.weak	LPTIM4_IRQHandler
+	.thumb_set LPTIM4_IRQHandler,Default_Handler
+
+	.weak	LPTIM5_IRQHandler
+	.thumb_set LPTIM5_IRQHandler,Default_Handler
+
+	.weak	LPTIM6_IRQHandler
+	.thumb_set LPTIM6_IRQHandler,Default_Handler

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h563xx.s

@@ -0,0 +1,697 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h563xx.s
+  * @author    MCD Application Team
+  * @brief     STM32H563xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m33
+	.fpu softvfp
+	.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+  * @brief  This is the code that gets called when the processor first
+  *          starts execution following a reset event. Only the absolutely
+  *          necessary set is performed, after which the application
+  *          supplied main() routine is called.
+  * @param  None
+  * @retval : None
+  */
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+
+LoopForever:
+    b LoopForever
+
+  .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32H563xx vector table.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	SecureFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_AVD_IRQHandler
+	.word	RTC_IRQHandler
+	.word	RTC_S_IRQHandler
+	.word	TAMP_IRQHandler
+	.word	RAMCFG_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	FLASH_S_IRQHandler
+	.word	GTZC_IRQHandler
+	.word	RCC_IRQHandler
+	.word	RCC_S_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	EXTI5_IRQHandler
+	.word	EXTI6_IRQHandler
+	.word	EXTI7_IRQHandler
+	.word	EXTI8_IRQHandler
+	.word	EXTI9_IRQHandler
+	.word	EXTI10_IRQHandler
+	.word	EXTI11_IRQHandler
+	.word	EXTI12_IRQHandler
+	.word	EXTI13_IRQHandler
+	.word	EXTI14_IRQHandler
+	.word	EXTI15_IRQHandler
+	.word	GPDMA1_Channel0_IRQHandler
+	.word	GPDMA1_Channel1_IRQHandler
+	.word	GPDMA1_Channel2_IRQHandler
+	.word	GPDMA1_Channel3_IRQHandler
+	.word	GPDMA1_Channel4_IRQHandler
+	.word	GPDMA1_Channel5_IRQHandler
+	.word	GPDMA1_Channel6_IRQHandler
+	.word	GPDMA1_Channel7_IRQHandler
+	.word	IWDG_IRQHandler
+	.word	0
+	.word	ADC1_IRQHandler
+	.word	DAC1_IRQHandler
+	.word	FDCAN1_IT0_IRQHandler
+	.word	FDCAN1_IT1_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	TIM5_IRQHandler
+	.word	TIM6_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	LPTIM1_IRQHandler
+    .word	TIM8_BRK_IRQHandler
+    .word	TIM8_UP_IRQHandler
+    .word	TIM8_TRG_COM_IRQHandler
+    .word	TIM8_CC_IRQHandler
+    .word	ADC2_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	TIM15_IRQHandler
+	.word	TIM16_IRQHandler
+	.word	TIM17_IRQHandler
+	.word	USB_DRD_FS_IRQHandler
+	.word	CRS_IRQHandler
+	.word	UCPD1_IRQHandler
+	.word	FMC_IRQHandler
+	.word	OCTOSPI1_IRQHandler
+	.word	SDMMC1_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SPI4_IRQHandler
+	.word	SPI5_IRQHandler
+	.word	SPI6_IRQHandler
+	.word	USART6_IRQHandler
+	.word	USART10_IRQHandler
+	.word	USART11_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	SAI2_IRQHandler
+	.word	GPDMA2_Channel0_IRQHandler
+	.word	GPDMA2_Channel1_IRQHandler
+	.word	GPDMA2_Channel2_IRQHandler
+	.word	GPDMA2_Channel3_IRQHandler
+	.word	GPDMA2_Channel4_IRQHandler
+	.word	GPDMA2_Channel5_IRQHandler
+	.word	GPDMA2_Channel6_IRQHandler
+	.word	GPDMA2_Channel7_IRQHandler
+	.word	UART7_IRQHandler
+	.word	UART8_IRQHandler
+	.word	UART9_IRQHandler
+	.word	UART12_IRQHandler
+	.word	SDMMC2_IRQHandler
+	.word	FPU_IRQHandler
+	.word	ICACHE_IRQHandler
+	.word	DCACHE1_IRQHandler
+	.word	ETH_IRQHandler
+	.word	ETH_WKUP_IRQHandler
+	.word	DCMI_PSSI_IRQHandler
+	.word	FDCAN2_IT0_IRQHandler
+	.word	FDCAN2_IT1_IRQHandler
+	.word	CORDIC_IRQHandler
+ 	.word   FMAC_IRQHandler
+	.word	DTS_IRQHandler
+	.word	RNG_IRQHandler
+	.word	0
+	.word	0
+	.word	HASH_IRQHandler
+	.word	0
+	.word	CEC_IRQHandler
+	.word	TIM12_IRQHandler
+	.word	TIM13_IRQHandler
+	.word	TIM14_IRQHandler
+	.word	I3C1_EV_IRQHandler
+	.word	I3C1_ER_IRQHandler
+	.word	I2C4_EV_IRQHandler
+	.word	I2C4_ER_IRQHandler
+	.word	LPTIM3_IRQHandler
+	.word	LPTIM4_IRQHandler
+	.word	LPTIM5_IRQHandler
+	.word	LPTIM6_IRQHandler
+
+  .size g_pfnVectors, .-g_pfnVectors
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+	.weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+	.weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+	.weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+	.weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SecureFault_Handler
+	.thumb_set SecureFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_AVD_IRQHandler
+	.thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	RTC_S_IRQHandler
+	.thumb_set RTC_S_IRQHandler,Default_Handler
+
+	.weak	TAMP_IRQHandler
+	.thumb_set TAMP_IRQHandler,Default_Handler
+
+	.weak	RAMCFG_IRQHandler
+	.thumb_set RAMCFG_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	FLASH_S_IRQHandler
+	.thumb_set FLASH_S_IRQHandler,Default_Handler
+
+	.weak	GTZC_IRQHandler
+	.thumb_set GTZC_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	RCC_S_IRQHandler
+	.thumb_set RCC_S_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	EXTI5_IRQHandler
+	.thumb_set EXTI5_IRQHandler,Default_Handler
+
+	.weak	EXTI6_IRQHandler
+	.thumb_set EXTI6_IRQHandler,Default_Handler
+
+	.weak	EXTI7_IRQHandler
+	.thumb_set EXTI7_IRQHandler,Default_Handler
+
+	.weak	EXTI8_IRQHandler
+	.thumb_set EXTI8_IRQHandler,Default_Handler
+
+	.weak	EXTI9_IRQHandler
+	.thumb_set EXTI9_IRQHandler,Default_Handler
+
+	.weak	EXTI10_IRQHandler
+	.thumb_set EXTI10_IRQHandler,Default_Handler
+
+	.weak	EXTI11_IRQHandler
+	.thumb_set EXTI11_IRQHandler,Default_Handler
+
+	.weak	EXTI12_IRQHandler
+	.thumb_set EXTI12_IRQHandler,Default_Handler
+
+	.weak	EXTI13_IRQHandler
+	.thumb_set EXTI13_IRQHandler,Default_Handler
+
+	.weak	EXTI14_IRQHandler
+	.thumb_set EXTI14_IRQHandler,Default_Handler
+
+	.weak	EXTI15_IRQHandler
+	.thumb_set EXTI15_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel0_IRQHandler
+	.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel1_IRQHandler
+	.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel2_IRQHandler
+	.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel3_IRQHandler
+	.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel4_IRQHandler
+	.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel5_IRQHandler
+	.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel6_IRQHandler
+	.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel7_IRQHandler
+	.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	IWDG_IRQHandler
+	.thumb_set IWDG_IRQHandler,Default_Handler
+
+	.weak	ADC1_IRQHandler
+	.thumb_set ADC1_IRQHandler,Default_Handler
+
+	.weak	DAC1_IRQHandler
+	.thumb_set DAC1_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT0_IRQHandler
+	.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT1_IRQHandler
+	.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	TIM6_IRQHandler
+	.thumb_set TIM6_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC2_IRQHandler
+	.thumb_set ADC2_IRQHandler,Default_Handler
+
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler
+
+	.weak	TIM15_IRQHandler
+	.thumb_set TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM16_IRQHandler
+	.thumb_set TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM17_IRQHandler
+	.thumb_set TIM17_IRQHandler,Default_Handler
+
+	.weak	USB_DRD_FS_IRQHandler
+	.thumb_set USB_DRD_FS_IRQHandler,Default_Handler
+
+	.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+
+	.weak	UCPD1_IRQHandler
+	.thumb_set UCPD1_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	OCTOSPI1_IRQHandler
+	.thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+	.weak	SPI4_IRQHandler
+	.thumb_set SPI4_IRQHandler,Default_Handler
+
+	.weak	SPI5_IRQHandler
+	.thumb_set SPI5_IRQHandler,Default_Handler
+
+	.weak	SPI6_IRQHandler
+	.thumb_set SPI6_IRQHandler,Default_Handler
+
+	.weak	USART6_IRQHandler
+	.thumb_set USART6_IRQHandler,Default_Handler
+
+	.weak	USART10_IRQHandler
+	.thumb_set USART10_IRQHandler,Default_Handler
+
+	.weak	USART11_IRQHandler
+	.thumb_set USART11_IRQHandler,Default_Handler
+
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+
+	.weak	SAI2_IRQHandler
+	.thumb_set SAI2_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel0_IRQHandler
+	.thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel1_IRQHandler
+	.thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel2_IRQHandler
+	.thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel3_IRQHandler
+	.thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel4_IRQHandler
+	.thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel5_IRQHandler
+	.thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel6_IRQHandler
+	.thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel7_IRQHandler
+	.thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler
+
+	.weak	UART7_IRQHandler
+	.thumb_set UART7_IRQHandler,Default_Handler
+
+	.weak	UART8_IRQHandler
+	.thumb_set UART8_IRQHandler,Default_Handler
+
+	.weak	UART9_IRQHandler
+	.thumb_set UART9_IRQHandler,Default_Handler
+
+	.weak	UART12_IRQHandler
+	.thumb_set UART12_IRQHandler,Default_Handler
+
+	.weak	SDMMC2_IRQHandler
+	.thumb_set SDMMC2_IRQHandler,Default_Handler
+
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+
+	.weak	ICACHE_IRQHandler
+	.thumb_set ICACHE_IRQHandler,Default_Handler
+
+	.weak	DCACHE1_IRQHandler
+	.thumb_set DCACHE1_IRQHandler,Default_Handler
+
+	.weak	ETH_IRQHandler
+	.thumb_set ETH_IRQHandler,Default_Handler
+
+	.weak	ETH_WKUP_IRQHandler
+	.thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+	.weak	DCMI_PSSI_IRQHandler
+	.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+	.weak	FDCAN2_IT0_IRQHandler
+	.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN2_IT1_IRQHandler
+	.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+	.weak	CORDIC_IRQHandler
+	.thumb_set CORDIC_IRQHandler,Default_Handler
+
+	.weak	FMAC_IRQHandler
+	.thumb_set FMAC_IRQHandler,Default_Handler
+
+	.weak	DTS_IRQHandler
+	.thumb_set DTS_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	HASH_IRQHandler
+	.thumb_set HASH_IRQHandler,Default_Handler
+
+	.weak	CEC_IRQHandler
+	.thumb_set CEC_IRQHandler,Default_Handler
+
+	.weak	TIM12_IRQHandler
+	.thumb_set TIM12_IRQHandler,Default_Handler
+
+	.weak	TIM13_IRQHandler
+	.thumb_set TIM13_IRQHandler,Default_Handler
+
+	.weak	TIM14_IRQHandler
+	.thumb_set TIM14_IRQHandler,Default_Handler
+
+	.weak	I3C1_EV_IRQHandler
+	.thumb_set I3C1_EV_IRQHandler,Default_Handler
+
+	.weak	I3C1_ER_IRQHandler
+	.thumb_set I3C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C4_EV_IRQHandler
+	.thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+	.weak	I2C4_ER_IRQHandler
+	.thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+	.weak	LPTIM3_IRQHandler
+	.thumb_set LPTIM3_IRQHandler,Default_Handler
+
+	.weak	LPTIM4_IRQHandler
+	.thumb_set LPTIM4_IRQHandler,Default_Handler
+
+	.weak	LPTIM5_IRQHandler
+	.thumb_set LPTIM5_IRQHandler,Default_Handler
+
+	.weak	LPTIM6_IRQHandler
+	.thumb_set LPTIM6_IRQHandler,Default_Handler

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h573xx.s

@@ -0,0 +1,713 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h573xx.s
+  * @author    MCD Application Team
+  * @brief     STM32H573xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M33 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m33
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+  * @brief  This is the code that gets called when the processor first
+  *          starts execution following a reset event. Only the absolutely
+  *          necessary set is performed, after which the application
+  *          supplied main() routine is called.
+  * @param  None
+  * @retval : None
+  */
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+
+LoopForever:
+    b LoopForever
+
+  .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32H573xx vector table.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	SecureFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_AVD_IRQHandler
+	.word	RTC_IRQHandler
+	.word	RTC_S_IRQHandler
+	.word	TAMP_IRQHandler
+	.word	RAMCFG_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	FLASH_S_IRQHandler
+	.word	GTZC_IRQHandler
+	.word	RCC_IRQHandler
+	.word	RCC_S_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	EXTI5_IRQHandler
+	.word	EXTI6_IRQHandler
+	.word	EXTI7_IRQHandler
+	.word	EXTI8_IRQHandler
+	.word	EXTI9_IRQHandler
+	.word	EXTI10_IRQHandler
+	.word	EXTI11_IRQHandler
+	.word	EXTI12_IRQHandler
+	.word	EXTI13_IRQHandler
+	.word	EXTI14_IRQHandler
+	.word	EXTI15_IRQHandler
+	.word	GPDMA1_Channel0_IRQHandler
+	.word	GPDMA1_Channel1_IRQHandler
+	.word	GPDMA1_Channel2_IRQHandler
+	.word	GPDMA1_Channel3_IRQHandler
+	.word	GPDMA1_Channel4_IRQHandler
+	.word	GPDMA1_Channel5_IRQHandler
+	.word	GPDMA1_Channel6_IRQHandler
+	.word	GPDMA1_Channel7_IRQHandler
+	.word	IWDG_IRQHandler
+	.word	SAES_IRQHandler
+	.word	ADC1_IRQHandler
+	.word	DAC1_IRQHandler
+	.word	FDCAN1_IT0_IRQHandler
+	.word	FDCAN1_IT1_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	TIM5_IRQHandler
+	.word	TIM6_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	ADC2_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	TIM15_IRQHandler
+	.word	TIM16_IRQHandler
+	.word	TIM17_IRQHandler
+	.word	USB_DRD_FS_IRQHandler
+	.word	CRS_IRQHandler
+	.word	UCPD1_IRQHandler
+	.word	FMC_IRQHandler
+	.word	OCTOSPI1_IRQHandler
+	.word	SDMMC1_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SPI4_IRQHandler
+	.word	SPI5_IRQHandler
+	.word	SPI6_IRQHandler
+	.word	USART6_IRQHandler
+	.word	USART10_IRQHandler
+	.word	USART11_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	SAI2_IRQHandler
+	.word	GPDMA2_Channel0_IRQHandler
+	.word	GPDMA2_Channel1_IRQHandler
+	.word	GPDMA2_Channel2_IRQHandler
+	.word	GPDMA2_Channel3_IRQHandler
+	.word	GPDMA2_Channel4_IRQHandler
+	.word	GPDMA2_Channel5_IRQHandler
+	.word	GPDMA2_Channel6_IRQHandler
+	.word	GPDMA2_Channel7_IRQHandler
+	.word	UART7_IRQHandler
+	.word	UART8_IRQHandler
+	.word	UART9_IRQHandler
+	.word	UART12_IRQHandler
+	.word	SDMMC2_IRQHandler
+	.word	FPU_IRQHandler
+	.word	ICACHE_IRQHandler
+	.word	DCACHE1_IRQHandler
+	.word	ETH_IRQHandler
+	.word	ETH_WKUP_IRQHandler
+	.word	DCMI_PSSI_IRQHandler
+	.word	FDCAN2_IT0_IRQHandler
+	.word	FDCAN2_IT1_IRQHandler
+	.word	CORDIC_IRQHandler
+ 	.word   FMAC_IRQHandler
+	.word	DTS_IRQHandler
+	.word	RNG_IRQHandler
+	.word	OTFDEC1_IRQHandler
+	.word	AES_IRQHandler
+	.word	HASH_IRQHandler
+	.word	PKA_IRQHandler
+	.word	CEC_IRQHandler
+	.word	TIM12_IRQHandler
+	.word	TIM13_IRQHandler
+	.word	TIM14_IRQHandler
+	.word	I3C1_EV_IRQHandler
+	.word	I3C1_ER_IRQHandler
+	.word	I2C4_EV_IRQHandler
+	.word	I2C4_ER_IRQHandler
+	.word	LPTIM3_IRQHandler
+	.word	LPTIM4_IRQHandler
+	.word	LPTIM5_IRQHandler
+	.word	LPTIM6_IRQHandler
+
+	.size	g_pfnVectors, .-g_pfnVectors
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+	.weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+	.weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+	.weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+	.weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SecureFault_Handler
+	.thumb_set SecureFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_AVD_IRQHandler
+	.thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	RTC_S_IRQHandler
+	.thumb_set RTC_S_IRQHandler,Default_Handler
+
+	.weak	TAMP_IRQHandler
+	.thumb_set TAMP_IRQHandler,Default_Handler
+
+	.weak	RAMCFG_IRQHandler
+	.thumb_set RAMCFG_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	FLASH_S_IRQHandler
+	.thumb_set FLASH_S_IRQHandler,Default_Handler
+
+	.weak	GTZC_IRQHandler
+	.thumb_set GTZC_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	RCC_S_IRQHandler
+	.thumb_set RCC_S_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	EXTI5_IRQHandler
+	.thumb_set EXTI5_IRQHandler,Default_Handler
+
+	.weak	EXTI6_IRQHandler
+	.thumb_set EXTI6_IRQHandler,Default_Handler
+
+	.weak	EXTI7_IRQHandler
+	.thumb_set EXTI7_IRQHandler,Default_Handler
+
+	.weak	EXTI8_IRQHandler
+	.thumb_set EXTI8_IRQHandler,Default_Handler
+
+	.weak	EXTI9_IRQHandler
+	.thumb_set EXTI9_IRQHandler,Default_Handler
+
+	.weak	EXTI10_IRQHandler
+	.thumb_set EXTI10_IRQHandler,Default_Handler
+
+	.weak	EXTI11_IRQHandler
+	.thumb_set EXTI11_IRQHandler,Default_Handler
+
+	.weak	EXTI12_IRQHandler
+	.thumb_set EXTI12_IRQHandler,Default_Handler
+
+	.weak	EXTI13_IRQHandler
+	.thumb_set EXTI13_IRQHandler,Default_Handler
+
+	.weak	EXTI14_IRQHandler
+	.thumb_set EXTI14_IRQHandler,Default_Handler
+
+	.weak	EXTI15_IRQHandler
+	.thumb_set EXTI15_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel0_IRQHandler
+	.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel1_IRQHandler
+	.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel2_IRQHandler
+	.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel3_IRQHandler
+	.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel4_IRQHandler
+	.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel5_IRQHandler
+	.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel6_IRQHandler
+	.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA1_Channel7_IRQHandler
+	.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	IWDG_IRQHandler
+	.thumb_set IWDG_IRQHandler,Default_Handler
+
+	.weak	SAES_IRQHandler
+	.thumb_set SAES_IRQHandler,Default_Handler
+
+	.weak	ADC1_IRQHandler
+	.thumb_set ADC1_IRQHandler,Default_Handler
+
+	.weak	DAC1_IRQHandler
+	.thumb_set DAC1_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT0_IRQHandler
+	.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT1_IRQHandler
+	.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	TIM6_IRQHandler
+	.thumb_set TIM6_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC2_IRQHandler
+	.thumb_set ADC2_IRQHandler,Default_Handler
+
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler
+
+	.weak	TIM15_IRQHandler
+	.thumb_set TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM16_IRQHandler
+	.thumb_set TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM17_IRQHandler
+	.thumb_set TIM17_IRQHandler,Default_Handler
+
+	.weak	USB_DRD_FS_IRQHandler
+	.thumb_set USB_DRD_FS_IRQHandler,Default_Handler
+
+	.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+
+	.weak	UCPD1_IRQHandler
+	.thumb_set UCPD1_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	OCTOSPI1_IRQHandler
+	.thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+	.weak	SPI4_IRQHandler
+	.thumb_set SPI4_IRQHandler,Default_Handler
+
+	.weak	SPI5_IRQHandler
+	.thumb_set SPI5_IRQHandler,Default_Handler
+
+	.weak	SPI6_IRQHandler
+	.thumb_set SPI6_IRQHandler,Default_Handler
+
+	.weak	USART6_IRQHandler
+	.thumb_set USART6_IRQHandler,Default_Handler
+
+	.weak	USART10_IRQHandler
+	.thumb_set USART10_IRQHandler,Default_Handler
+
+	.weak	USART11_IRQHandler
+	.thumb_set USART11_IRQHandler,Default_Handler
+
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+
+	.weak	SAI2_IRQHandler
+	.thumb_set SAI2_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel0_IRQHandler
+	.thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel1_IRQHandler
+	.thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel2_IRQHandler
+	.thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel3_IRQHandler
+	.thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel4_IRQHandler
+	.thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel5_IRQHandler
+	.thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel6_IRQHandler
+	.thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler
+
+	.weak	GPDMA2_Channel7_IRQHandler
+	.thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler
+
+	.weak	UART7_IRQHandler
+	.thumb_set UART7_IRQHandler,Default_Handler
+
+	.weak	UART8_IRQHandler
+	.thumb_set UART8_IRQHandler,Default_Handler
+
+	.weak	UART9_IRQHandler
+	.thumb_set UART9_IRQHandler,Default_Handler
+
+	.weak	UART12_IRQHandler
+	.thumb_set UART12_IRQHandler,Default_Handler
+
+	.weak	SDMMC2_IRQHandler
+	.thumb_set SDMMC2_IRQHandler,Default_Handler
+
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+
+	.weak	ICACHE_IRQHandler
+	.thumb_set ICACHE_IRQHandler,Default_Handler
+
+	.weak	DCACHE1_IRQHandler
+	.thumb_set DCACHE1_IRQHandler,Default_Handler
+
+	.weak	ETH_IRQHandler
+	.thumb_set ETH_IRQHandler,Default_Handler
+
+	.weak	ETH_WKUP_IRQHandler
+	.thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+	.weak	DCMI_PSSI_IRQHandler
+	.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+	.weak	FDCAN2_IT0_IRQHandler
+	.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN2_IT1_IRQHandler
+	.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+	.weak	CORDIC_IRQHandler
+	.thumb_set CORDIC_IRQHandler,Default_Handler
+
+	.weak	FMAC_IRQHandler
+	.thumb_set FMAC_IRQHandler,Default_Handler
+
+	.weak	DTS_IRQHandler
+	.thumb_set DTS_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	OTFDEC1_IRQHandler
+	.thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+	.weak	AES_IRQHandler
+	.thumb_set AES_IRQHandler,Default_Handler
+
+	.weak	HASH_IRQHandler
+	.thumb_set HASH_IRQHandler,Default_Handler
+
+	.weak	PKA_IRQHandler
+	.thumb_set PKA_IRQHandler,Default_Handler
+
+	.weak	CEC_IRQHandler
+	.thumb_set CEC_IRQHandler,Default_Handler
+
+	.weak	TIM12_IRQHandler
+	.thumb_set TIM12_IRQHandler,Default_Handler
+
+	.weak	TIM13_IRQHandler
+	.thumb_set TIM13_IRQHandler,Default_Handler
+
+	.weak	TIM14_IRQHandler
+	.thumb_set TIM14_IRQHandler,Default_Handler
+
+	.weak	I3C1_EV_IRQHandler
+	.thumb_set I3C1_EV_IRQHandler,Default_Handler
+
+	.weak	I3C1_ER_IRQHandler
+	.thumb_set I3C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C4_EV_IRQHandler
+	.thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+	.weak	I2C4_ER_IRQHandler
+	.thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+	.weak	LPTIM3_IRQHandler
+	.thumb_set LPTIM3_IRQHandler,Default_Handler
+
+	.weak	LPTIM4_IRQHandler
+	.thumb_set LPTIM4_IRQHandler,Default_Handler
+
+	.weak	LPTIM5_IRQHandler
+	.thumb_set LPTIM5_IRQHandler,Default_Handler
+
+	.weak	LPTIM6_IRQHandler
+	.thumb_set LPTIM6_IRQHandler,Default_Handler

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h503xx_flash.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h503xx_sram.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x20003FFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20004000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x20007FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h523xx_flash.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x20043FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h523xx_flash_ns.icf

@@ -0,0 +1,32 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08040000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08040000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20034000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20043FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h523xx_flash_s.icf

@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x0C000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x0C03DFFF;
+define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x0C03E000;
+define symbol __ICFEDIT_region_ROM_NSC_end__   = 0x0C03FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x30033FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ROM_NS_start__    = 0x08040000;
+define symbol __region_ROM_NS_end__      = 0x0807FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__     to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__     to __ICFEDIT_region_RAM_end__];
+
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_ROM_NS_start__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in ROM_NSC_region { section Veneer$$CMSE };
+place in RAM_region     { readwrite,
+                          block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h523xx_sram.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x2002FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20030000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x20043FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h533xx_flash.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x20043FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h533xx_flash_ns.icf

@@ -0,0 +1,32 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08040000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08040000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20034000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20043FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h533xx_flash_s.icf

@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x0C000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x0C03DFFF;
+define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x0C03E000;
+define symbol __ICFEDIT_region_ROM_NSC_end__   = 0x0C03FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x30033FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ROM_NS_start__    = 0x08040000;
+define symbol __region_ROM_NS_end__      = 0x0807FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__     to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__     to __ICFEDIT_region_RAM_end__];
+
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_ROM_NS_start__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in ROM_NSC_region { section Veneer$$CMSE };
+place in RAM_region     { readwrite,
+                          block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h533xx_sram.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x2002FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20030000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x20043FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h562xx_flash.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h562xx_flash_ns.icf

@@ -0,0 +1,32 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20050000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h562xx_flash_s.icf

@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x0C000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x0C0FDFFF;
+define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x0C0FE000;
+define symbol __ICFEDIT_region_ROM_NSC_end__   = 0x0C0FFFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x3004FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ROM_NS_start__    = 0x08100000;
+define symbol __region_ROM_NS_end__      = 0x081FFFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__     to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__     to __ICFEDIT_region_RAM_end__];
+
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_ROM_NS_start__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in ROM_NSC_region { section Veneer$$CMSE };
+place in RAM_region     { readwrite,
+                          block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h562xx_sram.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x2004FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20050000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h562xx_sram_ns.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20060000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x20050000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x2007FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20080000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h562xx_sram_s.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x30000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x30000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x30037FFF;
+define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x30038000;
+define symbol __ICFEDIT_region_ROM_NSC_end__   = 0x3003FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x30040000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x3004FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM_NS_start__    = 0x20050000;
+define symbol __region_RAM_NS_end__      = 0x2009FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__     to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__     to __ICFEDIT_region_RAM_end__];
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_RAM_NS_start__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in ROM_NSC_region { section Veneer$$CMSE };
+place in RAM_region     { readwrite,
+                          block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h563xx_flash.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h563xx_flash_ns.icf

@@ -0,0 +1,32 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20050000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h563xx_flash_s.icf

@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x0C000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x0C0FDFFF;
+define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x0C0FE000;
+define symbol __ICFEDIT_region_ROM_NSC_end__   = 0x0C0FFFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x3004FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ROM_NS_start__    = 0x08100000;
+define symbol __region_ROM_NS_end__      = 0x081FFFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__     to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__     to __ICFEDIT_region_RAM_end__];
+
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_ROM_NS_start__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in ROM_NSC_region { section Veneer$$CMSE };
+place in RAM_region     { readwrite,
+                          block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h563xx_sram.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x2004FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20050000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h563xx_sram_ns.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20060000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x20050000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x2007FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20080000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h563xx_sram_s.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x30000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x30000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x30037FFF;
+define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x30038000;
+define symbol __ICFEDIT_region_ROM_NSC_end__   = 0x3003FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x30040000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x3004FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM_NS_start__    = 0x20050000;
+define symbol __region_RAM_NS_end__      = 0x2009FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__     to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__     to __ICFEDIT_region_RAM_end__];
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_RAM_NS_start__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in ROM_NSC_region { section Veneer$$CMSE };
+place in RAM_region     { readwrite,
+                          block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h573xx_flash.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h573xx_flash_ns.icf

@@ -0,0 +1,32 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20050000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h573xx_flash_s.icf

@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x0C000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x0C0FDFFF;
+define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x0C0FE000;
+define symbol __ICFEDIT_region_ROM_NSC_end__   = 0x0C0FFFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x3004FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ROM_NS_start__    = 0x08100000;
+define symbol __region_ROM_NS_end__      = 0x081FFFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__     to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__     to __ICFEDIT_region_RAM_end__];
+
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_ROM_NS_start__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in ROM_NSC_region { section Veneer$$CMSE };
+place in RAM_region     { readwrite,
+                          block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h573xx_sram.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x2004FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20050000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h573xx_sram_ns.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20060000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x20050000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x2007FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20080000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2009FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+                        

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/linker/stm32h573xx_sram_s.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x30000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x30000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x30037FFF;
+define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x30038000;
+define symbol __ICFEDIT_region_ROM_NSC_end__   = 0x3003FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x30040000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x3004FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM_NS_start__    = 0x20050000;
+define symbol __region_RAM_NS_end__      = 0x2009FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__     to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__     to __ICFEDIT_region_RAM_end__];
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_RAM_NS_start__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in ROM_NSC_region { section Veneer$$CMSE };
+place in RAM_region     { readwrite,
+                          block CSTACK, block HEAP };

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/startup_stm32h503xx.s

@@ -0,0 +1,670 @@
+;********************************************************************************
+;* File Name          : startup_stm32h503xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H503xx Non Crypto Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                    ; Reset Handler
+
+        DCD     NMI_Handler                      ; NMI Handler
+        DCD     HardFault_Handler                ; Hard Fault Handler
+        DCD     MemManage_Handler                ; MPU Fault Handler
+        DCD     BusFault_Handler                 ; Bus Fault Handler
+        DCD     UsageFault_Handler               ; Usage Fault Handler
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     SVC_Handler                      ; SVCall Handler
+        DCD     DebugMon_Handler                 ; Debug Monitor Handler
+        DCD     0                                ; Reserved
+        DCD     PendSV_Handler                   ; PendSV Handler
+        DCD     SysTick_Handler                  ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                  ; Window WatchDog
+        DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+        DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+        DCD     0                                ; Reserved
+        DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+        DCD     RAMCFG_IRQHandler                ; RAMCFG global
+        DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+        DCD     0                                ; Reserved
+        DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+        DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+        DCD     0                                ; Reserved
+        DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+        DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+        DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+        DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+        DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+        DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+        DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+        DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+        DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+        DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+        DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+        DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+        DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+        DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+        DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+        DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+        DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+        DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+        DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+        DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+        DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+        DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+        DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+        DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+        DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+        DCD     0                                ; Reserved
+        DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+        DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+        DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+        DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+        DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+        DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+        DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+        DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+        DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+        DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+        DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+        DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+        DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+        DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+        DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+        DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+        DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+        DCD     USART1_IRQHandler                ; USART1 global interrupt
+        DCD     USART2_IRQHandler                ; USART2 global interrupt
+        DCD     USART3_IRQHandler                ; USART3 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+        DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+        DCD     CRS_IRQHandler                   ; CRS global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+        DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+        DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+        DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+        DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+        DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+        DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+        DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     FPU_IRQHandler                   ; FPU global interrupt
+        DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     DTS_IRQHandler                   ; DTS global interrupt
+        DCD     RNG_IRQHandler                   ; RNG global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     HASH_IRQHandler                  ; HASH global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+        DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     I3C2_EV_IRQHandler               ; I3C2 Event interrupt
+        DCD     I3C2_ER_IRQHandler               ; I3C2 Error interrupt
+        DCD     COMP1_IRQHandler                 ; COMP1 global interrupt
+
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SecureFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SecureFault_Handler
+        B SecureFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_AVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+        B PVD_AVD_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK TAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_IRQHandler
+        B TAMP_IRQHandler
+
+        PUBWEAK RAMCFG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RAMCFG_IRQHandler
+        B RAMCFG_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK GTZC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GTZC_IRQHandler
+        B GTZC_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK EXTI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_IRQHandler
+        B EXTI5_IRQHandler
+
+        PUBWEAK EXTI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI6_IRQHandler
+        B EXTI6_IRQHandler
+
+        PUBWEAK EXTI7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI7_IRQHandler
+        B EXTI7_IRQHandler
+
+        PUBWEAK EXTI8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI8_IRQHandler
+        B EXTI8_IRQHandler
+
+        PUBWEAK EXTI9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_IRQHandler
+        B EXTI9_IRQHandler
+
+        PUBWEAK EXTI10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_IRQHandler
+        B EXTI10_IRQHandler
+
+        PUBWEAK EXTI11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI11_IRQHandler
+        B EXTI11_IRQHandler
+
+        PUBWEAK EXTI12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI12_IRQHandler
+        B EXTI12_IRQHandler
+
+        PUBWEAK EXTI13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI13_IRQHandler
+        B EXTI13_IRQHandler
+
+        PUBWEAK EXTI14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI14_IRQHandler
+        B EXTI14_IRQHandler
+
+        PUBWEAK EXTI15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_IRQHandler
+        B EXTI15_IRQHandler
+
+        PUBWEAK GPDMA1_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel0_IRQHandler
+        B GPDMA1_Channel0_IRQHandler
+
+        PUBWEAK GPDMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel1_IRQHandler
+        B GPDMA1_Channel1_IRQHandler
+
+        PUBWEAK GPDMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel2_IRQHandler
+        B GPDMA1_Channel2_IRQHandler
+
+        PUBWEAK GPDMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel3_IRQHandler
+        B GPDMA1_Channel3_IRQHandler
+
+        PUBWEAK GPDMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel4_IRQHandler
+        B GPDMA1_Channel4_IRQHandler
+
+        PUBWEAK GPDMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel5_IRQHandler
+        B GPDMA1_Channel5_IRQHandler
+
+        PUBWEAK GPDMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel6_IRQHandler
+        B GPDMA1_Channel6_IRQHandler
+
+        PUBWEAK GPDMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel7_IRQHandler
+        B GPDMA1_Channel7_IRQHandler
+
+        PUBWEAK IWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IWDG_IRQHandler
+        B IWDG_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK DAC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC1_IRQHandler
+        B DAC1_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK USB_DRD_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_DRD_FS_IRQHandler
+        B USB_DRD_FS_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK GPDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel0_IRQHandler
+        B GPDMA2_Channel0_IRQHandler
+
+        PUBWEAK GPDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel1_IRQHandler
+        B GPDMA2_Channel1_IRQHandler
+
+        PUBWEAK GPDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel2_IRQHandler
+        B GPDMA2_Channel2_IRQHandler
+
+        PUBWEAK GPDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel3_IRQHandler
+        B GPDMA2_Channel3_IRQHandler
+
+        PUBWEAK GPDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel4_IRQHandler
+        B GPDMA2_Channel4_IRQHandler
+
+        PUBWEAK GPDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel5_IRQHandler
+        B GPDMA2_Channel5_IRQHandler
+
+        PUBWEAK GPDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel6_IRQHandler
+        B GPDMA2_Channel6_IRQHandler
+
+        PUBWEAK GPDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel7_IRQHandler
+        B GPDMA2_Channel7_IRQHandler
+
+        PUBWEAK COMP1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+        B COMP1_IRQHandler
+
+        PUBWEAK I3C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C2_EV_IRQHandler
+        B I3C2_EV_IRQHandler
+
+        PUBWEAK I3C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C2_ER_IRQHandler
+        B I3C2_ER_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK ICACHE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ICACHE_IRQHandler
+        B ICACHE_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK HASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_IRQHandler
+        B HASH_IRQHandler
+
+        PUBWEAK I3C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_EV_IRQHandler
+        B I3C1_EV_IRQHandler
+
+        PUBWEAK I3C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_ER_IRQHandler
+        B I3C1_ER_IRQHandler
+
+        END

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/startup_stm32h523xx.s

@@ -0,0 +1,799 @@
+;********************************************************************************
+;* File Name          : startup_stm32h523xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H523xx Non Crypto Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                    ; Reset Handler
+
+        DCD     NMI_Handler                      ; NMI Handler
+        DCD     HardFault_Handler                ; Hard Fault Handler
+        DCD     MemManage_Handler                ; MPU Fault Handler
+        DCD     BusFault_Handler                 ; Bus Fault Handler
+        DCD     UsageFault_Handler               ; Usage Fault Handler
+        DCD     SecureFault_Handler              ; Secure Fault Handler
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     SVC_Handler                      ; SVCall Handler
+        DCD     DebugMon_Handler                 ; Debug Monitor Handler
+        DCD     0                                ; Reserved
+        DCD     PendSV_Handler                   ; PendSV Handler
+        DCD     SysTick_Handler                  ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                  ; Window WatchDog
+        DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+        DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+        DCD     RTC_S_IRQHandler                 ; RTC secure interrupt
+        DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+        DCD     RAMCFG_IRQHandler                ; RAMCFG global
+        DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+        DCD     FLASH_S_IRQHandler               ; FLASH secure global interrupt
+        DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+        DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+        DCD     RCC_S_IRQHandler                 ; RCC secure global interrupt
+        DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+        DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+        DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+        DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+        DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+        DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+        DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+        DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+        DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+        DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+        DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+        DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+        DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+        DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+        DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+        DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+        DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+        DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+        DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+        DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+        DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+        DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+        DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+        DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+        DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+        DCD     0                                ; Reserved
+        DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+        DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+        DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+        DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+        DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+        DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+        DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+        DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+        DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+        DCD     TIM4_IRQHandler                  ; TIM4 global interrupt
+        DCD     TIM5_IRQHandler                  ; TIM5 global interrupt
+        DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+        DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+        DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+        DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+        DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+        DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+        DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+        DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+        DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+        DCD     USART1_IRQHandler                ; USART1 global interrupt
+        DCD     USART2_IRQHandler                ; USART2 global interrupt
+        DCD     USART3_IRQHandler                ; USART3 global interrupt
+        DCD     UART4_IRQHandler                 ; UART4 global interrupt
+        DCD     UART5_IRQHandler                 ; UART5 global interrupt
+        DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+        DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+        DCD     TIM8_BRK_IRQHandler              ; TIM8 Break interrupt
+        DCD     TIM8_UP_IRQHandler               ; TIM8 Update interrupt
+        DCD     TIM8_TRG_COM_IRQHandler          ; TIM8 Trigger and Commutation interrupt
+        DCD     TIM8_CC_IRQHandler               ; TIM8 Capture Compare interrupt
+        DCD     ADC2_IRQHandler                  ; ADC2 global interrupt
+        DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+        DCD     TIM15_IRQHandler                 ; TIM15 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+        DCD     CRS_IRQHandler                   ; CRS global interrupt
+        DCD     UCPD1_IRQHandler                 ; UCPD1 global interrupt
+        DCD     FMC_IRQHandler                   ; FMC global interrupt
+        DCD     OCTOSPI1_IRQHandler              ; OctoSPI1 global interrupt
+        DCD     SDMMC1_IRQHandler                ; SDMMC1 global interrupt
+        DCD     I2C3_EV_IRQHandler               ; I2C2 Event interrupt
+        DCD     I2C3_ER_IRQHandler               ; I2C2 Error interrupt
+        DCD     SPI4_IRQHandler                  ; SPI4 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     USART6_IRQHandler                ; USART6 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+        DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+        DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+        DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+        DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+        DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+        DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+        DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     FPU_IRQHandler                   ; FPU global interrupt
+        DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+        DCD     DCACHE1_IRQHandler               ; DCACHE1 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     DCMI_PSSI_IRQHandler             ; DCMI PSSI global interrupt
+        DCD     FDCAN2_IT0_IRQHandler            ; FDCAN2 interrupt 0
+        DCD     FDCAN2_IT1_IRQHandler            ; FDCAN2 interrupt 1
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     DTS_IRQHandler                   ; DTS global interrupt
+        DCD     RNG_IRQHandler                   ; RNG global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     HASH_IRQHandler                  ; HASH global interrupt
+        DCD     0                                ; Reserved
+        DCD     CEC_IRQHandler                   ; CEC global interrupt
+        DCD     TIM12_IRQHandler                 ; TIM12 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+        DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     I3C2_EV_IRQHandler               ; I3C2 Event interrupt
+        DCD     I3C2_ER_IRQHandler               ; I3C2 Error interrupt
+
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SecureFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SecureFault_Handler
+        B SecureFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_AVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+        B PVD_AVD_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK RTC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_S_IRQHandler
+        B RTC_S_IRQHandler
+
+        PUBWEAK TAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_IRQHandler
+        B TAMP_IRQHandler
+
+        PUBWEAK RAMCFG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RAMCFG_IRQHandler
+        B RAMCFG_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK FLASH_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_S_IRQHandler
+        B FLASH_S_IRQHandler
+
+        PUBWEAK GTZC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GTZC_IRQHandler
+        B GTZC_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK RCC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_S_IRQHandler
+        B RCC_S_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK EXTI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_IRQHandler
+        B EXTI5_IRQHandler
+
+        PUBWEAK EXTI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI6_IRQHandler
+        B EXTI6_IRQHandler
+
+        PUBWEAK EXTI7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI7_IRQHandler
+        B EXTI7_IRQHandler
+
+        PUBWEAK EXTI8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI8_IRQHandler
+        B EXTI8_IRQHandler
+
+        PUBWEAK EXTI9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_IRQHandler
+        B EXTI9_IRQHandler
+
+        PUBWEAK EXTI10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_IRQHandler
+        B EXTI10_IRQHandler
+
+        PUBWEAK EXTI11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI11_IRQHandler
+        B EXTI11_IRQHandler
+
+        PUBWEAK EXTI12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI12_IRQHandler
+        B EXTI12_IRQHandler
+
+        PUBWEAK EXTI13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI13_IRQHandler
+        B EXTI13_IRQHandler
+
+        PUBWEAK EXTI14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI14_IRQHandler
+        B EXTI14_IRQHandler
+
+        PUBWEAK EXTI15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_IRQHandler
+        B EXTI15_IRQHandler
+
+        PUBWEAK GPDMA1_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel0_IRQHandler
+        B GPDMA1_Channel0_IRQHandler
+
+        PUBWEAK GPDMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel1_IRQHandler
+        B GPDMA1_Channel1_IRQHandler
+
+        PUBWEAK GPDMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel2_IRQHandler
+        B GPDMA1_Channel2_IRQHandler
+
+        PUBWEAK GPDMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel3_IRQHandler
+        B GPDMA1_Channel3_IRQHandler
+
+        PUBWEAK GPDMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel4_IRQHandler
+        B GPDMA1_Channel4_IRQHandler
+
+        PUBWEAK GPDMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel5_IRQHandler
+        B GPDMA1_Channel5_IRQHandler
+
+        PUBWEAK GPDMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel6_IRQHandler
+        B GPDMA1_Channel6_IRQHandler
+
+        PUBWEAK GPDMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel7_IRQHandler
+        B GPDMA1_Channel7_IRQHandler
+
+        PUBWEAK IWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IWDG_IRQHandler
+        B IWDG_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK DAC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC1_IRQHandler
+        B DAC1_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC2_IRQHandler
+        B ADC2_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK USB_DRD_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_DRD_FS_IRQHandler
+        B USB_DRD_FS_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK UCPD1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UCPD1_IRQHandler
+        B UCPD1_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+        B USART6_IRQHandler
+
+        PUBWEAK GPDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel0_IRQHandler
+        B GPDMA2_Channel0_IRQHandler
+
+        PUBWEAK GPDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel1_IRQHandler
+        B GPDMA2_Channel1_IRQHandler
+
+        PUBWEAK GPDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel2_IRQHandler
+        B GPDMA2_Channel2_IRQHandler
+
+        PUBWEAK GPDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel3_IRQHandler
+        B GPDMA2_Channel3_IRQHandler
+
+        PUBWEAK GPDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel4_IRQHandler
+        B GPDMA2_Channel4_IRQHandler
+
+        PUBWEAK GPDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel5_IRQHandler
+        B GPDMA2_Channel5_IRQHandler
+
+        PUBWEAK GPDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel6_IRQHandler
+        B GPDMA2_Channel6_IRQHandler
+
+        PUBWEAK GPDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel7_IRQHandler
+        B GPDMA2_Channel7_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK ICACHE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ICACHE_IRQHandler
+        B ICACHE_IRQHandler
+
+        PUBWEAK DCACHE1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCACHE1_IRQHandler
+        B DCACHE1_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK HASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_IRQHandler
+        B HASH_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM12_IRQHandler
+        B TIM12_IRQHandler
+
+        PUBWEAK I3C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_EV_IRQHandler
+        B I3C1_EV_IRQHandler
+
+        PUBWEAK I3C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_ER_IRQHandler
+        B I3C1_ER_IRQHandler
+
+        PUBWEAK I3C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C2_EV_IRQHandler
+        B I3C2_EV_IRQHandler
+
+        PUBWEAK I3C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C2_ER_IRQHandler
+        B I3C2_ER_IRQHandler
+
+        END

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/startup_stm32h533xx.s

@@ -0,0 +1,819 @@
+;********************************************************************************
+;* File Name          : startup_stm32h533xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H533xx Crypto Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                    ; Reset Handler
+
+        DCD     NMI_Handler                      ; NMI Handler
+        DCD     HardFault_Handler                ; Hard Fault Handler
+        DCD     MemManage_Handler                ; MPU Fault Handler
+        DCD     BusFault_Handler                 ; Bus Fault Handler
+        DCD     UsageFault_Handler               ; Usage Fault Handler
+        DCD     SecureFault_Handler              ; Secure Fault Handler
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     SVC_Handler                      ; SVCall Handler
+        DCD     DebugMon_Handler                 ; Debug Monitor Handler
+        DCD     0                                ; Reserved
+        DCD     PendSV_Handler                   ; PendSV Handler
+        DCD     SysTick_Handler                  ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                  ; Window WatchDog
+        DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+        DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+        DCD     RTC_S_IRQHandler                 ; RTC secure interrupt
+        DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+        DCD     RAMCFG_IRQHandler                ; RAMCFG global
+        DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+        DCD     FLASH_S_IRQHandler               ; FLASH secure global interrupt
+        DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+        DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+        DCD     RCC_S_IRQHandler                 ; RCC secure global interrupt
+        DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+        DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+        DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+        DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+        DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+        DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+        DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+        DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+        DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+        DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+        DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+        DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+        DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+        DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+        DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+        DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+        DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+        DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+        DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+        DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+        DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+        DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+        DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+        DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+        DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+        DCD     SAES_IRQHandler                  ; SAES global interrupt
+        DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+        DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+        DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+        DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+        DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+        DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+        DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+        DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+        DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+        DCD     TIM4_IRQHandler                  ; TIM4 global interrupt
+        DCD     TIM5_IRQHandler                  ; TIM5 global interrupt
+        DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+        DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+        DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+        DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+        DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+        DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+        DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+        DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+        DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+        DCD     USART1_IRQHandler                ; USART1 global interrupt
+        DCD     USART2_IRQHandler                ; USART2 global interrupt
+        DCD     USART3_IRQHandler                ; USART3 global interrupt
+        DCD     UART4_IRQHandler                 ; UART4 global interrupt
+        DCD     UART5_IRQHandler                 ; UART5 global interrupt
+        DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+        DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+        DCD     TIM8_BRK_IRQHandler              ; TIM8 Break interrupt
+        DCD     TIM8_UP_IRQHandler               ; TIM8 Update interrupt
+        DCD     TIM8_TRG_COM_IRQHandler          ; TIM8 Trigger and Commutation interrupt
+        DCD     TIM8_CC_IRQHandler               ; TIM8 Capture Compare interrupt
+        DCD     ADC2_IRQHandler                  ; ADC2 global interrupt
+        DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+        DCD     TIM15_IRQHandler                 ; TIM15 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+        DCD     CRS_IRQHandler                   ; CRS global interrupt
+        DCD     UCPD1_IRQHandler                 ; UCPD1 global interrupt
+        DCD     FMC_IRQHandler                   ; FMC global interrupt
+        DCD     OCTOSPI1_IRQHandler              ; OctoSPI1 global interrupt
+        DCD     SDMMC1_IRQHandler                ; SDMMC1 global interrupt
+        DCD     I2C3_EV_IRQHandler               ; I2C2 Event interrupt
+        DCD     I2C3_ER_IRQHandler               ; I2C2 Error interrupt
+        DCD     SPI4_IRQHandler                  ; SPI4 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     USART6_IRQHandler                ; USART6 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+        DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+        DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+        DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+        DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+        DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+        DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+        DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     FPU_IRQHandler                   ; FPU global interrupt
+        DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+        DCD     DCACHE1_IRQHandler               ; DCACHE1 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     DCMI_PSSI_IRQHandler             ; DCMI PSSI global interrupt
+        DCD     FDCAN2_IT0_IRQHandler            ; FDCAN2 interrupt 0
+        DCD     FDCAN2_IT1_IRQHandler            ; FDCAN2 interrupt 1
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     DTS_IRQHandler                   ; DTS global interrupt
+        DCD     RNG_IRQHandler                   ; RNG global interrupt
+        DCD     OTFDEC1_IRQHandler               ; OTFDEC1 global interrupt
+        DCD     AES_IRQHandler                   ; AES global interrupt
+        DCD     HASH_IRQHandler                  ; HASH global interrupt
+        DCD     PKA_IRQHandler                   ; PKA global interrupt
+        DCD     CEC_IRQHandler                   ; CEC global interrupt
+        DCD     TIM12_IRQHandler                 ; TIM12 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+        DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     I3C2_EV_IRQHandler               ; I3C2 Event interrupt
+        DCD     I3C2_ER_IRQHandler               ; I3C2 Error interrupt
+
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SecureFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SecureFault_Handler
+        B SecureFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_AVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+        B PVD_AVD_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK RTC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_S_IRQHandler
+        B RTC_S_IRQHandler
+
+        PUBWEAK TAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_IRQHandler
+        B TAMP_IRQHandler
+
+        PUBWEAK RAMCFG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RAMCFG_IRQHandler
+        B RAMCFG_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK FLASH_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_S_IRQHandler
+        B FLASH_S_IRQHandler
+
+        PUBWEAK GTZC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GTZC_IRQHandler
+        B GTZC_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK RCC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_S_IRQHandler
+        B RCC_S_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK EXTI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_IRQHandler
+        B EXTI5_IRQHandler
+
+        PUBWEAK EXTI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI6_IRQHandler
+        B EXTI6_IRQHandler
+
+        PUBWEAK EXTI7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI7_IRQHandler
+        B EXTI7_IRQHandler
+
+        PUBWEAK EXTI8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI8_IRQHandler
+        B EXTI8_IRQHandler
+
+        PUBWEAK EXTI9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_IRQHandler
+        B EXTI9_IRQHandler
+
+        PUBWEAK EXTI10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_IRQHandler
+        B EXTI10_IRQHandler
+
+        PUBWEAK EXTI11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI11_IRQHandler
+        B EXTI11_IRQHandler
+
+        PUBWEAK EXTI12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI12_IRQHandler
+        B EXTI12_IRQHandler
+
+        PUBWEAK EXTI13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI13_IRQHandler
+        B EXTI13_IRQHandler
+
+        PUBWEAK EXTI14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI14_IRQHandler
+        B EXTI14_IRQHandler
+
+        PUBWEAK EXTI15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_IRQHandler
+        B EXTI15_IRQHandler
+
+        PUBWEAK GPDMA1_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel0_IRQHandler
+        B GPDMA1_Channel0_IRQHandler
+
+        PUBWEAK GPDMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel1_IRQHandler
+        B GPDMA1_Channel1_IRQHandler
+
+        PUBWEAK GPDMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel2_IRQHandler
+        B GPDMA1_Channel2_IRQHandler
+
+        PUBWEAK GPDMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel3_IRQHandler
+        B GPDMA1_Channel3_IRQHandler
+
+        PUBWEAK GPDMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel4_IRQHandler
+        B GPDMA1_Channel4_IRQHandler
+
+        PUBWEAK GPDMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel5_IRQHandler
+        B GPDMA1_Channel5_IRQHandler
+
+        PUBWEAK GPDMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel6_IRQHandler
+        B GPDMA1_Channel6_IRQHandler
+
+        PUBWEAK GPDMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel7_IRQHandler
+        B GPDMA1_Channel7_IRQHandler
+
+        PUBWEAK IWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IWDG_IRQHandler
+        B IWDG_IRQHandler
+
+        PUBWEAK SAES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAES_IRQHandler
+        B SAES_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK DAC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC1_IRQHandler
+        B DAC1_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC2_IRQHandler
+        B ADC2_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK USB_DRD_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_DRD_FS_IRQHandler
+        B USB_DRD_FS_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK UCPD1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UCPD1_IRQHandler
+        B UCPD1_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+        B USART6_IRQHandler
+
+        PUBWEAK GPDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel0_IRQHandler
+        B GPDMA2_Channel0_IRQHandler
+
+        PUBWEAK GPDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel1_IRQHandler
+        B GPDMA2_Channel1_IRQHandler
+
+        PUBWEAK GPDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel2_IRQHandler
+        B GPDMA2_Channel2_IRQHandler
+
+        PUBWEAK GPDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel3_IRQHandler
+        B GPDMA2_Channel3_IRQHandler
+
+        PUBWEAK GPDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel4_IRQHandler
+        B GPDMA2_Channel4_IRQHandler
+
+        PUBWEAK GPDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel5_IRQHandler
+        B GPDMA2_Channel5_IRQHandler
+
+        PUBWEAK GPDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel6_IRQHandler
+        B GPDMA2_Channel6_IRQHandler
+
+        PUBWEAK GPDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel7_IRQHandler
+        B GPDMA2_Channel7_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK ICACHE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ICACHE_IRQHandler
+        B ICACHE_IRQHandler
+
+        PUBWEAK DCACHE1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCACHE1_IRQHandler
+        B DCACHE1_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK OTFDEC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+        B OTFDEC1_IRQHandler
+
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK HASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_IRQHandler
+        B HASH_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM12_IRQHandler
+        B TIM12_IRQHandler
+
+        PUBWEAK I3C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_EV_IRQHandler
+        B I3C1_EV_IRQHandler
+
+        PUBWEAK I3C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_ER_IRQHandler
+        B I3C1_ER_IRQHandler
+
+        PUBWEAK I3C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C2_EV_IRQHandler
+        B I3C2_EV_IRQHandler
+
+        PUBWEAK I3C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C2_ER_IRQHandler
+        B I3C2_ER_IRQHandler
+
+        END

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/startup_stm32h562xx.s

@@ -0,0 +1,887 @@
+;********************************************************************************
+;* File Name          : startup_stm32h562xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H562xx Non Crypto Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                    ; Reset Handler
+
+        DCD     NMI_Handler                      ; NMI Handler
+        DCD     HardFault_Handler                ; Hard Fault Handler
+        DCD     MemManage_Handler                ; MPU Fault Handler
+        DCD     BusFault_Handler                 ; Bus Fault Handler
+        DCD     UsageFault_Handler               ; Usage Fault Handler
+        DCD     SecureFault_Handler              ; Secure Fault Handler
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     SVC_Handler                      ; SVCall Handler
+        DCD     DebugMon_Handler                 ; Debug Monitor Handler
+        DCD     0                                ; Reserved
+        DCD     PendSV_Handler                   ; PendSV Handler
+        DCD     SysTick_Handler                  ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                  ; Window WatchDog
+        DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+        DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+        DCD     RTC_S_IRQHandler                 ; RTC secure interrupt
+        DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+        DCD     RAMCFG_IRQHandler                ; RAMCFG global
+        DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+        DCD     FLASH_S_IRQHandler               ; FLASH secure global interrupt
+        DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+        DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+        DCD     RCC_S_IRQHandler                 ; RCC secure global interrupt
+        DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+        DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+        DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+        DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+        DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+        DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+        DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+        DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+        DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+        DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+        DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+        DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+        DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+        DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+        DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+        DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+        DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+        DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+        DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+        DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+        DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+        DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+        DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+        DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+        DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+        DCD     0                                ; Reserved
+        DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+        DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+        DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+        DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+        DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+        DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+        DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+        DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+        DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+        DCD     TIM4_IRQHandler                  ; TIM4 global interrupt
+        DCD     TIM5_IRQHandler                  ; TIM5 global interrupt
+        DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+        DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+        DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+        DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+        DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+        DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+        DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+        DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+        DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+        DCD     USART1_IRQHandler                ; USART1 global interrupt
+        DCD     USART2_IRQHandler                ; USART2 global interrupt
+        DCD     USART3_IRQHandler                ; USART3 global interrupt
+        DCD     UART4_IRQHandler                 ; UART4 global interrupt
+        DCD     UART5_IRQHandler                 ; UART5 global interrupt
+        DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+        DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+        DCD     TIM8_BRK_IRQHandler              ; TIM8 Break interrupt
+        DCD     TIM8_UP_IRQHandler               ; TIM8 Update interrupt
+        DCD     TIM8_TRG_COM_IRQHandler          ; TIM8 Trigger and Commutation interrupt
+        DCD     TIM8_CC_IRQHandler               ; TIM8 Capture Compare interrupt
+        DCD     ADC2_IRQHandler                  ; ADC2 global interrupt
+        DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+        DCD     TIM15_IRQHandler                 ; TIM15 global interrupt
+        DCD     TIM16_IRQHandler                 ; TIM16 global interrupt
+        DCD     TIM17_IRQHandler                 ; TIM17 global interrupt
+        DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+        DCD     CRS_IRQHandler                   ; CRS global interrupt
+        DCD     UCPD1_IRQHandler                 ; UCPD1 global interrupt
+        DCD     FMC_IRQHandler                   ; FMC global interrupt
+        DCD     OCTOSPI1_IRQHandler              ; OctoSPI1 global interrupt
+        DCD     SDMMC1_IRQHandler                ; SDMMC1 global interrupt
+        DCD     I2C3_EV_IRQHandler               ; I2C2 Event interrupt
+        DCD     I2C3_ER_IRQHandler               ; I2C2 Error interrupt
+        DCD     SPI4_IRQHandler                  ; SPI4 global interrupt
+        DCD     SPI5_IRQHandler                  ; SPI5 global interrupt
+        DCD     SPI6_IRQHandler                  ; SPI6 global interrupt
+        DCD     USART6_IRQHandler                ; USART6 global interrupt
+        DCD     USART10_IRQHandler               ; USART10 global interrupt
+        DCD     USART11_IRQHandler               ; USART11 global interrupt
+        DCD     SAI1_IRQHandler                  ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                  ; Serial Audio Interface 2 global interrupt
+        DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+        DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+        DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+        DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+        DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+        DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+        DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+        DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+        DCD     UART7_IRQHandler                 ; UART7 global interrupt
+        DCD     UART8_IRQHandler                 ; UART8 global interrupt
+        DCD     UART9_IRQHandler                 ; UART9 global interrupt
+        DCD     UART12_IRQHandler                ; UART12 global interrupt
+        DCD     0                                ; Reserved
+        DCD     FPU_IRQHandler                   ; FPU global interrupt
+        DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+        DCD     DCACHE1_IRQHandler               ; DCACHE1 global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     DCMI_PSSI_IRQHandler             ; DCMI PSSI global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     CORDIC_IRQHandler                ; CORDIC global interrupt
+        DCD     FMAC_IRQHandler                  ; FMAC global interrupt
+        DCD     DTS_IRQHandler                   ; DTS global interrupt
+        DCD     RNG_IRQHandler                   ; RNG global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     HASH_IRQHandler                  ; HASH global interrupt
+        DCD     0                                ; Reserved
+        DCD     CEC_IRQHandler                   ; CEC global interrupt
+        DCD     TIM12_IRQHandler                 ; TIM12 global interrupt
+        DCD     TIM13_IRQHandler                 ; TIM13 global interrupt
+        DCD     TIM14_IRQHandler                 ; TIM14 global interrupt
+        DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+        DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+        DCD     I2C4_EV_IRQHandler               ; I2C4 Event interrupt
+        DCD     I2C4_ER_IRQHandler               ; I2C4 Error interrupt
+        DCD     LPTIM3_IRQHandler                ; LPTIM3 global interrupt
+        DCD     LPTIM4_IRQHandler                ; LPTIM4 global interrupt
+        DCD     LPTIM5_IRQHandler                ; LPTIM5 global interrupt
+        DCD     LPTIM6_IRQHandler                ; LPTIM6 global interrupt
+
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SecureFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SecureFault_Handler
+        B SecureFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_AVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+        B PVD_AVD_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK RTC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_S_IRQHandler
+        B RTC_S_IRQHandler
+
+        PUBWEAK TAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_IRQHandler
+        B TAMP_IRQHandler
+
+        PUBWEAK RAMCFG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RAMCFG_IRQHandler
+        B RAMCFG_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK FLASH_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_S_IRQHandler
+        B FLASH_S_IRQHandler
+
+        PUBWEAK GTZC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GTZC_IRQHandler
+        B GTZC_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK RCC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_S_IRQHandler
+        B RCC_S_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK EXTI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_IRQHandler
+        B EXTI5_IRQHandler
+
+        PUBWEAK EXTI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI6_IRQHandler
+        B EXTI6_IRQHandler
+
+        PUBWEAK EXTI7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI7_IRQHandler
+        B EXTI7_IRQHandler
+
+        PUBWEAK EXTI8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI8_IRQHandler
+        B EXTI8_IRQHandler
+
+        PUBWEAK EXTI9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_IRQHandler
+        B EXTI9_IRQHandler
+
+        PUBWEAK EXTI10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_IRQHandler
+        B EXTI10_IRQHandler
+
+        PUBWEAK EXTI11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI11_IRQHandler
+        B EXTI11_IRQHandler
+
+        PUBWEAK EXTI12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI12_IRQHandler
+        B EXTI12_IRQHandler
+
+        PUBWEAK EXTI13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI13_IRQHandler
+        B EXTI13_IRQHandler
+
+        PUBWEAK EXTI14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI14_IRQHandler
+        B EXTI14_IRQHandler
+
+        PUBWEAK EXTI15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_IRQHandler
+        B EXTI15_IRQHandler
+
+        PUBWEAK GPDMA1_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel0_IRQHandler
+        B GPDMA1_Channel0_IRQHandler
+
+        PUBWEAK GPDMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel1_IRQHandler
+        B GPDMA1_Channel1_IRQHandler
+
+        PUBWEAK GPDMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel2_IRQHandler
+        B GPDMA1_Channel2_IRQHandler
+
+        PUBWEAK GPDMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel3_IRQHandler
+        B GPDMA1_Channel3_IRQHandler
+
+        PUBWEAK GPDMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel4_IRQHandler
+        B GPDMA1_Channel4_IRQHandler
+
+        PUBWEAK GPDMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel5_IRQHandler
+        B GPDMA1_Channel5_IRQHandler
+
+        PUBWEAK GPDMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel6_IRQHandler
+        B GPDMA1_Channel6_IRQHandler
+
+        PUBWEAK GPDMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel7_IRQHandler
+        B GPDMA1_Channel7_IRQHandler
+
+        PUBWEAK IWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IWDG_IRQHandler
+        B IWDG_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK DAC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC1_IRQHandler
+        B DAC1_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC2_IRQHandler
+        B ADC2_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK USB_DRD_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_DRD_FS_IRQHandler
+        B USB_DRD_FS_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK UCPD1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UCPD1_IRQHandler
+        B UCPD1_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+        B SPI5_IRQHandler
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+        B SPI6_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+        B USART6_IRQHandler
+
+        PUBWEAK USART10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+        B USART10_IRQHandler
+
+        PUBWEAK USART11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART11_IRQHandler
+        B USART11_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+        PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK GPDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel0_IRQHandler
+        B GPDMA2_Channel0_IRQHandler
+
+        PUBWEAK GPDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel1_IRQHandler
+        B GPDMA2_Channel1_IRQHandler
+
+        PUBWEAK GPDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel2_IRQHandler
+        B GPDMA2_Channel2_IRQHandler
+
+        PUBWEAK GPDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel3_IRQHandler
+        B GPDMA2_Channel3_IRQHandler
+
+        PUBWEAK GPDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel4_IRQHandler
+        B GPDMA2_Channel4_IRQHandler
+
+        PUBWEAK GPDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel5_IRQHandler
+        B GPDMA2_Channel5_IRQHandler
+
+        PUBWEAK GPDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel6_IRQHandler
+        B GPDMA2_Channel6_IRQHandler
+
+        PUBWEAK GPDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel7_IRQHandler
+        B GPDMA2_Channel7_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+        B UART7_IRQHandler
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+        B UART8_IRQHandler
+
+        PUBWEAK UART9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+        B UART9_IRQHandler
+
+        PUBWEAK UART12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART12_IRQHandler
+        B UART12_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK ICACHE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ICACHE_IRQHandler
+        B ICACHE_IRQHandler
+
+        PUBWEAK DCACHE1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCACHE1_IRQHandler
+        B DCACHE1_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK CORDIC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CORDIC_IRQHandler
+        B CORDIC_IRQHandler
+
+        PUBWEAK FMAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMAC_IRQHandler
+        B FMAC_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK HASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_IRQHandler
+        B HASH_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler 
+        B CEC_IRQHandler
+
+        PUBWEAK TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM12_IRQHandler
+        B TIM12_IRQHandler
+
+        PUBWEAK TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM13_IRQHandler
+        B TIM13_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+
+        PUBWEAK I3C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_EV_IRQHandler
+        B I3C1_EV_IRQHandler
+
+        PUBWEAK I3C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_ER_IRQHandler
+        B I3C1_ER_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+        B LPTIM3_IRQHandler
+
+        PUBWEAK LPTIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+        B LPTIM4_IRQHandler
+
+        PUBWEAK LPTIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+        B LPTIM5_IRQHandler
+
+        PUBWEAK LPTIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM6_IRQHandler
+        B LPTIM6_IRQHandler
+
+        END

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/startup_stm32h563xx.s

@@ -0,0 +1,912 @@
+;********************************************************************************
+;* File Name          : startup_stm32h563xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H563xx Non Crypto Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                    ; Reset Handler
+
+        DCD     NMI_Handler                      ; NMI Handler
+        DCD     HardFault_Handler                ; Hard Fault Handler
+        DCD     MemManage_Handler                ; MPU Fault Handler
+        DCD     BusFault_Handler                 ; Bus Fault Handler
+        DCD     UsageFault_Handler               ; Usage Fault Handler
+        DCD     SecureFault_Handler              ; Secure Fault Handler
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     SVC_Handler                      ; SVCall Handler
+        DCD     DebugMon_Handler                 ; Debug Monitor Handler
+        DCD     0                                ; Reserved
+        DCD     PendSV_Handler                   ; PendSV Handler
+        DCD     SysTick_Handler                  ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                  ; Window WatchDog
+        DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+        DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+        DCD     RTC_S_IRQHandler                 ; RTC secure interrupt
+        DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+        DCD     RAMCFG_IRQHandler                ; RAMCFG global
+        DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+        DCD     FLASH_S_IRQHandler               ; FLASH secure global interrupt
+        DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+        DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+        DCD     RCC_S_IRQHandler                 ; RCC secure global interrupt
+        DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+        DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+        DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+        DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+        DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+        DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+        DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+        DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+        DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+        DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+        DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+        DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+        DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+        DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+        DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+        DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+        DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+        DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+        DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+        DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+        DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+        DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+        DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+        DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+        DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+        DCD     0                                ; Reserved
+        DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+        DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+        DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+        DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+        DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+        DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+        DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+        DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+        DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+        DCD     TIM4_IRQHandler                  ; TIM4 global interrupt
+        DCD     TIM5_IRQHandler                  ; TIM5 global interrupt
+        DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+        DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+        DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+        DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+        DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+        DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+        DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+        DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+        DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+        DCD     USART1_IRQHandler                ; USART1 global interrupt
+        DCD     USART2_IRQHandler                ; USART2 global interrupt
+        DCD     USART3_IRQHandler                ; USART3 global interrupt
+        DCD     UART4_IRQHandler                 ; UART4 global interrupt
+        DCD     UART5_IRQHandler                 ; UART5 global interrupt
+        DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+        DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+        DCD     TIM8_BRK_IRQHandler              ; TIM8 Break interrupt
+        DCD     TIM8_UP_IRQHandler               ; TIM8 Update interrupt
+        DCD     TIM8_TRG_COM_IRQHandler          ; TIM8 Trigger and Commutation interrupt
+        DCD     TIM8_CC_IRQHandler               ; TIM8 Capture Compare interrupt
+        DCD     ADC2_IRQHandler                  ; ADC2 global interrupt
+        DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+        DCD     TIM15_IRQHandler                 ; TIM15 global interrupt
+        DCD     TIM16_IRQHandler                 ; TIM16 global interrupt
+        DCD     TIM17_IRQHandler                 ; TIM17 global interrupt
+        DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+        DCD     CRS_IRQHandler                   ; CRS global interrupt
+        DCD     UCPD1_IRQHandler                 ; UCPD1 global interrupt
+        DCD     FMC_IRQHandler                   ; FMC global interrupt
+        DCD     OCTOSPI1_IRQHandler              ; OctoSPI1 global interrupt
+        DCD     SDMMC1_IRQHandler                ; SDMMC1 global interrupt
+        DCD     I2C3_EV_IRQHandler               ; I2C2 Event interrupt
+        DCD     I2C3_ER_IRQHandler               ; I2C2 Error interrupt
+        DCD     SPI4_IRQHandler                  ; SPI4 global interrupt
+        DCD     SPI5_IRQHandler                  ; SPI5 global interrupt
+        DCD     SPI6_IRQHandler                  ; SPI6 global interrupt
+        DCD     USART6_IRQHandler                ; USART6 global interrupt
+        DCD     USART10_IRQHandler               ; USART10 global interrupt
+        DCD     USART11_IRQHandler               ; USART11 global interrupt
+        DCD     SAI1_IRQHandler                  ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                  ; Serial Audio Interface 2 global interrupt
+        DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+        DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+        DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+        DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+        DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+        DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+        DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+        DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+        DCD     UART7_IRQHandler                 ; UART7 global interrupt
+        DCD     UART8_IRQHandler                 ; UART8 global interrupt
+        DCD     UART9_IRQHandler                 ; UART9 global interrupt
+        DCD     UART12_IRQHandler                ; UART12 global interrupt
+        DCD     SDMMC2_IRQHandler                ; SDMMC2 global interrupt
+        DCD     FPU_IRQHandler                   ; FPU global interrupt
+        DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+        DCD     DCACHE1_IRQHandler               ; DCACHE1 global interrupt
+        DCD     ETH_IRQHandler                   ; Ethernet global interrupt
+        DCD     ETH_WKUP_IRQHandler              ; Ethernet Wakeup global interrupt
+        DCD     DCMI_PSSI_IRQHandler             ; DCMI PSSI global interrupt
+        DCD     FDCAN2_IT0_IRQHandler            ; FDCAN2 interrupt 0
+        DCD     FDCAN2_IT1_IRQHandler            ; FDCAN2 interrupt 1
+        DCD     CORDIC_IRQHandler                ; CORDIC global interrupt
+        DCD     FMAC_IRQHandler                  ; FMAC global interrupt
+        DCD     DTS_IRQHandler                   ; DTS global interrupt
+        DCD     RNG_IRQHandler                   ; RNG global interrupt
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     HASH_IRQHandler                  ; HASH global interrupt
+        DCD     0                                ; Reserved
+        DCD     CEC_IRQHandler                   ; CEC global interrupt
+        DCD     TIM12_IRQHandler                 ; TIM12 global interrupt
+        DCD     TIM13_IRQHandler                 ; TIM13 global interrupt
+        DCD     TIM14_IRQHandler                 ; TIM14 global interrupt
+        DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+        DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+        DCD     I2C4_EV_IRQHandler               ; I2C4 Event interrupt
+        DCD     I2C4_ER_IRQHandler               ; I2C4 Error interrupt
+        DCD     LPTIM3_IRQHandler                ; LPTIM3 global interrupt
+        DCD     LPTIM4_IRQHandler                ; LPTIM4 global interrupt
+        DCD     LPTIM5_IRQHandler                ; LPTIM5 global interrupt
+        DCD     LPTIM6_IRQHandler                ; LPTIM6 global interrupt
+
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SecureFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SecureFault_Handler
+        B SecureFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_AVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+        B PVD_AVD_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK RTC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_S_IRQHandler
+        B RTC_S_IRQHandler
+
+        PUBWEAK TAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_IRQHandler
+        B TAMP_IRQHandler
+
+        PUBWEAK RAMCFG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RAMCFG_IRQHandler
+        B RAMCFG_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK FLASH_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_S_IRQHandler
+        B FLASH_S_IRQHandler
+
+        PUBWEAK GTZC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GTZC_IRQHandler
+        B GTZC_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK RCC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_S_IRQHandler
+        B RCC_S_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK EXTI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_IRQHandler
+        B EXTI5_IRQHandler
+
+        PUBWEAK EXTI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI6_IRQHandler
+        B EXTI6_IRQHandler
+
+        PUBWEAK EXTI7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI7_IRQHandler
+        B EXTI7_IRQHandler
+
+        PUBWEAK EXTI8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI8_IRQHandler
+        B EXTI8_IRQHandler
+
+        PUBWEAK EXTI9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_IRQHandler
+        B EXTI9_IRQHandler
+
+        PUBWEAK EXTI10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_IRQHandler
+        B EXTI10_IRQHandler
+
+        PUBWEAK EXTI11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI11_IRQHandler
+        B EXTI11_IRQHandler
+
+        PUBWEAK EXTI12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI12_IRQHandler
+        B EXTI12_IRQHandler
+
+        PUBWEAK EXTI13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI13_IRQHandler
+        B EXTI13_IRQHandler
+
+        PUBWEAK EXTI14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI14_IRQHandler
+        B EXTI14_IRQHandler
+
+        PUBWEAK EXTI15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_IRQHandler
+        B EXTI15_IRQHandler
+
+        PUBWEAK GPDMA1_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel0_IRQHandler
+        B GPDMA1_Channel0_IRQHandler
+
+        PUBWEAK GPDMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel1_IRQHandler
+        B GPDMA1_Channel1_IRQHandler
+
+        PUBWEAK GPDMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel2_IRQHandler
+        B GPDMA1_Channel2_IRQHandler
+
+        PUBWEAK GPDMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel3_IRQHandler
+        B GPDMA1_Channel3_IRQHandler
+
+        PUBWEAK GPDMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel4_IRQHandler
+        B GPDMA1_Channel4_IRQHandler
+
+        PUBWEAK GPDMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel5_IRQHandler
+        B GPDMA1_Channel5_IRQHandler
+
+        PUBWEAK GPDMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel6_IRQHandler
+        B GPDMA1_Channel6_IRQHandler
+
+        PUBWEAK GPDMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel7_IRQHandler
+        B GPDMA1_Channel7_IRQHandler
+
+        PUBWEAK IWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IWDG_IRQHandler
+        B IWDG_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK DAC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC1_IRQHandler
+        B DAC1_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC2_IRQHandler
+        B ADC2_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK USB_DRD_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_DRD_FS_IRQHandler
+        B USB_DRD_FS_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK UCPD1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UCPD1_IRQHandler
+        B UCPD1_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+        B SPI5_IRQHandler
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+        B SPI6_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+        B USART6_IRQHandler
+
+        PUBWEAK USART10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+        B USART10_IRQHandler
+
+        PUBWEAK USART11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART11_IRQHandler
+        B USART11_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+        PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK GPDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel0_IRQHandler
+        B GPDMA2_Channel0_IRQHandler
+
+        PUBWEAK GPDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel1_IRQHandler
+        B GPDMA2_Channel1_IRQHandler
+
+        PUBWEAK GPDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel2_IRQHandler
+        B GPDMA2_Channel2_IRQHandler
+
+        PUBWEAK GPDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel3_IRQHandler
+        B GPDMA2_Channel3_IRQHandler
+
+        PUBWEAK GPDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel4_IRQHandler
+        B GPDMA2_Channel4_IRQHandler
+
+        PUBWEAK GPDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel5_IRQHandler
+        B GPDMA2_Channel5_IRQHandler
+
+        PUBWEAK GPDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel6_IRQHandler
+        B GPDMA2_Channel6_IRQHandler
+
+        PUBWEAK GPDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel7_IRQHandler
+        B GPDMA2_Channel7_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+        B UART7_IRQHandler
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+        B UART8_IRQHandler
+
+        PUBWEAK UART9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+        B UART9_IRQHandler
+
+        PUBWEAK UART12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART12_IRQHandler
+        B UART12_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+        B SDMMC2_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK ICACHE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ICACHE_IRQHandler
+        B ICACHE_IRQHandler
+
+        PUBWEAK DCACHE1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCACHE1_IRQHandler
+        B DCACHE1_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+        B ETH_IRQHandler
+
+        PUBWEAK ETH_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+        B ETH_WKUP_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK CORDIC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CORDIC_IRQHandler
+        B CORDIC_IRQHandler
+
+        PUBWEAK FMAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMAC_IRQHandler
+        B FMAC_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK HASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_IRQHandler
+        B HASH_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM12_IRQHandler
+        B TIM12_IRQHandler
+
+        PUBWEAK TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM13_IRQHandler
+        B TIM13_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+
+        PUBWEAK I3C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_EV_IRQHandler
+        B I3C1_EV_IRQHandler
+
+        PUBWEAK I3C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_ER_IRQHandler
+        B I3C1_ER_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+        B LPTIM3_IRQHandler
+
+        PUBWEAK LPTIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+        B LPTIM4_IRQHandler
+
+        PUBWEAK LPTIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+        B LPTIM5_IRQHandler
+
+        PUBWEAK LPTIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM6_IRQHandler
+        B LPTIM6_IRQHandler
+
+        END

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/iar/startup_stm32h573xx.s

@@ -0,0 +1,932 @@
+;********************************************************************************
+;* File Name          : startup_stm32h573xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H573xx Crypto Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2023 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                    ; Reset Handler
+
+        DCD     NMI_Handler                      ; NMI Handler
+        DCD     HardFault_Handler                ; Hard Fault Handler
+        DCD     MemManage_Handler                ; MPU Fault Handler
+        DCD     BusFault_Handler                 ; Bus Fault Handler
+        DCD     UsageFault_Handler               ; Usage Fault Handler
+        DCD     SecureFault_Handler              ; Secure Fault Handler
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     0                                ; Reserved
+        DCD     SVC_Handler                      ; SVCall Handler
+        DCD     DebugMon_Handler                 ; Debug Monitor Handler
+        DCD     0                                ; Reserved
+        DCD     PendSV_Handler                   ; PendSV Handler
+        DCD     SysTick_Handler                  ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                  ; Window WatchDog
+        DCD     PVD_AVD_IRQHandler               ; PVD/AVD through EXTI Line detection Interrupt
+        DCD     RTC_IRQHandler                   ; RTC non-secure interrupt
+        DCD     RTC_S_IRQHandler                 ; RTC secure interrupt
+        DCD     TAMP_IRQHandler                  ; Tamper non-secure interrupt
+        DCD     RAMCFG_IRQHandler                ; RAMCFG global
+        DCD     FLASH_IRQHandler                 ; FLASH non-secure global interrupt
+        DCD     FLASH_S_IRQHandler               ; FLASH secure global interrupt
+        DCD     GTZC_IRQHandler                  ; Global TrustZone Controller interrupt
+        DCD     RCC_IRQHandler                   ; RCC non-secure global interrupt
+        DCD     RCC_S_IRQHandler                 ; RCC secure global interrupt
+        DCD     EXTI0_IRQHandler                 ; EXTI Line0 interrupt
+        DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
+        DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
+        DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
+        DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+        DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
+        DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
+        DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
+        DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt
+        DCD     EXTI9_IRQHandler                 ; EXTI Line9 interrupt
+        DCD     EXTI10_IRQHandler                ; EXTI Line10 interrupt
+        DCD     EXTI11_IRQHandler                ; EXTI Line11 interrupt
+        DCD     EXTI12_IRQHandler                ; EXTI Line12 interrupt
+        DCD     EXTI13_IRQHandler                ; EXTI Line13 interrupt
+        DCD     EXTI14_IRQHandler                ; EXTI Line14 interrupt
+        DCD     EXTI15_IRQHandler                ; EXTI Line15 interrupt
+        DCD     GPDMA1_Channel0_IRQHandler       ; GPDMA1 Channel 0 global interrupt
+        DCD     GPDMA1_Channel1_IRQHandler       ; GPDMA1 Channel 1 global interrupt
+        DCD     GPDMA1_Channel2_IRQHandler       ; GPDMA1 Channel 2 global interrupt
+        DCD     GPDMA1_Channel3_IRQHandler       ; GPDMA1 Channel 3 global interrupt
+        DCD     GPDMA1_Channel4_IRQHandler       ; GPDMA1 Channel 4 global interrupt
+        DCD     GPDMA1_Channel5_IRQHandler       ; GPDMA1 Channel 5 global interrupt
+        DCD     GPDMA1_Channel6_IRQHandler       ; GPDMA1 Channel 6 global interrupt
+        DCD     GPDMA1_Channel7_IRQHandler       ; GPDMA1 Channel 7 global interrupt
+        DCD     IWDG_IRQHandler                  ; IWDG global interrupt
+        DCD     SAES_IRQHandler                  ; SAES global interrupt
+        DCD     ADC1_IRQHandler                  ; ADC1 global interrupt
+        DCD     DAC1_IRQHandler                  ; DAC1 global interrupt
+        DCD     FDCAN1_IT0_IRQHandler            ; FDCAN1 interrupt 0
+        DCD     FDCAN1_IT1_IRQHandler            ; FDCAN1 interrupt 1
+        DCD     TIM1_BRK_IRQHandler              ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler               ; TIM1 Update interrupt
+        DCD     TIM1_TRG_COM_IRQHandler          ; TIM1 Trigger and Commutation interrupt
+        DCD     TIM1_CC_IRQHandler               ; TIM1 Capture Compare interrupt
+        DCD     TIM2_IRQHandler                  ; TIM2 global interrupt
+        DCD     TIM3_IRQHandler                  ; TIM3 global interrupt
+        DCD     TIM4_IRQHandler                  ; TIM4 global interrupt
+        DCD     TIM5_IRQHandler                  ; TIM5 global interrupt
+        DCD     TIM6_IRQHandler                  ; TIM6 global interrupt
+        DCD     TIM7_IRQHandler                  ; TIM7 global interrupt
+        DCD     I2C1_EV_IRQHandler               ; I2C1 Event interrupt
+        DCD     I2C1_ER_IRQHandler               ; I2C1 Error interrupt
+        DCD     I2C2_EV_IRQHandler               ; I2C2 Event interrupt
+        DCD     I2C2_ER_IRQHandler               ; I2C2 Error interrupt
+        DCD     SPI1_IRQHandler                  ; SPI1 global interrupt
+        DCD     SPI2_IRQHandler                  ; SPI2 global interrupt
+        DCD     SPI3_IRQHandler                  ; SPI3 global interrupt
+        DCD     USART1_IRQHandler                ; USART1 global interrupt
+        DCD     USART2_IRQHandler                ; USART2 global interrupt
+        DCD     USART3_IRQHandler                ; USART3 global interrupt
+        DCD     UART4_IRQHandler                 ; UART4 global interrupt
+        DCD     UART5_IRQHandler                 ; UART5 global interrupt
+        DCD     LPUART1_IRQHandler               ; LPUART1 global interrupt
+        DCD     LPTIM1_IRQHandler                ; LPTIM1 global interrupt
+        DCD     TIM8_BRK_IRQHandler              ; TIM8 Break interrupt
+        DCD     TIM8_UP_IRQHandler               ; TIM8 Update interrupt
+        DCD     TIM8_TRG_COM_IRQHandler          ; TIM8 Trigger and Commutation interrupt
+        DCD     TIM8_CC_IRQHandler               ; TIM8 Capture Compare interrupt
+        DCD     ADC2_IRQHandler                  ; ADC2 global interrupt
+        DCD     LPTIM2_IRQHandler                ; LPTIM2 global interrupt
+        DCD     TIM15_IRQHandler                 ; TIM15 global interrupt
+        DCD     TIM16_IRQHandler                 ; TIM16 global interrupt
+        DCD     TIM17_IRQHandler                 ; TIM17 global interrupt
+        DCD     USB_DRD_FS_IRQHandler            ; USB DRD FS global interrupt
+        DCD     CRS_IRQHandler                   ; CRS global interrupt
+        DCD     UCPD1_IRQHandler                 ; UCPD1 global interrupt
+        DCD     FMC_IRQHandler                   ; FMC global interrupt
+        DCD     OCTOSPI1_IRQHandler              ; OctoSPI1 global interrupt
+        DCD     SDMMC1_IRQHandler                ; SDMMC1 global interrupt
+        DCD     I2C3_EV_IRQHandler               ; I2C2 Event interrupt
+        DCD     I2C3_ER_IRQHandler               ; I2C2 Error interrupt
+        DCD     SPI4_IRQHandler                  ; SPI4 global interrupt
+        DCD     SPI5_IRQHandler                  ; SPI5 global interrupt
+        DCD     SPI6_IRQHandler                  ; SPI6 global interrupt
+        DCD     USART6_IRQHandler                ; USART6 global interrupt
+        DCD     USART10_IRQHandler               ; USART10 global interrupt
+        DCD     USART11_IRQHandler               ; USART11 global interrupt
+        DCD     SAI1_IRQHandler                  ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                  ; Serial Audio Interface 2 global interrupt
+        DCD     GPDMA2_Channel0_IRQHandler       ; GPDMA2 Channel 0 global interrupt
+        DCD     GPDMA2_Channel1_IRQHandler       ; GPDMA2 Channel 1 global interrupt
+        DCD     GPDMA2_Channel2_IRQHandler       ; GPDMA2 Channel 2 global interrupt
+        DCD     GPDMA2_Channel3_IRQHandler       ; GPDMA2 Channel 3 global interrupt
+        DCD     GPDMA2_Channel4_IRQHandler       ; GPDMA2 Channel 4 global interrupt
+        DCD     GPDMA2_Channel5_IRQHandler       ; GPDMA2 Channel 5 global interrupt
+        DCD     GPDMA2_Channel6_IRQHandler       ; GPDMA2 Channel 6 global interrupt
+        DCD     GPDMA2_Channel7_IRQHandler       ; GPDMA2 Channel 7 global interrupt
+        DCD     UART7_IRQHandler                 ; UART7 global interrupt
+        DCD     UART8_IRQHandler                 ; UART8 global interrupt
+        DCD     UART9_IRQHandler                 ; UART9 global interrupt
+        DCD     UART12_IRQHandler                ; UART12 global interrupt
+        DCD     SDMMC2_IRQHandler                ; SDMMC2 global interrupt
+        DCD     FPU_IRQHandler                   ; FPU global interrupt
+        DCD     ICACHE_IRQHandler                ; Instruction cache global interrupt
+        DCD     DCACHE1_IRQHandler               ; DCACHE1 global interrupt
+        DCD     ETH_IRQHandler                   ; Ethernet global interrupt
+        DCD     ETH_WKUP_IRQHandler              ; Ethernet Wakeup global interrupt
+        DCD     DCMI_PSSI_IRQHandler             ; DCMI PSSI global interrupt
+        DCD     FDCAN2_IT0_IRQHandler            ; FDCAN2 interrupt 0
+        DCD     FDCAN2_IT1_IRQHandler            ; FDCAN2 interrupt 1
+        DCD     CORDIC_IRQHandler                ; CORDIC global interrupt
+        DCD     FMAC_IRQHandler                  ; FMAC global interrupt
+        DCD     DTS_IRQHandler                   ; DTS global interrupt
+        DCD     RNG_IRQHandler                   ; RNG global interrupt
+        DCD     OTFDEC1_IRQHandler               ; OTFDEC1 global interrupt
+        DCD     AES_IRQHandler                   ; AES global interrupt
+        DCD     HASH_IRQHandler                  ; HASH global interrupt
+        DCD     PKA_IRQHandler                   ; PKA global interrupt
+        DCD     CEC_IRQHandler                   ; CEC global interrupt
+        DCD     TIM12_IRQHandler                 ; TIM12 global interrupt
+        DCD     TIM13_IRQHandler                 ; TIM13 global interrupt
+        DCD     TIM14_IRQHandler                 ; TIM14 global interrupt
+        DCD     I3C1_EV_IRQHandler               ; I3C1 Event interrupt
+        DCD     I3C1_ER_IRQHandler               ; I3C1 Error interrupt
+        DCD     I2C4_EV_IRQHandler               ; I2C4 Event interrupt
+        DCD     I2C4_ER_IRQHandler               ; I2C4 Error interrupt
+        DCD     LPTIM3_IRQHandler                ; LPTIM3 global interrupt
+        DCD     LPTIM4_IRQHandler                ; LPTIM4 global interrupt
+        DCD     LPTIM5_IRQHandler                ; LPTIM5 global interrupt
+        DCD     LPTIM6_IRQHandler                ; LPTIM6 global interrupt
+
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SecureFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SecureFault_Handler
+        B SecureFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_AVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+        B PVD_AVD_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK RTC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_S_IRQHandler
+        B RTC_S_IRQHandler
+
+        PUBWEAK TAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_IRQHandler
+        B TAMP_IRQHandler
+
+        PUBWEAK RAMCFG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RAMCFG_IRQHandler
+        B RAMCFG_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK FLASH_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_S_IRQHandler
+        B FLASH_S_IRQHandler
+
+        PUBWEAK GTZC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GTZC_IRQHandler
+        B GTZC_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK RCC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_S_IRQHandler
+        B RCC_S_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK EXTI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_IRQHandler
+        B EXTI5_IRQHandler
+
+        PUBWEAK EXTI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI6_IRQHandler
+        B EXTI6_IRQHandler
+
+        PUBWEAK EXTI7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI7_IRQHandler
+        B EXTI7_IRQHandler
+
+        PUBWEAK EXTI8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI8_IRQHandler
+        B EXTI8_IRQHandler
+
+        PUBWEAK EXTI9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_IRQHandler
+        B EXTI9_IRQHandler
+
+        PUBWEAK EXTI10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_IRQHandler
+        B EXTI10_IRQHandler
+
+        PUBWEAK EXTI11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI11_IRQHandler
+        B EXTI11_IRQHandler
+
+        PUBWEAK EXTI12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI12_IRQHandler
+        B EXTI12_IRQHandler
+
+        PUBWEAK EXTI13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI13_IRQHandler
+        B EXTI13_IRQHandler
+
+        PUBWEAK EXTI14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI14_IRQHandler
+        B EXTI14_IRQHandler
+
+        PUBWEAK EXTI15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_IRQHandler
+        B EXTI15_IRQHandler
+
+        PUBWEAK GPDMA1_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel0_IRQHandler
+        B GPDMA1_Channel0_IRQHandler
+
+        PUBWEAK GPDMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel1_IRQHandler
+        B GPDMA1_Channel1_IRQHandler
+
+        PUBWEAK GPDMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel2_IRQHandler
+        B GPDMA1_Channel2_IRQHandler
+
+        PUBWEAK GPDMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel3_IRQHandler
+        B GPDMA1_Channel3_IRQHandler
+
+        PUBWEAK GPDMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel4_IRQHandler
+        B GPDMA1_Channel4_IRQHandler
+
+        PUBWEAK GPDMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel5_IRQHandler
+        B GPDMA1_Channel5_IRQHandler
+
+        PUBWEAK GPDMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel6_IRQHandler
+        B GPDMA1_Channel6_IRQHandler
+
+        PUBWEAK GPDMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA1_Channel7_IRQHandler
+        B GPDMA1_Channel7_IRQHandler
+
+        PUBWEAK IWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IWDG_IRQHandler
+        B IWDG_IRQHandler
+
+        PUBWEAK SAES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAES_IRQHandler
+        B SAES_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK DAC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC1_IRQHandler
+        B DAC1_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC2_IRQHandler
+        B ADC2_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK USB_DRD_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_DRD_FS_IRQHandler
+        B USB_DRD_FS_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK UCPD1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UCPD1_IRQHandler
+        B UCPD1_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+        B SPI5_IRQHandler
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+        B SPI6_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+        B USART6_IRQHandler
+
+        PUBWEAK USART10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+        B USART10_IRQHandler
+
+        PUBWEAK USART11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART11_IRQHandler
+        B USART11_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+        PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK GPDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel0_IRQHandler
+        B GPDMA2_Channel0_IRQHandler
+
+        PUBWEAK GPDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel1_IRQHandler
+        B GPDMA2_Channel1_IRQHandler
+
+        PUBWEAK GPDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel2_IRQHandler
+        B GPDMA2_Channel2_IRQHandler
+
+        PUBWEAK GPDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel3_IRQHandler
+        B GPDMA2_Channel3_IRQHandler
+
+        PUBWEAK GPDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel4_IRQHandler
+        B GPDMA2_Channel4_IRQHandler
+
+        PUBWEAK GPDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel5_IRQHandler
+        B GPDMA2_Channel5_IRQHandler
+
+        PUBWEAK GPDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel6_IRQHandler
+        B GPDMA2_Channel6_IRQHandler
+
+        PUBWEAK GPDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPDMA2_Channel7_IRQHandler
+        B GPDMA2_Channel7_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+        B UART7_IRQHandler
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+        B UART8_IRQHandler
+
+        PUBWEAK UART9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+        B UART9_IRQHandler
+
+        PUBWEAK UART12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART12_IRQHandler
+        B UART12_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+        B SDMMC2_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK ICACHE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ICACHE_IRQHandler
+        B ICACHE_IRQHandler
+
+        PUBWEAK DCACHE1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCACHE1_IRQHandler
+        B DCACHE1_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+        B ETH_IRQHandler
+
+        PUBWEAK ETH_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+        B ETH_WKUP_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK CORDIC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CORDIC_IRQHandler
+        B CORDIC_IRQHandler
+
+        PUBWEAK FMAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMAC_IRQHandler
+        B FMAC_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK OTFDEC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+        B OTFDEC1_IRQHandler
+
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK HASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_IRQHandler
+        B HASH_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM12_IRQHandler
+        B TIM12_IRQHandler
+
+        PUBWEAK TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM13_IRQHandler
+        B TIM13_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+
+        PUBWEAK I3C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_EV_IRQHandler
+        B I3C1_EV_IRQHandler
+
+        PUBWEAK I3C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I3C1_ER_IRQHandler
+        B I3C1_ER_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+        B LPTIM3_IRQHandler
+
+        PUBWEAK LPTIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+        B LPTIM4_IRQHandler
+
+        PUBWEAK LPTIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+        B LPTIM5_IRQHandler
+
+        PUBWEAK LPTIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM6_IRQHandler
+        B LPTIM6_IRQHandler
+
+        END

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c

@@ -0,0 +1,401 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h5xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32h5xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the HSI (64 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                     | HSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                              | 64000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                                | 64000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                           | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB3 Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        HSI Division factor                     | 1
+  *-----------------------------------------------------------------------------
+  *        PLL1_SRC                                | No clock
+  *-----------------------------------------------------------------------------
+  *        PLL1_M                                  | Prescaler disabled
+  *-----------------------------------------------------------------------------
+  *        PLL1_N                                  | 129
+  *-----------------------------------------------------------------------------
+  *        PLL1_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL1_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL1_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL1_FRACN                              | 0
+  *-----------------------------------------------------------------------------
+  *        PLL2_SRC                                | No clock
+  *-----------------------------------------------------------------------------
+  *        PLL2_M                                  | Prescaler disabled
+  *-----------------------------------------------------------------------------
+  *        PLL2_N                                  | 129
+  *-----------------------------------------------------------------------------
+  *        PLL2_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL2_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL2_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL2_FRACN                              | 0
+  *-----------------------------------------------------------------------------
+  *        PLL3_SRC                                | No clock
+  *-----------------------------------------------------------------------------
+  *        PLL3_M                                  | Prescaler disabled
+  *-----------------------------------------------------------------------------
+  *        PLL3_N                                  | 129
+  *-----------------------------------------------------------------------------
+  *        PLL3_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL3_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL3_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL3_FRACN                              | 0
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32H5xx_system
+  * @{
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32h5xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Defines
+  * @{
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (25000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    (4000000UL)  /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (64000000UL) /*!< Value of the Internal oscillator in Hz */
+#endif /* HSI_VALUE */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 64000000U;
+
+  const uint8_t  AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t  APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  uint32_t reg_opsr;
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+   SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR = RCC_CR_HSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR1 = 0U;
+  RCC->CFGR2 = 0U;
+
+  /* Reset HSEON, HSECSSON, HSEBYP, HSEEXT, HSIDIV, HSIKERON, CSION, CSIKERON, HSI48 and PLLxON bits */
+#if defined(RCC_CR_PLL3ON)
+  RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIDIV | RCC_CR_HSIKERON | \
+               RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
+#else
+  RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIDIV | RCC_CR_HSIKERON | \
+               RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON);
+#endif
+
+  /* Reset PLLxCFGR register */
+  RCC->PLL1CFGR = 0U;
+  RCC->PLL2CFGR = 0U;
+#if defined(RCC_CR_PLL3ON)
+  RCC->PLL3CFGR = 0U;
+#endif /* RCC_CR_PLL3ON */
+
+  /* Reset PLL1DIVR register */
+  RCC->PLL1DIVR = 0x01010280U;
+  /* Reset PLL1FRACR register */
+  RCC->PLL1FRACR = 0x00000000U;
+  /* Reset PLL2DIVR register */
+  RCC->PLL2DIVR = 0x01010280U;
+  /* Reset PLL2FRACR register */
+  RCC->PLL2FRACR = 0x00000000U;
+#if defined(RCC_CR_PLL3ON)
+  /* Reset PLL3DIVR register */
+  RCC->PLL3DIVR = 0x01010280U;
+  /* Reset PLL3FRACR register */
+  RCC->PLL3FRACR = 0x00000000U;
+#endif /* RCC_CR_PLL3ON */
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= ~(RCC_CR_HSEBYP);
+
+  /* Disable all interrupts */
+  RCC->CIER = 0U;
+
+  /* Configure the Vector Table location add offset address ------------------*/
+  #ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+  #else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+  #endif /* VECT_TAB_SRAM */
+
+  /* Check OPSR register to verify if there is an ongoing swap or option bytes update interrupted by a reset */
+  reg_opsr = FLASH->OPSR & FLASH_OPSR_CODE_OP;
+  if ((reg_opsr == FLASH_OPSR_CODE_OP) || (reg_opsr == (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1)))
+  {
+    /* Check FLASH Option Control Register access */
+    if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != 0U)
+    {
+      /* Authorizes the Option Byte registers programming */
+      FLASH->OPTKEYR = 0x08192A3BU;
+      FLASH->OPTKEYR = 0x4C5D6E7FU;
+    }
+    /* Launch the option bytes change operation */
+    FLASH->OPTCR |= FLASH_OPTCR_OPTSTART;
+
+    /* Lock the FLASH Option Control Register access */
+    FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
+  }
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
+  *              64 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+  float_t fracn1, pllvco;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR1 & RCC_CFGR1_SWS)
+  {
+  case 0x00UL:  /* HSI used as system clock source */
+    SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+    break;
+
+  case 0x08UL:  /* CSI used as system clock  source */
+    SystemCoreClock = CSI_VALUE;
+    break;
+
+  case 0x10UL:  /* HSE used as system clock  source */
+    SystemCoreClock = HSE_VALUE;
+    break;
+
+  case 0x18UL:  /* PLL1 used as system clock source */
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
+    pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos);
+    pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
+
+    switch (pllsource)
+    {
+    case 0x01UL:  /* HSI used as PLL clock source */
+      hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+      pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+                (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case 0x02UL:  /* CSI used as PLL clock source */
+      pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+                (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case 0x03UL:  /* HSE used as PLL clock source */
+      pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+                (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:  /* No clock sent to PLL*/
+      pllvco = (float_t) 0U;
+      break;
+    }
+
+    pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ;
+    SystemCoreClock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+
+    break;
+
+  default:
+    SystemCoreClock = HSI_VALUE;
+    break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx_ns.c

@@ -0,0 +1,208 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h5xx_ns.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+  *          to be used in non-secure application when the system implements
+  *          the TrustZone-M security.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at non-secure startup before
+  *                      branch to non-secure main program.
+  *                      This call is made inside the "startup_stm32h5xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the HSI (64 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to
+  *   configure the system clock before to branch to main secure program.
+  *   Later, when non-secure SystemInit() function is called, in "startup_stm32h5xx.s"
+  *   file, the system clock may have been updated from reset value by the main
+  *   secure program.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32H5xx_system
+  * @{
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32h5xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Defines
+  * @{
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (25000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    (4000000UL)  /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (64000000UL) /*!< Value of the Internal oscillator in Hz */
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 64000000U;
+
+  const uint8_t  AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t  APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  /* Nothing done in non-secure */
+
+  /* Non-secure main application shall call SystemCoreClockUpdate() to update */
+  /* the SystemCoreClock variable to insure non-secure application relies on  */
+  /* the initial clock reference set by secure application.                   */
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   From the non-secure application, the SystemCoreClock value is
+  *         retrieved from the secure domain via a Non-Secure Callable function
+  *         since the RCC peripheral may be protected with security attributes
+  *         that prevent to compute the SystemCoreClock variable from the RCC
+  *         peripheral registers.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
+  *              64 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  /* Get the SystemCoreClock value from the secure domain */
+  SystemCoreClock = SECURE_SystemCoreClockUpdate();
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

lib/main/STM32H5/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx_s.c

@@ -0,0 +1,430 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h5xx_s.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+  *          to be used in secure application when the system implements
+  *          the security.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32h5xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *      - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update
+  *                                        the variable SystemCoreClock and return
+  *                                        its value to the non-secure calling
+  *                                        application. It must be called whenever
+  *                                        the core clock is changed during program
+  *                                        execution.
+  *
+  *   After each device reset the HSI (64 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                     | HSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                              | 64000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                                | 64000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                           | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB3 Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        HSI Division factor                     | 1
+  *-----------------------------------------------------------------------------
+  *        PLL1_SRC                                | No clock
+  *-----------------------------------------------------------------------------
+  *        PLL1_M                                  | Prescaler disabled
+  *-----------------------------------------------------------------------------
+  *        PLL1_N                                  | 129
+  *-----------------------------------------------------------------------------
+  *        PLL1_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL1_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL1_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL1_FRACN                              | 0
+  *-----------------------------------------------------------------------------
+  *        PLL2_SRC                                | No clock
+  *-----------------------------------------------------------------------------
+  *        PLL2_M                                  | Prescaler disabled
+  *-----------------------------------------------------------------------------
+  *        PLL2_N                                  | 129
+  *-----------------------------------------------------------------------------
+  *        PLL2_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL2_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL2_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL2_FRACN                              | 0
+  *-----------------------------------------------------------------------------
+  *        PLL3_SRC                                | No clock
+  *-----------------------------------------------------------------------------
+  *        PLL3_M                                  | Prescaler disabled
+  *-----------------------------------------------------------------------------
+  *        PLL3_N                                  | 129
+  *-----------------------------------------------------------------------------
+  *        PLL3_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL3_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL3_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL3_FRACN                              | 0
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32H5xx_system
+  * @{
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32h5xx.h"
+#include "partition_stm32h5xx.h"  /* Trustzone-M core secure attributes */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+#if defined ( __ICCARM__ )
+#  define CMSE_NS_ENTRY __cmse_nonsecure_entry
+#else
+#  define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry))
+#endif
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Defines
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (25000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    (4000000UL)  /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (64000000UL) /*!< Value of the Internal oscillator in Hz */
+#endif /* HSI_VALUE */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 64000000U;
+
+  const uint8_t  AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t  APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H5xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  uint32_t reg_opsr;
+
+  /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */
+  TZ_SAU_Setup();
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));     /* set CP10 and CP11 Full Access */
+
+    SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR = RCC_CR_HSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR1 = 0U;
+  RCC->CFGR2 = 0U;
+
+  /* Reset HSEON, HSECSSON, HSEBYP, HSEEXT, HSIDIV, HSIKERON, CSION, CSIKERON, HSI48 and PLLxON bits */
+  RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIDIV | RCC_CR_HSIKERON | \
+               RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
+
+  /* Reset PLLxCFGR register */
+  RCC->PLL1CFGR = 0U;
+  RCC->PLL2CFGR = 0U;
+  RCC->PLL3CFGR = 0U;
+
+  /* Reset PLL1DIVR register */
+  RCC->PLL1DIVR = 0x01010280U;
+  /* Reset PLL1FRACR register */
+  RCC->PLL1FRACR = 0x00000000U;
+  /* Reset PLL2DIVR register */
+  RCC->PLL2DIVR = 0x01010280U;
+  /* Reset PLL2FRACR register */
+  RCC->PLL2FRACR = 0x00000000U;
+  /* Reset PLL3DIVR register */
+  RCC->PLL3DIVR = 0x01010280U;
+  /* Reset PLL3FRACR register */
+  RCC->PLL3FRACR = 0x00000000U;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= ~(RCC_CR_HSEBYP);
+
+  /* Disable all interrupts */
+  RCC->CIER = 0U;
+
+  /* Configure the Vector Table location add offset address ------------------*/
+  #ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+  #else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+  #endif /* VECT_TAB_SRAM */
+
+  /* Check OPSR register to verify if there is an ongoing swap or option bytes update interrupted by a reset */
+  reg_opsr = FLASH->OPSR & FLASH_OPSR_CODE_OP;
+  if ((reg_opsr == FLASH_OPSR_CODE_OP) || (reg_opsr == (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1)))
+  {
+    /* Check FLASH Option Control Registers access */
+    if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != 0U)
+    {
+      /* Authorizes the Option Byte register programming */
+      FLASH->OPTKEYR = 0x08192A3BU;
+      FLASH->OPTKEYR = 0x4C5D6E7FU;
+    }
+    /* Launch the option bytes change operation */
+    FLASH->OPTCR |= FLASH_OPTCR_OPTSTART;
+
+    /* Lock the FLASH Option Control Register access */
+    FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
+  }
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Depending on secure or non-secure compilation, the adequate RCC peripheral
+  *         memory are is accessed thanks to RCC alias defined in stm32h5xxxx.h device file
+  *         so either from RCC_S peripheral register mapped memory in secure or from
+  *         RCC_NS peripheral register mapped memory in non-secure.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
+  *              64 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+  float_t fracn1, pllvco;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR1 & RCC_CFGR1_SWS)
+  {
+  case 0x00UL:  /* HSI used as system clock source */
+    SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+    break;
+
+  case 0x08UL:  /* CSI used as system clock  source */
+    SystemCoreClock = CSI_VALUE;
+    break;
+
+  case 0x10UL:  /* HSE used as system clock  source */
+    SystemCoreClock = HSE_VALUE;
+    break;
+
+  case 0x18UL:  /* PLL1 used as system clock source */
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
+    pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos);
+    pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
+
+      switch (pllsource)
+      {
+      case 0x01UL:  /* HSI used as PLL clock source */
+        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+        pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+                  (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      case 0x02UL:  /* CSI used as PLL clock source */
+        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+                  (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      case 0x03UL:  /* HSE used as PLL clock source */
+          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
+                    (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default: /* No clock sent to PLL*/
+          pllvco = (float_t) 0U;
+        break;
+      }
+
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ;
+      SystemCoreClock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+
+      break;
+
+  default:
+    SystemCoreClock = HSI_VALUE;
+    break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+
+}
+
+/**
+  * @brief  Secure Non-Secure-Callable function to return the current
+  *         SystemCoreClock value after SystemCoreClock update.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  * @retval SystemCoreClock value (HCLK)
+  */
+CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void)
+{
+  SystemCoreClockUpdate();
+
+  return SystemCoreClock;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

lib/main/STM32H5/Drivers/STM32H5xx_HAL_Driver/Inc/stm32_assert_template.h

@@ -0,0 +1,54 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @author  MCD Application Team
+  * @brief   STM32 assert template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32_assert.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+