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Rebased on to master (with merged CMS)

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This commit is contained in:
jflyper 2016-11-15 15:46:43 +09:00
commit 61a87480b3
341 changed files with 8778 additions and 8563 deletions
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17
src/main/drivers/serial_uart_stm32f10x.c
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@ -109,8 +109,8 @@ uartPort_t *serialUART1(uint32_t baudRate, portMode_t mode, portOptions_t option
s->USARTx = USART1;
#ifdef USE_UART1_RX_DMA
dmaInit(DMA1_CH5_HANDLER, OWNER_SERIAL_RX, 1);
s->rxDMAChannel = DMA1_Channel5;
s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
#endif
@ -118,7 +118,6 @@ uartPort_t *serialUART1(uint32_t baudRate, portMode_t mode, portOptions_t option
s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
RCC_ClockCmd(RCC_APB2(USART1), ENABLE);
RCC_ClockCmd(RCC_AHB(DMA1), ENABLE);
// UART1_TX PA9
// UART1_RX PA10
@ -127,17 +126,18 @@ uartPort_t *serialUART1(uint32_t baudRate, portMode_t mode, portOptions_t option
IOConfigGPIO(IOGetByTag(IO_TAG(PA9)), (options & SERIAL_BIDIR_PP) ? IOCFG_AF_PP : IOCFG_AF_OD);
} else {
if (mode & MODE_TX) {
IOInit(IOGetByTag(IO_TAG(PA9)), OWNER_SERIAL, RESOURCE_UART_TX, 1);
IOInit(IOGetByTag(IO_TAG(PA9)), OWNER_SERIAL_TX, 1);
IOConfigGPIO(IOGetByTag(IO_TAG(PA9)), IOCFG_AF_PP);
}
if (mode & MODE_RX) {
IOInit(IOGetByTag(IO_TAG(PA10)), OWNER_SERIAL, RESOURCE_UART_RX, 1);
IOInit(IOGetByTag(IO_TAG(PA10)), OWNER_SERIAL_RX, 1);
IOConfigGPIO(IOGetByTag(IO_TAG(PA10)), IOCFG_IPU);
}
}
// DMA TX Interrupt
dmaInit(DMA1_CH4_HANDLER, OWNER_SERIAL_TX, 1);
dmaSetHandler(DMA1_CH4_HANDLER, uart_tx_dma_IRQHandler, NVIC_PRIO_SERIALUART1_TXDMA, (uint32_t)&uartPort1);
#ifndef USE_UART1_RX_DMA
@ -189,7 +189,6 @@ uartPort_t *serialUART2(uint32_t baudRate, portMode_t mode, portOptions_t option
s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
RCC_ClockCmd(RCC_APB1(USART2), ENABLE);
RCC_ClockCmd(RCC_AHB(DMA1), ENABLE);
// UART2_TX PA2
// UART2_RX PA3
@ -198,12 +197,12 @@ uartPort_t *serialUART2(uint32_t baudRate, portMode_t mode, portOptions_t option
IOConfigGPIO(IOGetByTag(IO_TAG(PA2)), (options & SERIAL_BIDIR_PP) ? IOCFG_AF_PP : IOCFG_AF_OD);
} else {
if (mode & MODE_TX) {
IOInit(IOGetByTag(IO_TAG(PA2)), OWNER_SERIAL, RESOURCE_UART_TX, 2);
IOInit(IOGetByTag(IO_TAG(PA2)), OWNER_SERIAL_TX, 2);
IOConfigGPIO(IOGetByTag(IO_TAG(PA2)), IOCFG_AF_PP);
}
if (mode & MODE_RX) {
IOInit(IOGetByTag(IO_TAG(PA3)), OWNER_SERIAL, RESOURCE_UART_RX, 2);
IOInit(IOGetByTag(IO_TAG(PA3)), OWNER_SERIAL_RX, 2);
IOConfigGPIO(IOGetByTag(IO_TAG(PA3)), IOCFG_IPU);
}
}
@ -260,12 +259,12 @@ uartPort_t *serialUART3(uint32_t baudRate, portMode_t mode, portOptions_t option
IOConfigGPIO(IOGetByTag(IO_TAG(UART3_TX_PIN)), (options & SERIAL_BIDIR_PP) ? IOCFG_AF_PP : IOCFG_AF_OD);
} else {
if (mode & MODE_TX) {
IOInit(IOGetByTag(IO_TAG(UART3_TX_PIN)), OWNER_SERIAL, RESOURCE_UART_TX, 3);
IOInit(IOGetByTag(IO_TAG(UART3_TX_PIN)), OWNER_SERIAL_TX, 3);
IOConfigGPIO(IOGetByTag(IO_TAG(UART3_TX_PIN)), IOCFG_AF_PP);
}
if (mode & MODE_RX) {
IOInit(IOGetByTag(IO_TAG(UART3_RX_PIN)), OWNER_SERIAL, RESOURCE_UART_RX, 3);
IOInit(IOGetByTag(IO_TAG(UART3_RX_PIN)), OWNER_SERIAL_RX, 3);
IOConfigGPIO(IOGetByTag(IO_TAG(UART3_RX_PIN)), IOCFG_IPU);
}
}