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Fix ADC clock speed to be within specification

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ADC clock speed may be slightly higher, but there is no benefit in current code
This commit is contained in:
Petr Ledvina 2014-12-26 15:13:59 +01:00
parent bebf43d568
commit 6888de5192
1 changed files with 3 additions and 0 deletions
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3
src/main/drivers/adc_stm32f10x.c
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@ -117,6 +117,9 @@ void adcInit(drv_adc_config_t *init)
adcConfig[ADC_CURRENT].sampleTime = ADC_SampleTime_239Cycles5;
}
RCC_ADCCLKConfig(RCC_PCLK2_Div8); // 9MHz from 72MHz APB2 clock(HSE), 8MHz from 64MHz (HSI)
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);