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[H7] H7A3 support

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This commit is contained in:
jflyper 2020-09-29 23:03:20 +09:00
parent c6d70214f5
commit 697d0f7ed3
17 changed files with 1363 additions and 49 deletions
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20
src/main/drivers/timer_stm32h7xx.c
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@ -160,6 +160,7 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
};
#endif
uint32_t timerClock(TIM_TypeDef *tim)
{
int timpre;
@ -167,16 +168,27 @@ uint32_t timerClock(TIM_TypeDef *tim)
uint32_t ppre;
// Implement the table:
// RM0433 "Table 48. Ratio between clock timer and pclk"
// RM0433 (Rev 6) Table 52.
// RM0455 (Rev 3) Table 55.
// "Ratio between clock timer and pclk"
// (Tables are the same, just D2 or CD difference)
#if defined(STM32H743xx) || defined(STM32H750xx)
#define PERIPH_PRESCALER(bus) ((RCC->D2CFGR & RCC_D2CFGR_D2PPRE ## bus) >> RCC_D2CFGR_D2PPRE ## bus ## _Pos)
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
#define PERIPH_PRESCALER(bus) ((RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE ## bus) >> RCC_CDCFGR2_CDPPRE ## bus ## _Pos)
#else
#error Unknown MCU type
#endif
if (tim == TIM1 || tim == TIM8 || tim == TIM15 || tim == TIM16 || tim == TIM17) {
// Timers on APB2
pclk = HAL_RCC_GetPCLK2Freq();
ppre = (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos;
ppre = PERIPH_PRESCALER(2);
} else {
// Timers on APB1
pclk = HAL_RCC_GetPCLK1Freq();
ppre = (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos;
ppre = PERIPH_PRESCALER(1);
}
timpre = (RCC->CFGR & RCC_CFGR_TIMPRE) ? 1 : 0;
@ -189,5 +201,7 @@ uint32_t timerClock(TIM_TypeDef *tim)
};
return pclk * periphToKernel[index];
#undef PERIPH_PRESCALER
}
#endif