From b06e6616d40f29fa95e3c5bcbea78743fc2b1b51 Mon Sep 17 00:00:00 2001 From: Dominic Clifton Date: Fri, 4 Mar 2022 20:22:52 +0100 Subject: [PATCH 1/2] Fix missing ELRS GPIO configuration. GPIO pins need to be in INPUT mode before they can be read via IDR. The reason it's broken on the H7 is that the default gpio mode is ANALOG, not INPUT like it is on other MCUs, and that the busy pin is used before communication to the SX1280 and the busy wait function returns to early because the GPIO IDR bit is always 0 on the H7. i.e. not busy, when it is. It may also be broken on other MCUs prior to this. --- src/main/drivers/rx/rx_sx1280.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/drivers/rx/rx_sx1280.c b/src/main/drivers/rx/rx_sx1280.c index f8550d70ee..bf9a5cc5a4 100644 --- a/src/main/drivers/rx/rx_sx1280.c +++ b/src/main/drivers/rx/rx_sx1280.c @@ -208,6 +208,7 @@ bool sx1280Init(IO_t resetPin, IO_t busyPin) if (busyPin) { IOInit(busyPin, OWNER_RX_SPI_EXPRESSLRS_BUSY, 0); + IOConfigGPIO(busyPin, IOCFG_IN_FLOATING); } else { busyPin = IO_NONE; } From 89bc834d014e60164e02165f1e17ea4b3865d822 Mon Sep 17 00:00:00 2001 From: Dominic Clifton Date: Sat, 5 Mar 2022 20:25:45 +0100 Subject: [PATCH 2/2] ELRS - Fix EXTI irq clash and SPI transfer failure. When the same exti IRQ (not exti line) is used for both the BUSY and the DIO signals the IRQ levels cannot be different and neither can be a higher priority than the SPI DMA. --- src/main/drivers/nvic.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/main/drivers/nvic.h b/src/main/drivers/nvic.h index 05a601e1ad..216ed7ae05 100644 --- a/src/main/drivers/nvic.h +++ b/src/main/drivers/nvic.h @@ -28,11 +28,14 @@ #define NVIC_PRIO_SONAR_EXTI NVIC_BUILD_PRIORITY(2, 0) // maybe increase slightly #define NVIC_PRIO_DSHOT_DMA NVIC_BUILD_PRIORITY(2, 1) #define NVIC_PRIO_TRANSPONDER_DMA NVIC_BUILD_PRIORITY(3, 0) -#define NVIC_PRIO_RX_INT_EXTI NVIC_BUILD_PRIORITY(0x0f, 0x0f) -#define NVIC_PRIO_RX_BUSY_EXTI NVIC_BUILD_PRIORITY(3, 0) + +// RX_SPI must be lower priority than SPI DMA so EXTI ISRs don't interfere with SPI transfers and transfer complete callbacks +#define NVIC_PRIO_RX_SPI_INT_EXTI NVIC_BUILD_PRIORITY(3, 0x0f) +#define NVIC_PRIO_RX_INT_EXTI NVIC_BUILD_PRIORITY(3, 0x0f) +#define NVIC_PRIO_RX_BUSY_EXTI NVIC_BUILD_PRIORITY(3, 0x0f) + #define NVIC_PRIO_MPU_INT_EXTI NVIC_BUILD_PRIORITY(0x0f, 0x0f) #define NVIC_PRIO_MAG_INT_EXTI NVIC_BUILD_PRIORITY(0x0f, 0x0f) -#define NVIC_PRIO_RX_SPI_INT_EXTI NVIC_BUILD_PRIORITY(0x0f, 0x0f) #define NVIC_PRIO_WS2811_DMA NVIC_BUILD_PRIORITY(1, 2) // TODO - is there some reason to use high priority? (or to use DMA IRQ at all?) #define NVIC_PRIO_SERIALUART_TXDMA NVIC_BUILD_PRIORITY(1, 1) // Highest of all SERIALUARTx_TXDMA #define NVIC_PRIO_SERIALUART1_TXDMA NVIC_BUILD_PRIORITY(1, 1)