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Fix clock initialisation on new revision CJMCU boards.

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This commit is contained in:
Dominic Clifton 2015-01-03 18:58:42 +00:00
parent 56b8f4d37f
commit 754d0974c5
1 changed files with 5 additions and 0 deletions
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5
lib/main/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c
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@ -141,7 +141,12 @@ void SetSysClock(bool overclock)
*RCC_CRH |= (uint32_t)0x8 << (RCC_CFGR_PLLMULL9 >> 16); *RCC_CRH |= (uint32_t)0x8 << (RCC_CFGR_PLLMULL9 >> 16);
GPIOC->ODR &= (uint32_t)~(CAN_MCR_RESET); GPIOC->ODR &= (uint32_t)~(CAN_MCR_RESET);
#if defined(CJMCU)
// On CJMCU new revision boards (Late 2014) bit 15 of GPIOC->IDR is '1'.
RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL9;
#else
RCC_CFGR_PLLMUL = GPIOC->IDR & CAN_MCR_RESET ? hse_value = 12000000, RCC_CFGR_PLLMULL6 : RCC_CFGR_PLLMULL9; RCC_CFGR_PLLMUL = GPIOC->IDR & CAN_MCR_RESET ? hse_value = 12000000, RCC_CFGR_PLLMULL6 : RCC_CFGR_PLLMULL9;
#endif
switch (clocksrc) { switch (clocksrc) {
case SRC_HSE: case SRC_HSE:
if (overclock) { if (overclock) {