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All SPI are fed with same clock (36MHz) on F1 and F3

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This commit is contained in:
jflyper 2017-08-23 19:36:21 +09:00
parent 7a66260713
commit 75f8e49a9a
2 changed files with 8 additions and 4 deletions
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6
src/main/drivers/bus_spi.c
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@ -263,16 +263,18 @@ void spiSetDivisor(SPI_TypeDef *instance, uint16_t divisor)
{
#define BR_BITS ((BIT(5) | BIT(4) | BIT(3)))
// SPI2 and SPI3 are always on APB1/AHB1 which PCLK is half that of APB2/AHB2.
#if !(defined(STM32F1) || defined(STM32F3))
// SPI2 and SPI3 are on APB1/AHB1 which PCLK is half that of APB2/AHB2.
if (instance == SPI2 || instance == SPI3) {
divisor /= 2; // Safe for divisor == 0 or 1
}
#endif
SPI_Cmd(instance, DISABLE);
const uint16_t tempRegister = (instance->CR1 & ~BR_BITS);
instance->CR1 = (tempRegister | ((ffs(divisor | 0x100) - 2) << 3));
instance->CR1 = tempRegister | (divisor ? ((ffs(divisor | 0x100) - 2) << 3) : 0);
SPI_Cmd(instance, ENABLE);

6
src/main/drivers/bus_spi_ll.c
View file

@ -302,14 +302,16 @@ bool spiBusTransfer(const busDevice_t *bus, const uint8_t *txData, uint8_t *rxDa
void spiSetDivisor(SPI_TypeDef *instance, uint16_t divisor)
{
// SPI2 and SPI3 are always on APB1/AHB1 which PCLK is half that of APB2/AHB2.
#if !(defined(STM32F1) || defined(STM32F3))
// SPI2 and SPI3 are on APB1/AHB1 which PCLK is half that of APB2/AHB2.
if (instance == SPI2 || instance == SPI3) {
divisor /= 2; // Safe for divisor == 0 or 1
}
#endif
LL_SPI_Disable(instance);
LL_SPI_SetBaudRatePrescaler(instance, (ffs(divisor | 0x100) - 2) << SPI_CR1_BR_Pos);
LL_SPI_SetBaudRatePrescaler(instance, divisor ? (ffs(divisor | 0x100) - 2) << SPI_CR1_BR_Pos : 0);
LL_SPI_Enable(instance);
}