Tidy up of AT (timer defs), and STM specific init defines (#12339)

* Tidy up of AT Timer Definitions * Removed unnecessary F1 code. * Remove some STM specific define logic from init.c * As per renaming suggestion from @klutvott123
2025-07-18 22:05:17 +03:00 · 2023-02-10 14:01:38 +11:00 · 2023-02-10 14:01:38 +11:00 · 7b2d114c51
commit 7b2d114c51
parent 01df7f3057
13 changed files with 93 additions and 116 deletions
--- a/src/main/drivers/at32/pwm_output_at32bsp.c
+++ b/src/main/drivers/at32/pwm_output_at32bsp.c
@ -203,12 +203,7 @@ motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idl
        motors[motorIndex].io = IOGetByTag(tag);
        IOInit(motors[motorIndex].io, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex));

-#if defined(STM32F1)
-        IOConfigGPIO(motors[motorIndex].io, IOCFG_AF_PP);
-        //FIXME：AT32F1 可以配置pin mux ，需要在io里面改一下
-#else
        IOConfigGPIOAF(motors[motorIndex].io, IOCFG_AF_PP, timerHardware->alternateFunction);
-#endif

        /* standard PWM outputs */
        // margin of safety is 4 periods when unsynced
@ -279,11 +274,7 @@ void servoDevInit(const servoDevConfig_t *servoConfig)
            break;
        }

-#if defined(STM32F1)
-        IOConfigGPIO(servos[servoIndex].io, IOCFG_AF_PP);
-#else
        IOConfigGPIOAF(servos[servoIndex].io, IOCFG_AF_PP, timer->alternateFunction);
-#endif

        pwmOutConfig(&servos[servoIndex].channel, timer, PWM_TIMER_1MHZ, PWM_TIMER_1MHZ / servoConfig->servoPwmRate, servoConfig->servoCenterPulse, 0);
        servos[servoIndex].enabled = true;
--- a/src/main/drivers/at32/timer_at32f43x.c
+++ b/src/main/drivers/at32/timer_at32f43x.c
@ -48,7 +48,6 @@ const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
    { .TIMx = TMR13, .rcc = RCC_APB1(TMR13), .inputIrq = TMR8_OVF_TMR13_IRQn },
    { .TIMx = TMR14, .rcc = RCC_APB1(TMR14), .inputIrq = TMR8_TRG_HALL_TMR14_IRQn },
    { .TIMx = TMR20, .rcc = RCC_APB2(TMR20), .inputIrq = TMR20_CH_IRQn },
-
 };

 #if defined(USE_TIMER_MGMT)
@ -74,7 +73,6 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
    DEF_TIM(TMR1,  CH3,  PA10, TIM_USE_ANY, 0, 0,  0),
    DEF_TIM(TMR1,  CH4,  PA11, TIM_USE_ANY, 0, 0,  0),

-
 // Port B ORDER BY MUX 1 2 3
 //MUX1
    DEF_TIM(TMR1,  CH2N, PB0,  TIM_USE_ANY, 0, 0,  0),
@ -94,7 +92,7 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
    DEF_TIM(TMR20, CH1,  PB2,  TIM_USE_ANY, 0, 0,  0),
    DEF_TIM(TMR3,  CH1,  PB4,  TIM_USE_ANY, 0, 0,  0),
    DEF_TIM(TMR3,  CH2,  PB5,  TIM_USE_ANY, 0, 0,  0),
-    DEF_TIM(TMR4, CH1, PB6, TIM_USE_ANY, 0, 13, 9),//FOR TARGET TEST only 
+    DEF_TIM(TMR4,  CH1,  PB6,  TIM_USE_ANY, 0, 13, 9),
    DEF_TIM(TMR4,  CH2,  PB7,  TIM_USE_ANY, 0, 12, 9),
    DEF_TIM(TMR4,  CH3,  PB8,  TIM_USE_ANY, 0, 11, 9),
    DEF_TIM(TMR4,  CH4,  PB9,  TIM_USE_ANY, 0, 10, 9),
@ -109,7 +107,7 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
 // Port C ORDER BY MUX 1 2 3
 //MUX2
    DEF_TIM(TMR20, CH2,  PC2,  TIM_USE_ANY, 0, 0,  0),
-    DEF_TIM(TMR3, CH1, PC6, TIM_USE_ANY, 0, 0, 12),//for target test only 
+    DEF_TIM(TMR3,  CH1,  PC6,  TIM_USE_ANY, 0, 0,  12),
    DEF_TIM(TMR3,  CH2,  PC7,  TIM_USE_ANY, 0, 0,  12),
    DEF_TIM(TMR3,  CH3,  PC8,  TIM_USE_ANY, 0, 0,  12),
    DEF_TIM(TMR3,  CH4,  PC9,  TIM_USE_ANY, 0, 0,  12),
@ -125,19 +123,6 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {

 uint32_t timerClock(tmr_type *tim)
 {
-    /*
-     * RM0440 Rev.1
-     * 6.2.13 Timer clock
-     * The timer clock frequencies are automatically defined by hardware. There are two cases:
-     * 1. If the APB prescaler equals 1, the timer clock frequencies are set to the same frequency as that of the APB domain.
-     * 2. Otherwise, they are set to twice (×2) the frequency of the APB domain.
-     */
-    /*
-     * AN0085 雅特力AT32F435/7 MCU
-     *      定时器 TMRxClk源于 APB1/2 如果APB1/2 存在非1 分频时，TMRxClK 为APB1/2 时钟频率的2倍,与stm32 相同
-     *      例如：system_core_clock =288mhz , apb1/2 =144mhz  apb1_div=1 ,TMRxClk= apb1/2 *2 = 288Mhz
-     *
-     */
    UNUSED(tim);
    return system_core_clock;
 }
--- a/src/main/fc/init.c
+++ b/src/main/fc/init.c
@ -256,6 +256,7 @@ static void sdCardAndFSInit(void)
 }
 #endif

+#ifdef USE_SWDIO
 static void swdPinsInit(void)
 {
    IO_t io = IOGetByTag(DEFIO_TAG_E(PA13)); // SWDIO
@ -267,6 +268,7 @@ static void swdPinsInit(void)
        IOInit(io, OWNER_SWD, 0);
    }
 }
+#endif

 void init(void)
 {
@ -1007,28 +1009,26 @@ void init(void)

    setArmingDisabled(ARMING_DISABLED_BOOT_GRACE_TIME);

-    // On F4/F7 allocate SPI DMA streams before motor timers
-#if defined(STM32F4) || defined(STM32F7)
-#ifdef USE_SPI
+// allocate SPI DMA streams before motor timers
+#if defined(USE_SPI) && defined(USE_SPI_DMA_ENABLE_EARLY)
    // Attempt to enable DMA on all SPI busses
    spiInitBusDMA();
 #endif
-#endif

 #ifdef USE_MOTOR
    motorPostInit();
    motorEnable();
 #endif

-    // On H7/G4 allocate SPI DMA streams after motor timers as SPI DMA allocate will always be possible
-#if defined(STM32H7) || defined(STM32G4) || defined(AT32F435)
-#ifdef USE_SPI
+// allocate SPI DMA streams after motor timers as SPI DMA allocate will always be possible
+#if defined(USE_SPI) && defined(USE_SPI_DMA_ENABLE_LATE) && !defined(USE_SPI_DMA_ENABLE_EARLY)
    // Attempt to enable DMA on all SPI busses
    spiInitBusDMA();
-#endif
 #endif

+#ifdef USE_SWDIO
    swdPinsInit();
+#endif

    unusedPinsInit();

--- a/src/main/target/AT32F435/target.h
+++ b/src/main/target/AT32F435/target.h
@ -55,6 +55,7 @@

 #define USE_SPI
 #define USE_SPI_DEVICE_2
+#define USE_SPI_DMA_ENABLE_LATE

 // AT-START-F435 J7 connector SPI 1
 #define SPI2_SCK_PIN            PD1
--- a/src/main/target/STM32F405/target.h
+++ b/src/main/target/STM32F405/target.h
@ -61,6 +61,7 @@

 #define USE_SPI
 #define SPI_FULL_RECONFIGURABILITY
+#define USE_SPI_DMA_ENABLE_EARLY

 #define USE_VCP

--- a/src/main/target/STM32F411/target.h
+++ b/src/main/target/STM32F411/target.h
@ -58,6 +58,7 @@

 #define USE_SPI
 #define SPI_FULL_RECONFIGURABILITY
+#define USE_SPI_DMA_ENABLE_EARLY

 #define USE_VCP

--- a/src/main/target/STM32F745/target.h
+++ b/src/main/target/STM32F745/target.h
@ -68,6 +68,7 @@

 #define USE_SPI
 #define SPI_FULL_RECONFIGURABILITY
+#define USE_SPI_DMA_ENABLE_EARLY

 #define USE_VCP

--- a/src/main/target/STM32F7X2/target.h
+++ b/src/main/target/STM32F7X2/target.h
@ -60,6 +60,7 @@

 #define USE_SPI
 #define SPI_FULL_RECONFIGURABILITY
+#define USE_SPI_DMA_ENABLE_EARLY

 #define USE_VCP

--- a/src/main/target/STM32G47X/target.h
+++ b/src/main/target/STM32G47X/target.h
@ -58,6 +58,7 @@

 #define USE_SPI
 #define SPI_FULL_RECONFIGURABILITY
+#define USE_SPI_DMA_ENABLE_LATE

 #define USE_VCP

--- a/src/main/target/STM32H723/target.h
+++ b/src/main/target/STM32H723/target.h
@ -50,6 +50,8 @@
 #define SPI_FULL_RECONFIGURABILITY
 #endif

+#define USE_SPI_DMA_ENABLE_LATE
+
 #define USE_UART1
 #define USE_UART2
 #define USE_UART3
--- a/src/main/target/STM32H730/target.h
+++ b/src/main/target/STM32H730/target.h
@ -64,6 +64,8 @@
 #define SPI_FULL_RECONFIGURABILITY
 #endif

+#define USE_SPI_DMA_ENABLE_LATE
+
 #define USE_UART1
 #define USE_UART2
 #define USE_UART3
--- a/src/main/target/STM32H743/target.h
+++ b/src/main/target/STM32H743/target.h
@ -68,6 +68,7 @@

 #define USE_SPI
 #define SPI_FULL_RECONFIGURABILITY
+#define USE_SPI_DMA_ENABLE_LATE

 #define USE_VCP

--- a/src/main/target/STM32H750/target.h
+++ b/src/main/target/STM32H750/target.h
@ -64,17 +64,7 @@
 #define SPI_FULL_RECONFIGURABILITY
 #endif

-// Provide a default so that this target builds on the build server.
-#if !defined(USE_SPI)
-#define USE_SPI
-#define USE_SPI_DEVICE_1
-#define USE_SPI_DEVICE_2
-#define USE_SPI_DEVICE_3
-#define USE_SPI_DEVICE_4
-#define USE_SPI_DEVICE_5
-#define USE_SPI_DEVICE_6
-#define SPI_FULL_RECONFIGURABILITY
-#endif
+#define USE_SPI_DMA_ENABLE_LATE

 #define USE_UART1
 #define USE_UART2