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Tidy up of AT (timer defs), and STM specific init defines (#12339)

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* Tidy up of AT Timer Definitions
* Removed unnecessary F1 code.
* Remove some STM specific define logic from init.c
* As per renaming suggestion from @klutvott123
This commit is contained in:
J Blackman 2023-02-10 14:01:38 +11:00 • committed by GitHub
parent 01df7f3057
commit 7b2d114c51
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
13 changed files with 93 additions and 116 deletions
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9
src/main/drivers/at32/pwm_output_at32bsp.c
View file

@ -203,12 +203,7 @@ motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idl
motors[motorIndex].io = IOGetByTag(tag);
IOInit(motors[motorIndex].io, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex));
#if defined(STM32F1)
IOConfigGPIO(motors[motorIndex].io, IOCFG_AF_PP);
//FIXME：AT32F1 可以配置pin mux ，需要在io里面改一下
#else
IOConfigGPIOAF(motors[motorIndex].io, IOCFG_AF_PP, timerHardware->alternateFunction);
#endif
/* standard PWM outputs */
// margin of safety is 4 periods when unsynced
@ -279,11 +274,7 @@ void servoDevInit(const servoDevConfig_t *servoConfig)
break;
}
#if defined(STM32F1)
IOConfigGPIO(servos[servoIndex].io, IOCFG_AF_PP);
#else
IOConfigGPIOAF(servos[servoIndex].io, IOCFG_AF_PP, timer->alternateFunction);
#endif
pwmOutConfig(&servos[servoIndex].channel, timer, PWM_TIMER_1MHZ, PWM_TIMER_1MHZ / servoConfig->servoPwmRate, servoConfig->servoCenterPulse, 0);
servos[servoIndex].enabled = true;

161
src/main/drivers/at32/timer_at32f43x.c
View file

@ -33,111 +33,96 @@
const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
{ .TIMx = TMR1, .rcc = RCC_APB2(TMR1), .inputIrq = TMR1_CH_IRQn},
{ .TIMx = TMR2, .rcc = RCC_APB1(TMR2), .inputIrq = TMR2_GLOBAL_IRQn},
{ .TIMx = TMR3, .rcc = RCC_APB1(TMR3), .inputIrq = TMR3_GLOBAL_IRQn},
{ .TIMx = TMR4, .rcc = RCC_APB1(TMR4), .inputIrq = TMR4_GLOBAL_IRQn},
{ .TIMx = TMR5, .rcc = RCC_APB1(TMR5), .inputIrq = TMR5_GLOBAL_IRQn},
{ .TIMx = TMR6, .rcc = RCC_APB1(TMR6), .inputIrq = TMR6_DAC_GLOBAL_IRQn},
{ .TIMx = TMR7, .rcc = RCC_APB1(TMR7), .inputIrq = TMR7_GLOBAL_IRQn},
{ .TIMx = TMR8, .rcc = RCC_APB2(TMR8), .inputIrq = TMR8_CH_IRQn},
{ .TIMx = TMR9, .rcc = RCC_APB2(TMR9), .inputIrq = TMR1_BRK_TMR9_IRQn},
{ .TIMx = TMR10, .rcc = RCC_APB2(TMR10), .inputIrq = TMR1_OVF_TMR10_IRQn},
{ .TIMx = TMR11, .rcc = RCC_APB2(TMR11), .inputIrq = TMR1_TRG_HALL_TMR11_IRQn},
{ .TIMx = TMR12, .rcc = RCC_APB1(TMR12), .inputIrq = TMR8_BRK_TMR12_IRQn},
{ .TIMx = TMR13, .rcc = RCC_APB1(TMR13), .inputIrq = TMR8_OVF_TMR13_IRQn},
{ .TIMx = TMR14, .rcc = RCC_APB1(TMR14), .inputIrq = TMR8_TRG_HALL_TMR14_IRQn},
{ .TIMx = TMR20, .rcc = RCC_APB2(TMR20), .inputIrq = TMR20_CH_IRQn},
{ .TIMx = TMR1, .rcc = RCC_APB2(TMR1), .inputIrq = TMR1_CH_IRQn },
{ .TIMx = TMR2, .rcc = RCC_APB1(TMR2), .inputIrq = TMR2_GLOBAL_IRQn },
{ .TIMx = TMR3, .rcc = RCC_APB1(TMR3), .inputIrq = TMR3_GLOBAL_IRQn },
{ .TIMx = TMR4, .rcc = RCC_APB1(TMR4), .inputIrq = TMR4_GLOBAL_IRQn },
{ .TIMx = TMR5, .rcc = RCC_APB1(TMR5), .inputIrq = TMR5_GLOBAL_IRQn },
{ .TIMx = TMR6, .rcc = RCC_APB1(TMR6), .inputIrq = TMR6_DAC_GLOBAL_IRQn },
{ .TIMx = TMR7, .rcc = RCC_APB1(TMR7), .inputIrq = TMR7_GLOBAL_IRQn} ,
{ .TIMx = TMR8, .rcc = RCC_APB2(TMR8), .inputIrq = TMR8_CH_IRQn },
{ .TIMx = TMR9, .rcc = RCC_APB2(TMR9), .inputIrq = TMR1_BRK_TMR9_IRQn },
{ .TIMx = TMR10, .rcc = RCC_APB2(TMR10), .inputIrq = TMR1_OVF_TMR10_IRQn },
{ .TIMx = TMR11, .rcc = RCC_APB2(TMR11), .inputIrq = TMR1_TRG_HALL_TMR11_IRQn },
{ .TIMx = TMR12, .rcc = RCC_APB1(TMR12), .inputIrq = TMR8_BRK_TMR12_IRQn },
{ .TIMx = TMR13, .rcc = RCC_APB1(TMR13), .inputIrq = TMR8_OVF_TMR13_IRQn },
{ .TIMx = TMR14, .rcc = RCC_APB1(TMR14), .inputIrq = TMR8_TRG_HALL_TMR14_IRQn },
{ .TIMx = TMR20, .rcc = RCC_APB2(TMR20), .inputIrq = TMR20_CH_IRQn },
};
#if defined(USE_TIMER_MGMT)
const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
// Port A
DEF_TIM(TMR2, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH2, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1, PA8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH2, PA9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3, PA10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH4, PA11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH2, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1, PA8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH2, PA9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3, PA10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH4, PA11, TIM_USE_ANY, 0, 0, 0),
// Port B ORDER BY MUX 1 2 3
//MUX1
DEF_TIM(TMR1, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PB8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH3, PB10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PB13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
//MUX1
DEF_TIM(TMR1, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PB8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH3, PB10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PB13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
//MUX2
DEF_TIM(TMR3, CH3, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH4, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR20, CH1, PB2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH2, PB5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR4, CH1, PB6, TIM_USE_ANY, 0, 13, 9),//FOR TARGET TEST only
DEF_TIM(TMR4, CH2, PB7, TIM_USE_ANY, 0, 12, 9),
DEF_TIM(TMR4, CH3, PB8, TIM_USE_ANY, 0, 11, 9),
DEF_TIM(TMR4, CH4, PB9, TIM_USE_ANY, 0, 10, 9),
DEF_TIM(TMR5, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH1, PB12, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH3, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH4, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR20, CH1, PB2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH2, PB5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR4, CH1, PB6, TIM_USE_ANY, 0, 13, 9),
DEF_TIM(TMR4, CH2, PB7, TIM_USE_ANY, 0, 12, 9),
DEF_TIM(TMR4, CH3, PB8, TIM_USE_ANY, 0, 11, 9),
DEF_TIM(TMR4, CH4, PB9, TIM_USE_ANY, 0, 10, 9),
DEF_TIM(TMR5, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH1, PB12, TIM_USE_ANY, 0, 0, 0),
//MUX3
DEF_TIM(TMR8, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
// Port C ORDER BY MUX 1 2 3
//MUX2
DEF_TIM(TMR20, CH2, PC2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PC6, TIM_USE_ANY, 0, 0, 12),//for target test only
DEF_TIM(TMR3, CH2, PC7, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR3, CH3, PC8, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR3, CH4, PC9, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR5, CH2, PC10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH3, PC11, TIM_USE_ANY, 0, 0, 0),
//MUX2
DEF_TIM(TMR20, CH2, PC2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PC6, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR3, CH2, PC7, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR3, CH3, PC8, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR3, CH4, PC9, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR5, CH2, PC10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH3, PC11, TIM_USE_ANY, 0, 0, 0),
//MUX 3
DEF_TIM(TMR8, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
};
#endif
uint32_t timerClock(tmr_type *tim)
{
/*
* RM0440 Rev.1
* 6.2.13 Timer clock
* The timer clock frequencies are automatically defined by hardware. There are two cases:
* 1. If the APB prescaler equals 1, the timer clock frequencies are set to the same frequency as that of the APB domain.
* 2. Otherwise, they are set to twice (×2) the frequency of the APB domain.
*/
/*
* AN0085 雅特力AT32F435/7 MCU
* 定时器 TMRxClk源于 APB1/2 如果APB1/2 存在非1 分频时，TMRxClK 为APB1/2 时钟频率的2倍,与stm32 相同
* 例如：system_core_clock =288mhz , apb1/2 =144mhz apb1_div=1 ,TMRxClk= apb1/2 *2 = 288Mhz
*
*/
UNUSED(tim);
return system_core_clock;
}

16
src/main/fc/init.c
View file

@ -256,6 +256,7 @@ static void sdCardAndFSInit(void)
}
#endif
#ifdef USE_SWDIO
static void swdPinsInit(void)
{
IO_t io = IOGetByTag(DEFIO_TAG_E(PA13)); // SWDIO
@ -267,6 +268,7 @@ static void swdPinsInit(void)
IOInit(io, OWNER_SWD, 0);
}
}
#endif
void init(void)
{
@ -1007,28 +1009,26 @@ void init(void)
setArmingDisabled(ARMING_DISABLED_BOOT_GRACE_TIME);
// On F4/F7 allocate SPI DMA streams before motor timers
#if defined(STM32F4) || defined(STM32F7)
#ifdef USE_SPI
// allocate SPI DMA streams before motor timers
#if defined(USE_SPI) && defined(USE_SPI_DMA_ENABLE_EARLY)
// Attempt to enable DMA on all SPI busses
spiInitBusDMA();
#endif
#endif
#ifdef USE_MOTOR
motorPostInit();
motorEnable();
#endif
// On H7/G4 allocate SPI DMA streams after motor timers as SPI DMA allocate will always be possible
#if defined(STM32H7) || defined(STM32G4) || defined(AT32F435)
#ifdef USE_SPI
// allocate SPI DMA streams after motor timers as SPI DMA allocate will always be possible
#if defined(USE_SPI) && defined(USE_SPI_DMA_ENABLE_LATE) && !defined(USE_SPI_DMA_ENABLE_EARLY)
// Attempt to enable DMA on all SPI busses
spiInitBusDMA();
#endif
#endif
#ifdef USE_SWDIO
swdPinsInit();
#endif
unusedPinsInit();

1
src/main/target/AT32F435/target.h
View file

@ -55,6 +55,7 @@
#define USE_SPI
#define USE_SPI_DEVICE_2
#define USE_SPI_DMA_ENABLE_LATE
// AT-START-F435 J7 connector SPI 1
#define SPI2_SCK_PIN PD1

1
src/main/target/STM32F405/target.h
View file

@ -61,6 +61,7 @@
#define USE_SPI
#define SPI_FULL_RECONFIGURABILITY
#define USE_SPI_DMA_ENABLE_EARLY
#define USE_VCP

1
src/main/target/STM32F411/target.h
View file

@ -58,6 +58,7 @@
#define USE_SPI
#define SPI_FULL_RECONFIGURABILITY
#define USE_SPI_DMA_ENABLE_EARLY
#define USE_VCP

1
src/main/target/STM32F745/target.h
View file

@ -68,6 +68,7 @@
#define USE_SPI
#define SPI_FULL_RECONFIGURABILITY
#define USE_SPI_DMA_ENABLE_EARLY
#define USE_VCP

1
src/main/target/STM32F7X2/target.h
View file

@ -60,6 +60,7 @@
#define USE_SPI
#define SPI_FULL_RECONFIGURABILITY
#define USE_SPI_DMA_ENABLE_EARLY
#define USE_VCP

1
src/main/target/STM32G47X/target.h
View file

@ -58,6 +58,7 @@
#define USE_SPI
#define SPI_FULL_RECONFIGURABILITY
#define USE_SPI_DMA_ENABLE_LATE
#define USE_VCP

2
src/main/target/STM32H723/target.h
View file

@ -50,6 +50,8 @@
#define SPI_FULL_RECONFIGURABILITY
#endif
#define USE_SPI_DMA_ENABLE_LATE
#define USE_UART1
#define USE_UART2
#define USE_UART3

2
src/main/target/STM32H730/target.h
View file

@ -64,6 +64,8 @@
#define SPI_FULL_RECONFIGURABILITY
#endif
#define USE_SPI_DMA_ENABLE_LATE
#define USE_UART1
#define USE_UART2
#define USE_UART3

1
src/main/target/STM32H743/target.h
View file

@ -68,6 +68,7 @@
#define USE_SPI
#define SPI_FULL_RECONFIGURABILITY
#define USE_SPI_DMA_ENABLE_LATE
#define USE_VCP

12
src/main/target/STM32H750/target.h
View file

@ -64,17 +64,7 @@
#define SPI_FULL_RECONFIGURABILITY
#endif
// Provide a default so that this target builds on the build server.
#if !defined(USE_SPI)
#define USE_SPI
#define USE_SPI_DEVICE_1
#define USE_SPI_DEVICE_2
#define USE_SPI_DEVICE_3
#define USE_SPI_DEVICE_4
#define USE_SPI_DEVICE_5
#define USE_SPI_DEVICE_6
#define SPI_FULL_RECONFIGURABILITY
#endif
#define USE_SPI_DMA_ENABLE_LATE
#define USE_UART1
#define USE_UART2