mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-21 07:15:18 +03:00
STM32F4: Drivers
This commit is contained in:
blckmn
parent
96757c18a2
commit
7ca39bbde6
29 changed files with 2082 additions and 282 deletions
582
src/main/drivers/serial_uart_stm32f4xx.c
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582
src/main/drivers/serial_uart_stm32f4xx.c
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/*
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* This file is part of Cleanflight.
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*
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* Cleanflight is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Cleanflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "platform.h"
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#include "system.h"
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#include "io.h"
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#include "rcc.h"
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#include "nvic.h"
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#include "serial.h"
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#include "serial_uart.h"
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#include "serial_uart_impl.h"
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// Using RX DMA disables the use of receive callbacks
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//#define USE_USART1_RX_DMA
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//#define USE_USART2_RX_DMA
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//#define USE_USART3_RX_DMA
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//#define USE_USART4_RX_DMA
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//#define USE_USART5_RX_DMA
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//#define USE_USART6_RX_DMA
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#define UART_RX_BUFFER_SIZE UART1_RX_BUFFER_SIZE
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#define UART_TX_BUFFER_SIZE UART1_TX_BUFFER_SIZE
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typedef enum UARTDevice {
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UARTDEV_1 = 0,
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UARTDEV_2 = 1,
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UARTDEV_3 = 2,
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UARTDEV_4 = 3,
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UARTDEV_5 = 4,
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UARTDEV_6 = 5
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} UARTDevice;
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typedef struct uartDevice_s {
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USART_TypeDef* dev;
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uartPort_t port;
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uint32_t DMAChannel;
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DMA_Stream_TypeDef *txDMAStream;
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DMA_Stream_TypeDef *rxDMAStream;
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ioTag_t rx;
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ioTag_t tx;
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volatile uint8_t rxBuffer[UART_RX_BUFFER_SIZE];
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volatile uint8_t txBuffer[UART_TX_BUFFER_SIZE];
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uint32_t rcc_ahb1;
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rccPeriphTag_t rcc_apb2;
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rccPeriphTag_t rcc_apb1;
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uint8_t af;
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uint8_t txIrq;
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uint8_t rxIrq;
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uint32_t txPriority;
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uint32_t rxPriority;
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} uartDevice_t;
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//static uartPort_t uartPort[MAX_UARTS];
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#ifdef USE_USART1
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static uartDevice_t uart1 =
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{
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.DMAChannel = DMA_Channel_4,
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.txDMAStream = DMA2_Stream7,
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#ifdef USE_USART1_RX_DMA
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.rxDMAStream = DMA2_Stream5,
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#endif
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.dev = USART1,
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.rx = IO_TAG(USART1_RX_PIN),
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.tx = IO_TAG(USART1_TX_PIN),
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.af = GPIO_AF_USART1,
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#ifdef USART1_AHB1_PERIPHERALS
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.rcc_ahb1 = USART1_AHB1_PERIPHERALS,
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#endif
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.rcc_apb2 = RCC_APB2(USART1),
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.txIrq = DMA2_Stream7_IRQn,
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.rxIrq = USART1_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART1_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART1
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};
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#endif
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#ifdef USE_USART2
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static uartDevice_t uart2 =
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{
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_USART2_RX_DMA
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.rxDMAStream = DMA1_Stream5,
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#endif
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.txDMAStream = DMA1_Stream6,
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.dev = USART2,
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.rx = IO_TAG(USART2_RX_PIN),
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.tx = IO_TAG(USART2_TX_PIN),
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.af = GPIO_AF_USART2,
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#ifdef USART2_AHB1_PERIPHERALS
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.rcc_ahb1 = USART2_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(USART2),
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.txIrq = DMA1_Stream6_IRQn,
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.rxIrq = USART2_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART2_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART2
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};
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#endif
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#ifdef USE_USART3
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static uartDevice_t uart3 =
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{
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_USART3_RX_DMA
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.rxDMAStream = DMA1_Stream1,
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#endif
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.txDMAStream = DMA1_Stream3,
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.dev = USART3,
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.rx = IO_TAG(USART3_RX_PIN),
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.tx = IO_TAG(USART3_TX_PIN),
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.af = GPIO_AF_USART3,
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#ifdef USART3_AHB1_PERIPHERALS
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.rcc_ahb1 = USART3_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(USART3),
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.txIrq = DMA1_Stream3_IRQn,
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.rxIrq = USART3_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART3_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART3
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};
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#endif
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#ifdef USE_USART4
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static uartDevice_t uart4 =
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{
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_USART1_RX_DMA
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.rxDMAStream = DMA1_Stream2,
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#endif
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.txDMAStream = DMA1_Stream4,
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.dev = UART4,
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.rx = IO_TAG(USART4_RX_PIN),
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.tx = IO_TAG(USART4_TX_PIN),
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.af = GPIO_AF_UART4,
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#ifdef USART4_AHB1_PERIPHERALS
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.rcc_ahb1 = USART4_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(UART4),
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.txIrq = DMA1_Stream4_IRQn,
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.rxIrq = UART4_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART4_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART4
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};
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#endif
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#ifdef USE_USART5
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static uartDevice_t uart5 =
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{
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_USART1_RX_DMA
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.rxDMAStream = DMA1_Stream0,
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#endif
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.txDMAStream = DMA2_Stream7,
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.dev = UART5,
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.rx = IO_TAG(USART5_RX_PIN),
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.tx = IO_TAG(USART5_TX_PIN),
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.af = GPIO_AF_UART5,
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#ifdef USART5_AHB1_PERIPHERALS
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.rcc_ahb1 = USART5_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(UART5),
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.txIrq = DMA2_Stream7_IRQn,
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.rxIrq = UART5_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART5_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART5
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};
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#endif
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#ifdef USE_USART6
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static uartDevice_t uart6 =
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{
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.DMAChannel = DMA_Channel_5,
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#ifdef USE_USART6_RX_DMA
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.rxDMAStream = DMA2_Stream1,
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#endif
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.txDMAStream = DMA2_Stream6,
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.dev = USART6,
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.rx = IO_TAG(USART6_RX_PIN),
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.tx = IO_TAG(USART6_TX_PIN),
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.af = GPIO_AF_USART6,
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#ifdef USART6_AHB1_PERIPHERALS
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.rcc_ahb1 = USART6_AHB1_PERIPHERALS,
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#endif
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.rcc_apb2 = RCC_APB2(USART6),
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.txIrq = DMA2_Stream6_IRQn,
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.rxIrq = USART6_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART6_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART6
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};
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#endif
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static uartDevice_t* uartHardwareMap[] = {
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#ifdef USE_USART1
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&uart1,
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#else
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NULL,
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#endif
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#ifdef USE_USART2
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&uart2,
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#else
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NULL,
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#endif
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#ifdef USE_USART3
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&uart3,
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#else
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NULL,
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#endif
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#ifdef USE_USART4
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&uart4,
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#else
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NULL,
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#endif
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#ifdef USE_USART5
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&uart5,
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#else
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NULL,
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#endif
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#ifdef USE_USART6
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&uart6,
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#else
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NULL,
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#endif
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};
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void usartIrqHandler(uartPort_t *s)
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{
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if (!s->rxDMAStream && (USART_GetITStatus(s->USARTx, USART_IT_RXNE) == SET)) {
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if (s->port.callback) {
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s->port.callback(s->USARTx->DR);
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} else {
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s->port.rxBuffer[s->port.rxBufferHead] = s->USARTx->DR;
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s->port.rxBufferHead = (s->port.rxBufferHead + 1) % s->port.rxBufferSize;
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}
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}
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if (!s->txDMAStream && (USART_GetITStatus(s->USARTx, USART_IT_TXE) == SET)) {
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if (s->port.txBufferTail != s->port.txBufferHead) {
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USART_SendData(s->USARTx, s->port.txBuffer[s->port.txBufferTail]);
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s->port.txBufferTail = (s->port.txBufferTail + 1) % s->port.txBufferSize;
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} else {
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USART_ITConfig(s->USARTx, USART_IT_TXE, DISABLE);
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}
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}
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if (USART_GetITStatus(s->USARTx, USART_FLAG_ORE) == SET)
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{
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USART_ClearITPendingBit (s->USARTx, USART_IT_ORE);
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}
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}
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static void handleUsartTxDma(uartPort_t *s)
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{
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DMA_Cmd(s->txDMAStream, DISABLE);
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if (s->port.txBufferHead != s->port.txBufferTail)
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uartStartTxDMA(s);
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else
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s->txDMAEmpty = true;
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}
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uartPort_t *serialUSART(UARTDevice device, uint32_t baudRate, portMode_t mode, portOptions_t options)
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{
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uartPort_t *s;
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NVIC_InitTypeDef NVIC_InitStructure;
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uartDevice_t *uart = uartHardwareMap[device];
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if (!uart) return NULL;
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s = &(uart->port);
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s->port.vTable = uartVTable;
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s->port.baudRate = baudRate;
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s->port.rxBuffer = uart->rxBuffer;
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s->port.txBuffer = uart->txBuffer;
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s->port.rxBufferSize = sizeof(uart->rxBuffer);
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s->port.txBufferSize = sizeof(uart->txBuffer);
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s->USARTx = uart->dev;
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if (uart->rxDMAStream) {
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s->rxDMAChannel = uart->DMAChannel;
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s->rxDMAStream = uart->rxDMAStream;
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}
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s->txDMAChannel = uart->DMAChannel;
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s->txDMAStream = uart->txDMAStream;
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s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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IO_t tx = IOGetByTag(uart->tx);
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IO_t rx = IOGetByTag(uart->rx);
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if (uart->rcc_apb2)
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RCC_ClockCmd(uart->rcc_apb2, ENABLE);
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if (uart->rcc_apb1)
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RCC_ClockCmd(uart->rcc_apb1, ENABLE);
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if (uart->rcc_ahb1)
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RCC_AHB1PeriphClockCmd(uart->rcc_ahb1, ENABLE);
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if (options & SERIAL_BIDIR) {
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IOInit(tx, OWNER_SERIAL_TX, RESOURCE_USART);
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IOConfigGPIOAF(tx, IOCFG_AF_OD, uart->af);
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}
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else {
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if (mode & MODE_TX) {
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IOInit(tx, OWNER_SERIAL_TX, RESOURCE_USART);
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IOConfigGPIOAF(tx, IOCFG_AF_PP, uart->af);
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}
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if (mode & MODE_RX) {
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IOInit(rx, OWNER_SERIAL_RX, RESOURCE_USART);
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IOConfigGPIOAF(rx, IOCFG_AF_PP, uart->af);
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}
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}
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// DMA TX Interrupt
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NVIC_InitStructure.NVIC_IRQChannel = uart->txIrq;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(uart->txPriority);
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(uart->txPriority);
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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if (!(s->rxDMAChannel)) {
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NVIC_InitStructure.NVIC_IRQChannel = uart->rxIrq;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(uart->rxPriority);
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(uart->rxPriority);
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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}
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return s;
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}
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#ifdef USE_USART1
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uartPort_t *serialUSART1(uint32_t baudRate, portMode_t mode, portOptions_t options)
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{
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return serialUSART(UARTDEV_1, baudRate, mode, options);
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}
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// USART1 Tx DMA Handler
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void DMA2_Stream7_IRQHandler(void)
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{
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uartPort_t *s = &(uartHardwareMap[UARTDEV_1]->port);
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if(DMA_GetITStatus(s->txDMAStream,DMA_IT_TCIF7))
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{
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DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TCIF7);
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DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_HTIF7);
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if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_FEIF7)==SET)
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{
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DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_FEIF7);
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}
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handleUsartTxDma(s);
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}
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if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_TEIF7)==SET)
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{
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DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TEIF7);
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}
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if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_DMEIF7)==SET)
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{
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DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_DMEIF7);
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}
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}
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// USART1 Rx/Tx IRQ Handler
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void USART1_IRQHandler(void)
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{
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uartPort_t *s = &(uartHardwareMap[UARTDEV_1]->port);
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usartIrqHandler(s);
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}
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#endif
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#ifdef USE_USART2
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// USART2 - GPS or Spektrum or ?? (RX + TX by IRQ)
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uartPort_t *serialUSART2(uint32_t baudRate, portMode_t mode, portOptions_t options)
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{
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return serialUSART(UARTDEV_2, baudRate, mode, options);
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}
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// USART2 Tx DMA Handler
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void DMA1_Stream6_IRQHandler(void)
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{
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uartPort_t *s = &(uartHardwareMap[UARTDEV_2]->port);
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if(DMA_GetITStatus(s->txDMAStream,DMA_IT_TCIF6))
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{
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DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TCIF6);
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DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_HTIF6);
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if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_FEIF6)==SET)
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{
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DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_FEIF6);
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}
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handleUsartTxDma(s);
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}
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if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_TEIF6)==SET)
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{
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DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TEIF6);
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}
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if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_DMEIF6)==SET)
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{
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DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_DMEIF6);
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}
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}
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void USART2_IRQHandler(void)
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{
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uartPort_t *s = &(uartHardwareMap[UARTDEV_2]->port);
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usartIrqHandler(s);
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}
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#endif
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#ifdef USE_USART3
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// USART3
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uartPort_t *serialUSART3(uint32_t baudRate, portMode_t mode, portOptions_t options)
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{
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return serialUSART(UARTDEV_3, baudRate, mode, options);
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}
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// USART3 Tx DMA Handler
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void DMA1_Stream3_IRQHandler(void)
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{
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uartPort_t *s = &(uartHardwareMap[UARTDEV_3]->port);
|
||||
if(DMA_GetITStatus(s->txDMAStream,DMA_IT_TCIF3))
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TCIF3);
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_HTIF3);
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_FEIF3)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_FEIF3);
|
||||
}
|
||||
handleUsartTxDma(s);
|
||||
}
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_TEIF3)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TEIF3);
|
||||
}
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_DMEIF3)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_DMEIF3);
|
||||
}
|
||||
}
|
||||
|
||||
void USART3_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_3]->port);
|
||||
usartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_USART4
|
||||
// USART4
|
||||
uartPort_t *serialUSART4(uint32_t baudRate, portMode_t mode, portOptions_t options)
|
||||
{
|
||||
return serialUSART(UARTDEV_4, baudRate, mode, options);
|
||||
}
|
||||
|
||||
// USART4 Tx DMA Handler
|
||||
void DMA1_Stream4_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_4]->port);
|
||||
if(DMA_GetITStatus(s->txDMAStream,DMA_IT_TCIF4))
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TCIF4);
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_HTIF4);
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_FEIF4)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_FEIF4);
|
||||
}
|
||||
handleUsartTxDma(s);
|
||||
}
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_TEIF4)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TEIF4);
|
||||
}
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_DMEIF4)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_DMEIF4);
|
||||
}
|
||||
}
|
||||
|
||||
void UART4_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_4]->port);
|
||||
usartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_USART5
|
||||
// USART5
|
||||
uartPort_t *serialUSART5(uint32_t baudRate, portMode_t mode, portOptions_t options)
|
||||
{
|
||||
return serialUSART(UARTDEV_5, baudRate, mode, options);
|
||||
}
|
||||
|
||||
// USART5 Tx DMA Handler
|
||||
void DMA1_Stream7_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_5]->port);
|
||||
if(DMA_GetITStatus(s->txDMAStream,DMA_IT_TCIF7))
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TCIF7);
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_HTIF7);
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_FEIF7)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_FEIF7);
|
||||
}
|
||||
handleUsartTxDma(s);
|
||||
}
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_TEIF7)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TEIF7);
|
||||
}
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_DMEIF7)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_DMEIF7);
|
||||
}
|
||||
}
|
||||
|
||||
void UART5_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_5]->port);
|
||||
usartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_USART6
|
||||
// USART6
|
||||
uartPort_t *serialUSART6(uint32_t baudRate, portMode_t mode, portOptions_t options)
|
||||
{
|
||||
return serialUSART(UARTDEV_6, baudRate, mode, options);
|
||||
}
|
||||
|
||||
// USART6 Tx DMA Handler
|
||||
void DMA2_Stream6_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_6]->port);
|
||||
if(DMA_GetITStatus(s->txDMAStream,DMA_IT_TCIF6))
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TCIF6);
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_HTIF6);
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_FEIF6)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_FEIF6);
|
||||
}
|
||||
handleUsartTxDma(s);
|
||||
}
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_TEIF6)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_TEIF6);
|
||||
}
|
||||
if(DMA_GetFlagStatus(s->txDMAStream,DMA_IT_DMEIF6)==SET)
|
||||
{
|
||||
DMA_ClearITPendingBit(s->txDMAStream,DMA_IT_DMEIF6);
|
||||
}
|
||||
}
|
||||
|
||||
void USART6_IRQHandler(void)
|
||||
{
|
||||
uartPort_t *s = &(uartHardwareMap[UARTDEV_6]->port);
|
||||
usartIrqHandler(s);
|
||||
}
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue