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https://github.com/betaflight/betaflight.git
synced 2025-07-23 00:05:33 +03:00
Unify DMA stream and channel handling
This commit is contained in:
parent
e8125e57c9
commit
7ddfd7dea6
40 changed files with 421 additions and 446 deletions
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@ -46,10 +46,10 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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.reg = USART1,
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_UART1_RX_DMA
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.rxDMAStream = DMA2_Stream5,
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.rxDMAResource = (dmaResource_t *)DMA2_Stream5,
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#endif
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#ifdef USE_UART1_TX_DMA
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.txDMAStream = DMA2_Stream7,
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.txDMAResource = (dmaResource_t *)DMA2_Stream7,
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#endif
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.rxPins = { { DEFIO_TAG_E(PA10) }, { DEFIO_TAG_E(PB7) } },
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.txPins = { { DEFIO_TAG_E(PA9) }, { DEFIO_TAG_E(PB6) } },
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@ -67,10 +67,10 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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.reg = USART2,
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_UART2_RX_DMA
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.rxDMAStream = DMA1_Stream5,
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.rxDMAResource = (dmaResource_t *)DMA1_Stream5,
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#endif
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#ifdef USE_UART2_TX_DMA
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.txDMAStream = DMA1_Stream6,
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.txDMAResource = (dmaResource_t *)DMA1_Stream6,
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#endif
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.rxPins = { { DEFIO_TAG_E(PA3) }, { DEFIO_TAG_E(PD6) } },
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.txPins = { { DEFIO_TAG_E(PA2) }, { DEFIO_TAG_E(PD5) } },
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@ -88,10 +88,10 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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.reg = USART3,
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_UART3_RX_DMA
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.rxDMAStream = DMA1_Stream1,
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.rxDMAResource = (dmaResource_t *)DMA1_Stream1,
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#endif
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#ifdef USE_UART3_TX_DMA
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.txDMAStream = DMA1_Stream3,
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.txDMAResource = (dmaResource_t *)DMA1_Stream3,
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#endif
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.rxPins = { { DEFIO_TAG_E(PB11) }, { DEFIO_TAG_E(PC11) }, { DEFIO_TAG_E(PD9) } },
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.txPins = { { DEFIO_TAG_E(PB10) }, { DEFIO_TAG_E(PC10) }, { DEFIO_TAG_E(PD8) } },
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@ -109,10 +109,10 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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.reg = UART4,
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_UART4_RX_DMA
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.rxDMAStream = DMA1_Stream2,
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.rxDMAResource = (dmaResource_t *)DMA1_Stream2,
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#endif
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#ifdef USE_UART4_TX_DMA
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.txDMAStream = DMA1_Stream4,
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.txDMAResource = (dmaResource_t *)DMA1_Stream4,
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#endif
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.rxPins = { { DEFIO_TAG_E(PA1) }, { DEFIO_TAG_E(PC11) } },
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.txPins = { { DEFIO_TAG_E(PA0) }, { DEFIO_TAG_E(PC10) } },
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@ -130,10 +130,10 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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.reg = UART5,
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.DMAChannel = DMA_Channel_4,
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#ifdef USE_UART5_RX_DMA
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.rxDMAStream = DMA1_Stream0,
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.rxDMAResource = (dmaResource_t *)DMA1_Stream0,
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#endif
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#ifdef USE_UART5_TX_DMA
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.txDMAStream = DMA1_Stream7,
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.txDMAResource = (dmaResource_t *)DMA1_Stream7,
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#endif
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.rxPins = { { DEFIO_TAG_E(PD2) } },
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.txPins = { { DEFIO_TAG_E(PC12) } },
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@ -151,10 +151,10 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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.reg = USART6,
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.DMAChannel = DMA_Channel_5,
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#ifdef USE_UART6_RX_DMA
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.rxDMAStream = DMA2_Stream1,
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.rxDMAResource = (dmaResource_t *)DMA2_Stream1,
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#endif
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#ifdef USE_UART6_TX_DMA
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.txDMAStream = DMA2_Stream6,
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.txDMAResource = (dmaResource_t *)DMA2_Stream6,
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#endif
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.rxPins = { { DEFIO_TAG_E(PC7) }, { DEFIO_TAG_E(PG9) } },
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.txPins = { { DEFIO_TAG_E(PC6) }, { DEFIO_TAG_E(PG14) } },
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@ -218,19 +218,19 @@ uartPort_t *serialUART(UARTDevice_e device, uint32_t baudRate, portMode_e mode,
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s->USARTx = hardware->reg;
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if (hardware->rxDMAStream) {
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dmaInit(dmaGetIdentifier(hardware->rxDMAStream), OWNER_SERIAL_RX, RESOURCE_INDEX(device));
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if (hardware->rxDMAResource) {
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dmaInit(dmaGetIdentifier(hardware->rxDMAResource), OWNER_SERIAL_RX, RESOURCE_INDEX(device));
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s->rxDMAChannel = hardware->DMAChannel;
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s->rxDMAStream = hardware->rxDMAStream;
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s->rxDMAResource = hardware->rxDMAResource;
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s->rxDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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}
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if (hardware->txDMAStream) {
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const dmaIdentifier_e identifier = dmaGetIdentifier(hardware->txDMAStream);
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if (hardware->txDMAResource) {
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const dmaIdentifier_e identifier = dmaGetIdentifier(hardware->txDMAResource);
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dmaInit(identifier, OWNER_SERIAL_TX, RESOURCE_INDEX(device));
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dmaSetHandler(identifier, dmaIRQHandler, hardware->txPriority, (uint32_t)uart);
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s->txDMAChannel = hardware->DMAChannel;
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s->txDMAStream = hardware->txDMAStream;
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s->txDMAResource = hardware->txDMAResource;
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s->txDMAPeripheralBaseAddr = (uint32_t)&s->USARTx->DR;
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}
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@ -271,7 +271,7 @@ uartPort_t *serialUART(UARTDevice_e device, uint32_t baudRate, portMode_e mode,
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void uartIrqHandler(uartPort_t *s)
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{
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if (!s->rxDMAStream && (USART_GetITStatus(s->USARTx, USART_IT_RXNE) == SET)) {
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if (!s->rxDMAResource && (USART_GetITStatus(s->USARTx, USART_IT_RXNE) == SET)) {
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if (s->port.rxCallback) {
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s->port.rxCallback(s->USARTx->DR, s->port.rxCallbackData);
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} else {
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@ -280,7 +280,7 @@ void uartIrqHandler(uartPort_t *s)
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}
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}
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if (!s->txDMAStream && (USART_GetITStatus(s->USARTx, USART_IT_TXE) == SET)) {
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if (!s->txDMAResource && (USART_GetITStatus(s->USARTx, USART_IT_TXE) == SET)) {
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if (s->port.txBufferTail != s->port.txBufferHead) {
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USART_SendData(s->USARTx, s->port.txBuffer[s->port.txBufferTail]);
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s->port.txBufferTail = (s->port.txBufferTail + 1) % s->port.txBufferSize;
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