From 844683279ab2594ff6f1da12a96e0b63d39db45d Mon Sep 17 00:00:00 2001 From: Dominic Clifton Date: Fri, 22 Feb 2019 15:22:43 +0100 Subject: [PATCH] STM32H750 - Apply workaround to the SDMMC Errata 2.11.4 Issue: "Consecutive multiple block transfers can induce incorrect data length" Workaround: "8 SDMMC clock cycles must elapse before DTEN can be set." --- .../STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c b/lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c index aaa783a150..5de4b8ccc6 100755 --- a/lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c +++ b/lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c @@ -463,6 +463,17 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data->TransferDir |\ Data->TransferMode |\ Data->DPSM); + + // DC - See errata 2.11.4 - 8 SDMMC clock cycles must elapse before DTEN can be set. + // 32U below is used as a VERY rough guess that the SDMMC clock is 1/4 of the sytem clock, 8 * 4 = 32 and that the + // assembly below only takes 1 CPU cycle to run. All of which will be wrong, but right enough most of the time, especially + // when considering other processing overheads. + register uint32_t count = 32U; + do + { + count--; + } while(count > 0); + // DC - See errata 2.11.4 /* Write to SDMMC DCTRL */ MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);