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Merge pull request #11699 from blckmn/remove_opbl
Removing OPBL support.
This commit is contained in:
commit
86bd708e4c
11 changed files with 0 additions and 291 deletions
8
Makefile
8
Makefile
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@ -21,9 +21,6 @@ TARGET ?= STM32F405
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# Compile-time options
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OPTIONS ?=
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# compile for OpenPilot BootLoader support
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OPBL ?= no
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# compile for External Storage Bootloader support
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EXST ?= no
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@ -187,12 +184,7 @@ endif
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TARGET_DIR = $(ROOT)/src/main/target/$(BASE_TARGET)
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TARGET_DIR_SRC = $(notdir $(wildcard $(TARGET_DIR)/*.c))
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ifeq ($(OPBL),yes)
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TARGET_FLAGS := -DOPBL $(TARGET_FLAGS)
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.DEFAULT_GOAL := binary
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else
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.DEFAULT_GOAL := hex
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endif
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ifeq ($(CUSTOM_DEFAULTS_EXTENDED),yes)
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TARGET_FLAGS += -DUSE_CUSTOM_DEFAULTS=
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@ -1,177 +0,0 @@
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# Board - CC3D
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The OpenPilot Copter Control 3D aka CC3D is a board more tuned to Acrobatic flying or GPS based
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auto-piloting. It only has one sensor, the MPU6000 SPI based Accelerometer/Gyro.
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It also features a 16Mbit SPI based EEPROM chip. It has 6 ports labeled as inputs (one pin each)
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and 6 ports labeled as motor/servo outputs (3 pins each).
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If issues are found with this board please report via the [github issue tracker](https://github.com/cleanflight/cleanflight/issues).
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The board has a USB port directly connected to the processor. Other boards like the Naze and Flip32
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have an on-board USB to uart adapter which connect to the processor's serial port instead.
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The board cannot currently be used for hexacopters/octocopters.
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Tricopter & Airplane support is untested, please report success or failure if you try it.
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# Pinouts
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The 8 pin RC_Input connector has the following pinouts when used in RX_PPM/RX_SERIAL mode
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| Pin | Function | Notes |
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| --- | --------- | -------------------------------- |
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| 1 | Ground | |
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| 2 | +5V | |
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| 3 | Unused | |
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| 4 | SoftSerial1 TX / Sonar trigger | |
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| 5 | SoftSerial1 RX / Sonar Echo / RSSI_ADC | Used either for SOFTSERIAL, SONAR or RSSI_ADC*. Only one feature can be enabled at any time. |
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| 6 | Current | Enable `feature CURRENT_METER`. Connect to the output of a current sensor, 0v-3.3v input |
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| 7 | Battery Voltage sensor | Enable `feature VBAT`. Connect to main battery using a voltage divider, 0v-3.3v input |
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| 8 | PPM Input | Enable `feature RX_PPM` |
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*Connect to the output of a PWM-RSSI conditioner, 0v-3.3v input.
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The 6 pin RC_Output connector has the following pinouts when used in RX_PPM/RX_SERIAL mode
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| Pin | Function | Notes |
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| --- | ----------| ------|
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| 1 | MOTOR 1 | |
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| 2 | MOTOR 2 | |
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| 3 | MOTOR 3 | |
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| 4 | MOTOR 4 | |
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| 5 | LED Strip | |
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| 6 | Unused | |
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The 8 pin RC_Input connector has the following pinouts when used in RX_PARALLEL_PWM mode
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| Pin | Function | Notes |
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| --- | ---------| ------|
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| 1 | Ground | |
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| 2 | +5V | |
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| 3 | Unused | |
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| 4 | CH1 | |
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| 5 | CH2 | |
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| 6 | CH3 | |
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| 7 | CH4/Battery Voltage sensor | CH4 if battery voltage sensor is disabled |
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| 8 | CH5/CH4 | CH4 if battery voltage monitor is enabled|
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The 6 pin RC_Output connector has the following pinouts when used in RX_PARALLEL_PWM mode
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| Pin | Function | Notes |
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| --- | ---------| ------|
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| 1 | MOTOR 1 | |
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| 2 | MOTOR 2 | |
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| 3 | MOTOR 3 | |
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| 4 | MOTOR 4 | |
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| 5 | Unused | |
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| 6 | Unused | |
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# Serial Ports
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| Value | Identifier | Board Markings | Notes |
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| ----- | ------------ | -------------- | ------------------------------------------|
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| 1 | VCP | USB PORT | |
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| 2 | USART1 | MAIN PORT | Connected to an MCU controllable inverter |
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| 3 | USART3 | FLEX PORT | |
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| 4 | SoftSerial | RC connector | Pins 4 and 5 (Tx and Rx respectively) |
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The SoftSerial port is not available when RX_PARALLEL_PWM is used. The transmission data rate is limited to 19200 baud.
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To connect the GUI to the flight controller you just need a USB cable to use the Virtual Com Port (VCP) or you can use UART1 (Main Port).
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CLI access is only available via the VCP by default.
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# Main Port
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The main port has MSP support enabled on it by default.
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The main port is connected to an inverter which is automatically enabled as required. For example, if the main port is used for SBus Serial RX then an external inverter is not required.
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# Flex Port
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The flex port will be enabled in I2C mode unless USART3 is used. You can connect external I2C sensors and displays to this port.
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You cannot use USART3 and I2C at the same time.
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## Flex port pinout
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| Pin | Signal | Notes |
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| --- | ------------------ | ----------------------- |
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| 1 | GND | |
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| 2 | VCC unregulated | |
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| 3 | I2C SCL / UART3 TX | 3.3v level |
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| 4 | I2C SDA / UART3 RX | 3.3v level (5v tolerant |
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# Flashing
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Since CleanFlight version 1.11.0 "single binary image mode" is the only way to get CleanFlight on CC3D. Prior the version 1.11.0 there was a possibility to use "OpenPilot Bootloader compatible image mode", which allows you to easily switch between OpenPilot and CleanFlight, please refer to documentation from releases prior to 1.11.0 for more details.
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## Single binary image mode.
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The entire flash ram on the target processor is flashed with a single image.
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The image can be flashed by using a USB to UART adapter connected to the main port when the CC3D is put into the STM32 bootloader mode, achieved by powering on the CC3D with the SBL/3.3v pads bridged.
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# Restoring OpenPilot bootloader
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If you have a JLink debugger, you can use JLinkExe to flash the open pilot bootloader.
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1. Run JLinkExe `/Applications/SEGGER/JLink/JLinkExe`
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2. `device STM32F103CB`
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3. `r`
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4. `h`
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5. `loadbin opbl.bin, 0x08000000`
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6. `q`
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7. Re-plug CC3D.
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Here's an example session:
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```
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$ /Applications/SEGGER/JLink/JLinkExe
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SEGGER J-Link Commander V4.90c ('?' for help)
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Compiled Aug 29 2014 09:52:38
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DLL version V4.90c, compiled Aug 29 2014 09:52:33
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Firmware: J-Link ARM-OB STM32 compiled Aug 22 2012 19:52:04
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Hardware: V7.00
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S/N: -1
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Feature(s): RDI,FlashDL,FlashBP,JFlash,GDBFull
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VTarget = 3.300V
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Info: Could not measure total IR len. TDO is constant high.
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Info: Could not measure total IR len. TDO is constant high.
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No devices found on JTAG chain. Trying to find device on SWD.
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Info: Found SWD-DP with ID 0x1BA01477
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Info: Found Cortex-M3 r1p1, Little endian.
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Info: FPUnit: 6 code (BP) slots and 2 literal slots
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Info: TPIU fitted.
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Cortex-M3 identified.
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Target interface speed: 100 kHz
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J-Link>device STM32F103CB
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Info: Device "STM32F103CB" selected (128 KB flash, 20 KB RAM).
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Reconnecting to target...
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Info: Found SWD-DP with ID 0x1BA01477
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Info: Found SWD-DP with ID 0x1BA01477
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Info: Found Cortex-M3 r1p1, Little endian.
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Info: FPUnit: 6 code (BP) slots and 2 literal slots
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Info: TPIU fitted.
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J-Link>r
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Reset delay: 0 ms
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Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
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J-Link>h
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PC = 0800010C, CycleCnt = 00000000
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R0 = 0000000C, R1 = 0000003F, R2 = 00000000, R3 = 00000008
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R4 = 00003000, R5 = 023ACEFC, R6 = 200000F0, R7 = 20000304
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R8 = 023B92BC, R9 = 00000000, R10= ED691105, R11= F626177C
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R12= 000F0000
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SP(R13)= 20000934, MSP= 20000934, PSP= 20000934, R14(LR) = FFFFFFFF
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XPSR = 01000000: APSR = nzcvq, EPSR = 01000000, IPSR = 000 (NoException)
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CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00
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J-Link>loadbin opbl.bin, 0x08000000
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Downloading file [opbl.bin]...
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WARNING: CPU is running at low speed (8004 kHz).
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Info: J-Link: Flash download: Flash download into internal flash skipped. Flash contents already match
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Info: J-Link: Flash download: Total time needed: 0.898s (Prepare: 0.709s, Compare: 0.128s, Erase: 0.000s, Program: 0.000s, Verify: 0.000s, Restore: 0.059s)
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O.K.
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J-Link>q
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$
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```
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@ -2,16 +2,6 @@
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# F4 Make file include
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#
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ifeq ($(OPBL),yes)
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ifeq ($(TARGET), $(filter $(TARGET),$(F405_TARGETS)))
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LD_SCRIPT = $(LINKER_DIR)/stm32_flash_f405_opbl.ld
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else ifeq ($(TARGET), $(filter $(TARGET),$(F411_TARGETS)))
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LD_SCRIPT = $(LINKER_DIR)/stm32_flash_f411_opbl.ld
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else
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$(error No OPBL linker script specified for $(TARGET`))
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endif
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endif
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#CMSIS
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ifeq ($(PERIPH_DRIVER), HAL)
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CMSIS_DIR := $(ROOT)/lib/main/STM32F4/Drivers/CMSIS
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@ -9,10 +9,6 @@ BASE_TARGET := $(call get_base_target,$(TARGET))
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# silently ignore if the file is not present. Allows for target specific.
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-include $(ROOT)/src/main/target/$(BASE_TARGET)/$(TARGET).mk
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ifeq ($(filter $(TARGET),$(OPBL_TARGETS)), $(TARGET))
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OPBL = yes
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endif
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# silently ignore if the file is not present. Allows for target defaults.
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-include $(ROOT)/src/main/target/$(BASE_TARGET)/target.mk
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@ -6,7 +6,6 @@ BASE_ALT_PAIRS = $(join $(BASE_TARGET_NAMES:=/),$(ALT_TARGET_NAMES))
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ALT_TARGETS = $(sort $(notdir $(BASE_ALT_PAIRS)))
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BASE_TARGETS = $(sort $(notdir $(patsubst %/,%,$(dir $(wildcard $(ROOT)/src/main/target/*/target.mk)))))
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NOBUILD_TARGETS = $(sort $(filter-out target,$(basename $(notdir $(wildcard $(ROOT)/src/main/target/*/*.nomk)))))
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OPBL_TARGETS = $(sort $(filter %_OPBL,$(ALT_TARGETS)))
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VALID_TARGETS = $(sort $(filter-out $(NOBUILD_TARGETS),$(BASE_TARGETS) $(ALT_TARGETS)))
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# For alt targets, returns their base target name.
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@ -1,41 +0,0 @@
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/*
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*****************************************************************************
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**
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** File : stm32_flash_f405.ld
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**
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** Abstract : Linker script for STM32F405RG Device with
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** 1024KByte FLASH, 128KByte RAM 64KByte CCM (RAM)
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**
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*****************************************************************************
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*/
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/*
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0x08000000 to 0x080FFFFF 1024K full flash,
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0x08000000 to 0x08003FFF 16K OPBL,
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0x08004000 to 0x08007FFF 16K isr vector, startup code,
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0x08008000 to 0x0800BFFF 16K config, // FLASH_Sector_2
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0x0800C000 to 0x080FFFFF 976K firmware,
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*/
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/* Specify the memory areas */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08004000, LENGTH = 16K
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FLASH_CONFIG (r): ORIGIN = 0x08008000, LENGTH = 16K
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FLASH1 (rx) : ORIGIN = 0x0800C000, LENGTH = 976K
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SYSTEM_MEMORY (rx): ORIGIN = 0x1FFF0000, LENGTH = 29K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
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MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
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}
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REGION_ALIAS("STACKRAM", CCM)
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REGION_ALIAS("FASTRAM", CCM)
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/* Put various bits and bobs of data into the main chunk of flash as we have enough of it */
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REGION_ALIAS("MOVABLE_FLASH", FLASH1)
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INCLUDE "stm32_flash_f4_split.ld"
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@ -1,40 +0,0 @@
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/*
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*****************************************************************************
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**
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** File : stm32_flash_f411_opbl.ld
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**
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** Abstract : Linker script for STM32F411 Device with
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** 512KByte FLASH, 128KByte RAM
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**
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*****************************************************************************
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*/
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/*
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0x08000000 to 0x0807FFFF 512K full flash,
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0x08000000 to 0x08003FFF 16K OPBL,
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0x08004000 to 0x08007FFF 16K isr vector, startup code,
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0x08008000 to 0x0800BFFF 16K config, // FLASH_Sector_2
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0x0800C000 to 0x0807FFFF 464K firmware,
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*/
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/* Specify the memory areas */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08004000, LENGTH = 16K
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FLASH_CONFIG (r) : ORIGIN = 0x08008000, LENGTH = 16K
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FLASH1 (rx) : ORIGIN = 0x0800C000, LENGTH = 464K
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SYSTEM_MEMORY (rx): ORIGIN = 0x1FFF0000, LENGTH = 29K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
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}
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REGION_ALIAS("STACKRAM", RAM)
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REGION_ALIAS("FASTRAM", RAM)
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/* Put various bits and bobs of data into the free space after the vector table in sector 0 to save flash space. */
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REGION_ALIAS("MOVABLE_FLASH", FLASH)
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INCLUDE "stm32_flash_f4_split.ld"
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@ -46,10 +46,6 @@
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#define TARGET_BOARD_IDENTIFIER "REVO"
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#define USBD_PRODUCT_STRING "Revolution"
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#ifdef OPBL
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#define USBD_SERIALNUMBER_STRING "0x8020000"
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#endif
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#endif
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#define LED0_PIN PB5
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@ -25,9 +25,6 @@
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#define TARGET_BOARD_IDENTIFIER "REVN"
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#define USBD_PRODUCT_STRING "Revo Nano"
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#ifdef OPBL
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#define USBD_SERIALNUMBER_STRING "0x8010000"
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#endif
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#define LED0_PIN PC14
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#define LED1_PIN PC13
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@ -22,9 +22,6 @@
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#define TARGET_BOARD_IDENTIFIER "SPK2"
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#define USBD_PRODUCT_STRING "Sparky 2.0"
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#ifdef OPBL
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#define USBD_SERIALNUMBER_STRING "0x8020000"
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#endif
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#define LED0_PIN PB5
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#define LED1_PIN PB4
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