mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-26 01:35:41 +03:00
New SPI API supporting DMA
Call targetConfiguration() once before config is loaded and again afterwards in case the config needs to be changed to load from SD card etc Drop SPI clock during binding Remove debug Add per device SPI DMA enable Fix sdioPinConfigure() declaration warning Reduce clock speed during SPI RX initialisation
This commit is contained in:
Steve Evans
Michael Keller
parent
6d286e25f1
commit
87c8847c13
136 changed files with 3585 additions and 2721 deletions
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@ -24,18 +24,24 @@
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#include "platform.h"
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#include "build/atomic.h"
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#ifdef USE_SPI
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#include "drivers/bus.h"
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#include "drivers/bus_spi.h"
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#include "drivers/bus_spi_impl.h"
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#include "drivers/dma_reqmap.h"
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#include "drivers/exti.h"
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#include "drivers/io.h"
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#include "drivers/motor.h"
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#include "drivers/rcc.h"
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#include "nvic.h"
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static uint8_t spiRegisteredDeviceCount = 0;
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spiDevice_t spiDevice[SPIDEV_COUNT];
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busDevice_t spiBusDevice[SPIDEV_COUNT];
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SPIDevice spiDeviceByInstance(SPI_TypeDef *instance)
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{
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@ -71,7 +77,7 @@ SPI_TypeDef *spiInstanceByDevice(SPIDevice device)
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return spiDevice[device].dev;
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}
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bool spiInit(SPIDevice device, bool leadingEdge)
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bool spiInit(SPIDevice device)
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{
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switch (device) {
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case SPIINVALID:
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@ -79,7 +85,7 @@ bool spiInit(SPIDevice device, bool leadingEdge)
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case SPIDEV_1:
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#ifdef USE_SPI_DEVICE_1
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spiInitDevice(device, leadingEdge);
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spiInitDevice(device);
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return true;
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#else
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break;
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@ -87,7 +93,7 @@ bool spiInit(SPIDevice device, bool leadingEdge)
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case SPIDEV_2:
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#ifdef USE_SPI_DEVICE_2
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spiInitDevice(device, leadingEdge);
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spiInitDevice(device);
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return true;
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#else
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break;
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@ -95,7 +101,7 @@ bool spiInit(SPIDevice device, bool leadingEdge)
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case SPIDEV_3:
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#if defined(USE_SPI_DEVICE_3) && !defined(STM32F1)
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spiInitDevice(device, leadingEdge);
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spiInitDevice(device);
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return true;
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#else
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break;
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@ -103,7 +109,7 @@ bool spiInit(SPIDevice device, bool leadingEdge)
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case SPIDEV_4:
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#if defined(USE_SPI_DEVICE_4)
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spiInitDevice(device, leadingEdge);
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spiInitDevice(device);
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return true;
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#else
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break;
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@ -111,7 +117,7 @@ bool spiInit(SPIDevice device, bool leadingEdge)
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case SPIDEV_5:
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#if defined(USE_SPI_DEVICE_5)
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spiInitDevice(device, leadingEdge);
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spiInitDevice(device);
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return true;
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#else
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break;
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@ -119,7 +125,7 @@ bool spiInit(SPIDevice device, bool leadingEdge)
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case SPIDEV_6:
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#if defined(USE_SPI_DEVICE_6)
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spiInitDevice(device, leadingEdge);
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spiInitDevice(device);
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return true;
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#else
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break;
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@ -128,116 +134,248 @@ bool spiInit(SPIDevice device, bool leadingEdge)
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return false;
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}
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uint32_t spiTimeoutUserCallback(SPI_TypeDef *instance)
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// Return true if DMA engine is busy
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bool spiIsBusy(const extDevice_t *dev)
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{
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SPIDevice device = spiDeviceByInstance(instance);
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if (device == SPIINVALID) {
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return -1;
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}
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spiDevice[device].errorCount++;
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return spiDevice[device].errorCount;
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return (dev->bus->curSegment != (busSegment_t *)NULL);
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}
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bool spiBusTransfer(const busDevice_t *bus, const uint8_t *txData, uint8_t *rxData, int length)
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// Indicate that the bus on which this device resides may initiate DMA transfers from interrupt context
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void spiSetAtomicWait(const extDevice_t *dev)
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{
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IOLo(bus->busdev_u.spi.csnPin);
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spiTransfer(bus->busdev_u.spi.instance, txData, rxData, length);
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IOHi(bus->busdev_u.spi.csnPin);
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return true;
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dev->bus->useAtomicWait = true;
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}
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uint16_t spiGetErrorCounter(SPI_TypeDef *instance)
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// Wait for DMA completion and claim the bus driver
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void spiWaitClaim(const extDevice_t *dev)
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{
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SPIDevice device = spiDeviceByInstance(instance);
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if (device == SPIINVALID) {
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return 0;
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}
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return spiDevice[device].errorCount;
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}
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// If there is a device on the bus whose driver might call spiSequence from an ISR then an
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// atomic access is required to claim the bus, however if not, then interrupts need not be
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// disabled as this can result in edge triggered interrupts being missed
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void spiResetErrorCounter(SPI_TypeDef *instance)
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{
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SPIDevice device = spiDeviceByInstance(instance);
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if (device != SPIINVALID) {
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spiDevice[device].errorCount = 0;
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if (dev->bus->useAtomicWait) {
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// Prevent race condition where the bus appears free, but a gyro interrupt starts a transfer
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do {
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ATOMIC_BLOCK(NVIC_PRIO_MPU_INT_EXTI) {
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if (dev->bus->curSegment == (busSegment_t *)NULL) {
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dev->bus->curSegment = (busSegment_t *)0x04;
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}
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}
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} while (dev->bus->curSegment != (busSegment_t *)0x04);
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} else {
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// Wait for completion
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while (dev->bus->curSegment != (busSegment_t *)NULL);
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}
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}
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bool spiBusIsBusBusy(const busDevice_t *bus)
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// Wait for DMA completion
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void spiWait(const extDevice_t *dev)
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{
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return spiIsBusBusy(bus->busdev_u.spi.instance);
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// Wait for completion
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while (dev->bus->curSegment != (busSegment_t *)NULL);
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}
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uint8_t spiBusTransferByte(const busDevice_t *bus, uint8_t data)
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// Wait for bus to become free, then read/write block of data
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void spiReadWriteBuf(const extDevice_t *dev, uint8_t *txData, uint8_t *rxData, int len)
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{
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return spiTransferByte(bus->busdev_u.spi.instance, data);
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{txData, rxData, len, true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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}
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void spiBusWriteByte(const busDevice_t *bus, uint8_t data)
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// Read/Write a block of data, returning false if the bus is busy
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bool spiReadWriteBufRB(const extDevice_t *dev, uint8_t *txData, uint8_t *rxData, int length)
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{
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IOLo(bus->busdev_u.spi.csnPin);
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spiBusTransferByte(bus, data);
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IOHi(bus->busdev_u.spi.csnPin);
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}
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// Ensure any prior DMA has completed before continuing
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if (spiIsBusy(dev)) {
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return false;
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}
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bool spiBusRawTransfer(const busDevice_t *bus, const uint8_t *txData, uint8_t *rxData, int len)
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{
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return spiTransfer(bus->busdev_u.spi.instance, txData, rxData, len);
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}
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bool spiBusWriteRegister(const busDevice_t *bus, uint8_t reg, uint8_t data)
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{
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IOLo(bus->busdev_u.spi.csnPin);
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spiTransferByte(bus->busdev_u.spi.instance, reg);
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spiTransferByte(bus->busdev_u.spi.instance, data);
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IOHi(bus->busdev_u.spi.csnPin);
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spiReadWriteBuf(dev, txData, rxData, length);
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return true;
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}
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bool spiBusRawReadRegisterBuffer(const busDevice_t *bus, uint8_t reg, uint8_t *data, uint8_t length)
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// Wait for bus to become free, then read/write a single byte
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uint8_t spiReadWrite(const extDevice_t *dev, uint8_t data)
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{
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IOLo(bus->busdev_u.spi.csnPin);
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spiTransferByte(bus->busdev_u.spi.instance, reg);
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spiTransfer(bus->busdev_u.spi.instance, NULL, data, length);
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IOHi(bus->busdev_u.spi.csnPin);
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uint8_t retval;
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{&data, &retval, sizeof (data), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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return retval;
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}
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// Wait for bus to become free, then read/write a single byte from a register
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uint8_t spiReadWriteReg(const extDevice_t *dev, uint8_t reg, uint8_t data)
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{
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uint8_t retval;
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{®, NULL, sizeof (reg), false, NULL},
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{&data, &retval, sizeof (data), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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return retval;
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}
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// Wait for bus to become free, then write a single byte
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void spiWrite(const extDevice_t *dev, uint8_t data)
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{
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{&data, NULL, sizeof (data), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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}
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// Write data to a register
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void spiWriteReg(const extDevice_t *dev, uint8_t reg, uint8_t data)
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{
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{®, NULL, sizeof (reg), false, NULL},
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{&data, NULL, sizeof (data), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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}
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// Write data to a register, returning false if the bus is busy
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bool spiWriteRegRB(const extDevice_t *dev, uint8_t reg, uint8_t data)
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{
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// Ensure any prior DMA has completed before continuing
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if (spiIsBusy(dev)) {
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return false;
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}
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spiWriteReg(dev, reg, data);
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return true;
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}
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bool spiBusReadRegisterBuffer(const busDevice_t *bus, uint8_t reg, uint8_t *data, uint8_t length)
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// Read a block of data from a register
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void spiReadRegBuf(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint8_t length)
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{
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return spiBusRawReadRegisterBuffer(bus, reg | 0x80, data, length);
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{®, NULL, sizeof (reg), false, NULL},
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{NULL, data, length, true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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}
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void spiBusWriteRegisterBuffer(const busDevice_t *bus, uint8_t reg, const uint8_t *data, uint8_t length)
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// Read a block of data from a register, returning false if the bus is busy
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bool spiReadRegBufRB(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint8_t length)
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{
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IOLo(bus->busdev_u.spi.csnPin);
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spiTransferByte(bus->busdev_u.spi.instance, reg);
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spiTransfer(bus->busdev_u.spi.instance, data, NULL, length);
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IOHi(bus->busdev_u.spi.csnPin);
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// Ensure any prior DMA has completed before continuing
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if (spiIsBusy(dev)) {
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return false;
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}
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spiReadRegBuf(dev, reg, data, length);
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return true;
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}
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uint8_t spiBusRawReadRegister(const busDevice_t *bus, uint8_t reg)
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// Read a block of data where the register is ORed with 0x80, returning false if the bus is busy
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bool spiReadRegMskBufRB(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint8_t length)
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{
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return spiReadRegBufRB(dev, reg | 0x80, data, length);
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}
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// Wait for bus to become free, then write a block of data to a register
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void spiWriteRegBuf(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint32_t length)
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{
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{®, NULL, sizeof (reg), false, NULL},
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{data, NULL, length, true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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}
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// Wait for bus to become free, then read a byte from a register
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uint8_t spiReadReg(const extDevice_t *dev, uint8_t reg)
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{
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uint8_t data;
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IOLo(bus->busdev_u.spi.csnPin);
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spiTransferByte(bus->busdev_u.spi.instance, reg);
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spiTransfer(bus->busdev_u.spi.instance, NULL, &data, 1);
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IOHi(bus->busdev_u.spi.csnPin);
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// This routine blocks so no need to use static data
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busSegment_t segments[] = {
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{®, NULL, sizeof (reg), false, NULL},
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{NULL, &data, sizeof (data), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWaitClaim(dev);
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spiSequence(dev, &segments[0]);
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spiWait(dev);
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return data;
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}
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uint8_t spiBusReadRegister(const busDevice_t *bus, uint8_t reg)
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// Wait for bus to become free, then read a byte of data where the register is ORed with 0x80
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uint8_t spiReadRegMsk(const extDevice_t *dev, uint8_t reg)
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{
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return spiBusRawReadRegister(bus, reg | 0x80);
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}
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void spiBusSetInstance(busDevice_t *bus, SPI_TypeDef *instance)
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{
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bus->bustype = BUSTYPE_SPI;
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bus->busdev_u.spi.instance = instance;
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return spiReadReg(dev, reg | 0x80);
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}
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uint16_t spiCalculateDivider(uint32_t freq)
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@ -259,54 +397,225 @@ uint16_t spiCalculateDivider(uint32_t freq)
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return divisor;
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}
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void spiBusSetDivisor(busDevice_t *bus, uint16_t divisor)
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// Interrupt handler for SPI receive DMA completion
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static void spiRxIrqHandler(dmaChannelDescriptor_t* descriptor)
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{
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spiSetDivisor(bus->busdev_u.spi.instance, divisor);
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// bus->busdev_u.spi.modeCache = bus->busdev_u.spi.instance->CR1;
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const extDevice_t *dev = (const extDevice_t *)descriptor->userParam;
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if (!dev) {
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return;
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}
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busDevice_t *bus = dev->bus;
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if (bus->curSegment->negateCS) {
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// Negate Chip Select
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IOHi(dev->busType_u.spi.csnPin);
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}
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spiInternalStopDMA(dev);
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#ifdef __DCACHE_PRESENT
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#ifdef STM32H7
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if (bus->curSegment->rxData &&
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((bus->curSegment->rxData < &_dmaram_start__) || (bus->curSegment->rxData >= &_dmaram_end__))) {
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#else
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if (bus->curSegment->rxData) {
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#endif
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// Invalidate the D cache covering the area into which data has been read
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SCB_InvalidateDCache_by_Addr(
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(uint32_t *)((uint32_t)bus->curSegment->rxData & ~CACHE_LINE_MASK),
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(((uint32_t)bus->curSegment->rxData & CACHE_LINE_MASK) +
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bus->curSegment->len - 1 + CACHE_LINE_SIZE) & ~CACHE_LINE_MASK);
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}
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#endif // __DCACHE_PRESENT
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if (bus->curSegment->callback) {
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switch(bus->curSegment->callback(dev->callbackArg)) {
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case BUS_BUSY:
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// Repeat the last DMA segment
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bus->curSegment--;
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// Reinitialise the cached init values as segment is not progressing
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spiInternalInitStream(dev, true);
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break;
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case BUS_ABORT:
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bus->curSegment = (busSegment_t *)NULL;
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return;
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||||
|
||||
case BUS_READY:
|
||||
default:
|
||||
// Advance to the next DMA segment
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Advance through the segment list
|
||||
bus->curSegment++;
|
||||
|
||||
if (bus->curSegment->len == 0) {
|
||||
// The end of the segment list has been reached, so mark transactions as complete
|
||||
bus->curSegment = (busSegment_t *)NULL;
|
||||
} else {
|
||||
// After the completion of the first segment setup the init structure for the subsequent segment
|
||||
if (bus->initSegment) {
|
||||
spiInternalInitStream(dev, false);
|
||||
bus->initSegment = false;
|
||||
}
|
||||
|
||||
// Launch the next transfer
|
||||
spiInternalStartDMA(dev);
|
||||
|
||||
// Prepare the init structures ready for the next segment to reduce inter-segment time
|
||||
spiInternalInitStream(dev, true);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef USE_SPI_TRANSACTION
|
||||
// Separate set of spiBusTransactionXXX to keep fast path for acc/gyros.
|
||||
|
||||
void spiBusTransactionBegin(const busDevice_t *bus)
|
||||
// Mark this bus as being SPI and record the first owner to use it
|
||||
bool spiSetBusInstance(extDevice_t *dev, uint32_t device, resourceOwner_e owner)
|
||||
{
|
||||
spiBusTransactionSetup(bus);
|
||||
IOLo(bus->busdev_u.spi.csnPin);
|
||||
if (device > SPIDEV_COUNT) {
|
||||
return false;
|
||||
}
|
||||
|
||||
dev->bus = &spiBusDevice[SPI_CFG_TO_DEV(device)];
|
||||
|
||||
if (dev->bus->busType == BUS_TYPE_SPI) {
|
||||
// This bus has already been initialised
|
||||
dev->bus->deviceCount++;
|
||||
return true;
|
||||
}
|
||||
|
||||
busDevice_t *bus = dev->bus;
|
||||
|
||||
bus->busType_u.spi.instance = spiInstanceByDevice(SPI_CFG_TO_DEV(device));
|
||||
|
||||
if (bus->busType_u.spi.instance == NULL) {
|
||||
return false;
|
||||
}
|
||||
|
||||
bus->busType = BUS_TYPE_SPI;
|
||||
dev->useDMA = true;
|
||||
bus->useDMA = false;
|
||||
bus->useAtomicWait = false;
|
||||
bus->deviceCount = 1;
|
||||
bus->owner = owner;
|
||||
bus->initTx = &dev->initTx;
|
||||
bus->initRx = &dev->initRx;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void spiBusTransactionEnd(const busDevice_t *bus)
|
||||
void spiInitBusDMA()
|
||||
{
|
||||
IOHi(bus->busdev_u.spi.csnPin);
|
||||
uint32_t device;
|
||||
#ifdef STM32F4
|
||||
/* Check https://www.st.com/resource/en/errata_sheet/dm00037591-stm32f405407xx-and-stm32f415417xx-device-limitations-stmicroelectronics.pdf
|
||||
* section 2.1.10 which reports an errata that corruption may occurs on DMA2 if AHB peripherals (eg GPIO ports) are
|
||||
* access concurrently with APB peripherals (eg SPI busses). Bitbang DSHOT uses DMA2 to write to GPIO ports. If this
|
||||
* is enabled, then don't enable DMA on an SPI bus using DMA2
|
||||
*/
|
||||
const bool dshotBitbangActive = isDshotBitbangActive(&motorConfig()->dev);
|
||||
#endif
|
||||
|
||||
for (device = 0; device < SPIDEV_COUNT; device++) {
|
||||
busDevice_t *bus = &spiBusDevice[device];
|
||||
|
||||
if (bus->busType != BUS_TYPE_SPI) {
|
||||
// This bus is not in use
|
||||
continue;
|
||||
}
|
||||
|
||||
dmaIdentifier_e dmaTxIdentifier = DMA_NONE;
|
||||
dmaIdentifier_e dmaRxIdentifier = DMA_NONE;
|
||||
|
||||
for (uint8_t opt = 0; opt < MAX_PERIPHERAL_DMA_OPTIONS; opt++) {
|
||||
const dmaChannelSpec_t *dmaTxChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_SPI_TX, device, opt);
|
||||
|
||||
if (dmaTxChannelSpec) {
|
||||
dmaTxIdentifier = dmaGetIdentifier(dmaTxChannelSpec->ref);
|
||||
if (dmaGetOwner(dmaTxIdentifier)->owner != OWNER_FREE) {
|
||||
dmaTxIdentifier = DMA_NONE;
|
||||
continue;
|
||||
}
|
||||
#ifdef STM32F4
|
||||
if (dshotBitbangActive && (DMA_DEVICE_NO(dmaTxIdentifier) == 2)) {
|
||||
dmaTxIdentifier = DMA_NONE;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
bus->dmaTxChannel = dmaTxChannelSpec->channel;
|
||||
dmaInit(dmaTxIdentifier, bus->owner, 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (uint8_t opt = 0; opt < MAX_PERIPHERAL_DMA_OPTIONS; opt++) {
|
||||
const dmaChannelSpec_t *dmaRxChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_SPI_RX, device, opt);
|
||||
|
||||
if (dmaRxChannelSpec) {
|
||||
dmaRxIdentifier = dmaGetIdentifier(dmaRxChannelSpec->ref);
|
||||
if (dmaGetOwner(dmaRxIdentifier)->owner != OWNER_FREE) {
|
||||
dmaRxIdentifier = DMA_NONE;
|
||||
continue;
|
||||
}
|
||||
#ifdef STM32F4
|
||||
if (dshotBitbangActive && (DMA_DEVICE_NO(dmaRxIdentifier) == 2)) {
|
||||
dmaRxIdentifier = DMA_NONE;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
bus->dmaRxChannel = dmaRxChannelSpec->channel;
|
||||
dmaInit(dmaRxIdentifier, bus->owner, 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (dmaTxIdentifier && dmaRxIdentifier) {
|
||||
bus->dmaTx = dmaGetDescriptorByIdentifier(dmaTxIdentifier);
|
||||
bus->dmaRx = dmaGetDescriptorByIdentifier(dmaRxIdentifier);
|
||||
|
||||
// Ensure streams are disabled
|
||||
spiInternalResetStream(bus->dmaRx);
|
||||
spiInternalResetStream(bus->dmaTx);
|
||||
|
||||
spiInternalResetDescriptors(bus);
|
||||
|
||||
/* Note that this driver may be called both from the normal thread of execution, or from USB interrupt
|
||||
* handlers, so the DMA completion interrupt must be at a higher priority
|
||||
*/
|
||||
dmaSetHandler(dmaRxIdentifier, spiRxIrqHandler, NVIC_PRIO_SPI_DMA, 0);
|
||||
|
||||
bus->useDMA = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool spiBusTransactionTransfer(const busDevice_t *bus, const uint8_t *txData, uint8_t *rxData, int length)
|
||||
void spiSetClkDivisor(const extDevice_t *dev, uint16_t divisor)
|
||||
{
|
||||
spiBusTransactionSetup(bus);
|
||||
return spiBusTransfer(bus, txData, rxData, length);
|
||||
((extDevice_t *)dev)->busType_u.spi.speed = divisor;
|
||||
}
|
||||
|
||||
bool spiBusTransactionWriteRegister(const busDevice_t *bus, uint8_t reg, uint8_t data)
|
||||
// Set the clock phase/polarity to be used for accesses by the given device
|
||||
void spiSetClkPhasePolarity(const extDevice_t *dev, bool leadingEdge)
|
||||
{
|
||||
spiBusTransactionSetup(bus);
|
||||
return spiBusWriteRegister(bus, reg, data);
|
||||
((extDevice_t *)dev)->busType_u.spi.leadingEdge = leadingEdge;
|
||||
}
|
||||
|
||||
uint8_t spiBusTransactionReadRegister(const busDevice_t *bus, uint8_t reg)
|
||||
// Enable/disable DMA on a specific device. Enabled by default.
|
||||
void spiDmaEnable(const extDevice_t *dev, bool enable)
|
||||
{
|
||||
spiBusTransactionSetup(bus);
|
||||
return spiBusReadRegister(bus, reg);
|
||||
((extDevice_t *)dev)->useDMA = enable;
|
||||
}
|
||||
|
||||
bool spiBusTransactionReadRegisterBuffer(const busDevice_t *bus, uint8_t reg, uint8_t *data, uint8_t length)
|
||||
bool spiUseDMA(const extDevice_t *dev)
|
||||
{
|
||||
spiBusTransactionSetup(bus);
|
||||
return spiBusReadRegisterBuffer(bus, reg, data, length);
|
||||
return dev->bus->useDMA && dev->useDMA;
|
||||
}
|
||||
#endif // USE_SPI_TRANSACTION
|
||||
|
||||
void spiBusDeviceRegister(const busDevice_t *bus)
|
||||
void spiBusDeviceRegister(const extDevice_t *dev)
|
||||
{
|
||||
UNUSED(bus);
|
||||
UNUSED(dev);
|
||||
|
||||
spiRegisteredDeviceCount++;
|
||||
}
|
||||
|
|
@ -315,4 +624,9 @@ uint8_t spiGetRegisteredDeviceCount(void)
|
|||
{
|
||||
return spiRegisteredDeviceCount;
|
||||
}
|
||||
|
||||
uint8_t spiGetExtDeviceCount(const extDevice_t *dev)
|
||||
{
|
||||
return dev->bus->deviceCount;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue