mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-23 08:15:30 +03:00
New SPI API supporting DMA
Call targetConfiguration() once before config is loaded and again afterwards in case the config needs to be changed to load from SD card etc Drop SPI clock during binding Remove debug Add per device SPI DMA enable Fix sdioPinConfigure() declaration warning Reduce clock speed during SPI RX initialisation
This commit is contained in:
Steve Evans
Michael Keller
parent
6d286e25f1
commit
87c8847c13
136 changed files with 3585 additions and 2721 deletions
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@ -26,6 +26,9 @@
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#ifdef USE_SPI
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// STM32F405 can't DMA to/from FASTRAM (CCM SRAM)
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#define IS_CCM(p) (((uint32_t)p & 0xffff0000) == 0x10000000)
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#include "common/maths.h"
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#include "drivers/bus.h"
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#include "drivers/bus_spi.h"
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@ -33,7 +36,6 @@
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#include "drivers/exti.h"
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#include "drivers/io.h"
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#include "drivers/rcc.h"
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#include "drivers/time.h"
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static SPI_InitTypeDef defaultInit = {
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.SPI_Mode = SPI_Mode_Master,
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@ -43,160 +45,19 @@ static SPI_InitTypeDef defaultInit = {
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.SPI_FirstBit = SPI_FirstBit_MSB,
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.SPI_CRCPolynomial = 7,
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.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8,
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.SPI_CPOL = SPI_CPOL_High,
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.SPI_CPHA = SPI_CPHA_2Edge
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};
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void spiInitDevice(SPIDevice device, bool leadingEdge)
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{
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spiDevice_t *spi = &(spiDevice[device]);
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if (!spi->dev) {
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return;
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}
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#ifndef USE_SPI_TRANSACTION
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spi->leadingEdge = leadingEdge;
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#else
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UNUSED(leadingEdge);
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#endif
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// Enable SPI clock
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RCC_ClockCmd(spi->rcc, ENABLE);
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RCC_ResetCmd(spi->rcc, ENABLE);
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IOInit(IOGetByTag(spi->sck), OWNER_SPI_SCK, RESOURCE_INDEX(device));
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IOInit(IOGetByTag(spi->miso), OWNER_SPI_MISO, RESOURCE_INDEX(device));
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IOInit(IOGetByTag(spi->mosi), OWNER_SPI_MOSI, RESOURCE_INDEX(device));
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#if defined(STM32F3) || defined(STM32F4)
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IOConfigGPIOAF(IOGetByTag(spi->sck), SPI_IO_AF_CFG, spi->af);
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IOConfigGPIOAF(IOGetByTag(spi->miso), SPI_IO_AF_CFG, spi->af);
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IOConfigGPIOAF(IOGetByTag(spi->mosi), SPI_IO_AF_CFG, spi->af);
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#elif defined(STM32F10X)
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IOConfigGPIO(IOGetByTag(spi->sck), SPI_IO_AF_SCK_CFG);
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IOConfigGPIO(IOGetByTag(spi->miso), SPI_IO_AF_MISO_CFG);
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IOConfigGPIO(IOGetByTag(spi->mosi), SPI_IO_AF_MOSI_CFG);
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#else
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#error Undefined MCU architecture
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#endif
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// Init SPI hardware
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SPI_I2S_DeInit(spi->dev);
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#ifndef USE_SPI_TRANSACTION
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if (spi->leadingEdge) {
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defaultInit.SPI_CPOL = SPI_CPOL_Low;
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defaultInit.SPI_CPHA = SPI_CPHA_1Edge;
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} else
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#endif
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{
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defaultInit.SPI_CPOL = SPI_CPOL_High;
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defaultInit.SPI_CPHA = SPI_CPHA_2Edge;
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}
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#ifdef STM32F303xC
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// Configure for 8-bit reads.
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SPI_RxFIFOThresholdConfig(spi->dev, SPI_RxFIFOThreshold_QF);
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#endif
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SPI_Init(spi->dev, &defaultInit);
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SPI_Cmd(spi->dev, ENABLE);
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}
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// return uint8_t value or -1 when failure
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uint8_t spiTransferByte(SPI_TypeDef *instance, uint8_t txByte)
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{
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timeUs_t timeoutStartUs = microsISR();
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DISCARD(instance->DR);
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while (SPI_I2S_GetFlagStatus(instance, SPI_I2S_FLAG_TXE) == RESET) {
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if (cmpTimeUs(microsISR(), timeoutStartUs) >= SPI_TIMEOUT_US) {
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return spiTimeoutUserCallback(instance);
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}
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}
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#ifdef STM32F303xC
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SPI_SendData8(instance, txByte);
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#else
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SPI_I2S_SendData(instance, txByte);
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#endif
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timeoutStartUs = microsISR();
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while (SPI_I2S_GetFlagStatus(instance, SPI_I2S_FLAG_RXNE) == RESET) {
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if (cmpTimeUs(microsISR(), timeoutStartUs) >= SPI_TIMEOUT_US) {
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return spiTimeoutUserCallback(instance);
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}
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}
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#ifdef STM32F303xC
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return ((uint8_t)SPI_ReceiveData8(instance));
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#else
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return ((uint8_t)SPI_I2S_ReceiveData(instance));
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#endif
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}
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/**
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* Return true if the bus is currently in the middle of a transmission.
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*/
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bool spiIsBusBusy(SPI_TypeDef *instance)
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{
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#ifdef STM32F303xC
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return SPI_GetTransmissionFIFOStatus(instance) != SPI_TransmissionFIFOStatus_Empty || SPI_I2S_GetFlagStatus(instance, SPI_I2S_FLAG_BSY) == SET;
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#else
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return SPI_I2S_GetFlagStatus(instance, SPI_I2S_FLAG_TXE) == RESET || SPI_I2S_GetFlagStatus(instance, SPI_I2S_FLAG_BSY) == SET;
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#endif
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}
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bool spiTransfer(SPI_TypeDef *instance, const uint8_t *txData, uint8_t *rxData, int len)
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{
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timeUs_t timeoutStartUs;
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uint8_t b;
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DISCARD(instance->DR);
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while (len--) {
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b = txData ? *(txData++) : 0xFF;
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timeoutStartUs = microsISR();
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while (SPI_I2S_GetFlagStatus(instance, SPI_I2S_FLAG_TXE) == RESET) {
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if (cmpTimeUs(microsISR(), timeoutStartUs) >= SPI_TIMEOUT_US) {
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return spiTimeoutUserCallback(instance);
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}
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}
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#ifdef STM32F303xC
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SPI_SendData8(instance, b);
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#else
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SPI_I2S_SendData(instance, b);
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#endif
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timeoutStartUs = microsISR();
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while (SPI_I2S_GetFlagStatus(instance, SPI_I2S_FLAG_RXNE) == RESET) {
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if (cmpTimeUs(microsISR(), timeoutStartUs) >= SPI_TIMEOUT_US) {
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return spiTimeoutUserCallback(instance);
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}
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}
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#ifdef STM32F303xC
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b = SPI_ReceiveData8(instance);
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#else
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b = SPI_I2S_ReceiveData(instance);
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#endif
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if (rxData) {
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*(rxData++) = b;
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}
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}
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return true;
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}
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static uint16_t spiDivisorToBRbits(SPI_TypeDef *instance, uint16_t divisor)
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{
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#if !(defined(STM32F1) || defined(STM32F3))
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// SPI2 and SPI3 are on APB1/AHB1 which PCLK is half that of APB2/AHB2.
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#if defined(STM32F410xx) || defined(STM32F411xE)
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UNUSED(instance);
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#else
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if (instance == SPI2 || instance == SPI3) {
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divisor /= 2; // Safe for divisor == 0 or 1
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}
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#else
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UNUSED(instance);
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#endif
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divisor = constrain(divisor, 2, 256);
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@ -212,61 +73,294 @@ static void spiSetDivisorBRreg(SPI_TypeDef *instance, uint16_t divisor)
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#undef BR_BITS
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}
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void spiSetDivisor(SPI_TypeDef *instance, uint16_t divisor)
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void spiInitDevice(SPIDevice device)
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{
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spiDevice_t *spi = &(spiDevice[device]);
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if (!spi->dev) {
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return;
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}
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// Enable SPI clock
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RCC_ClockCmd(spi->rcc, ENABLE);
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RCC_ResetCmd(spi->rcc, ENABLE);
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IOInit(IOGetByTag(spi->sck), OWNER_SPI_SCK, RESOURCE_INDEX(device));
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IOInit(IOGetByTag(spi->miso), OWNER_SPI_MISO, RESOURCE_INDEX(device));
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IOInit(IOGetByTag(spi->mosi), OWNER_SPI_MOSI, RESOURCE_INDEX(device));
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IOConfigGPIOAF(IOGetByTag(spi->sck), SPI_IO_AF_SCK_CFG, spi->af);
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IOConfigGPIOAF(IOGetByTag(spi->miso), SPI_IO_AF_MISO_CFG, spi->af);
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IOConfigGPIOAF(IOGetByTag(spi->mosi), SPI_IO_AF_CFG, spi->af);
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// Init SPI hardware
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SPI_I2S_DeInit(spi->dev);
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SPI_I2S_DMACmd(spi->dev, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, DISABLE);
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SPI_Init(spi->dev, &defaultInit);
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SPI_Cmd(spi->dev, ENABLE);
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}
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void spiInternalResetDescriptors(busDevice_t *bus)
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{
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DMA_InitTypeDef *initTx = bus->initTx;
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DMA_InitTypeDef *initRx = bus->initRx;
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DMA_StructInit(initTx);
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initTx->DMA_Channel = bus->dmaTxChannel;
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initTx->DMA_DIR = DMA_DIR_MemoryToPeripheral;
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initTx->DMA_Mode = DMA_Mode_Normal;
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initTx->DMA_PeripheralBaseAddr = (uint32_t)&bus->busType_u.spi.instance->DR;
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initTx->DMA_Priority = DMA_Priority_Low;
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initTx->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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initTx->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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initTx->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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DMA_StructInit(initRx);
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initRx->DMA_Channel = bus->dmaRxChannel;
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initRx->DMA_DIR = DMA_DIR_PeripheralToMemory;
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initRx->DMA_Mode = DMA_Mode_Normal;
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initRx->DMA_PeripheralBaseAddr = (uint32_t)&bus->busType_u.spi.instance->DR;
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initRx->DMA_Priority = DMA_Priority_Low;
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initRx->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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initRx->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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}
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void spiInternalResetStream(dmaChannelDescriptor_t *descriptor)
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{
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DMA_Stream_TypeDef *streamRegs = (DMA_Stream_TypeDef *)descriptor->ref;
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// Disable the stream
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streamRegs->CR = 0U;
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// Clear any pending interrupt flags
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DMA_CLEAR_FLAG(descriptor, DMA_IT_HTIF | DMA_IT_TEIF | DMA_IT_TCIF);
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}
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static bool spiInternalReadWriteBufPolled(SPI_TypeDef *instance, const uint8_t *txData, uint8_t *rxData, int len)
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{
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uint8_t b;
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while (len--) {
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b = txData ? *(txData++) : 0xFF;
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while (SPI_I2S_GetFlagStatus(instance, SPI_I2S_FLAG_TXE) == RESET);
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SPI_I2S_SendData(instance, b);
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while (SPI_I2S_GetFlagStatus(instance, SPI_I2S_FLAG_RXNE) == RESET);
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b = SPI_I2S_ReceiveData(instance);
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if (rxData) {
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*(rxData++) = b;
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}
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}
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return true;
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}
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void spiInternalInitStream(const extDevice_t *dev, bool preInit)
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{
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static uint8_t dummyTxByte = 0xff;
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static uint8_t dummyRxByte;
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busDevice_t *bus = dev->bus;
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volatile busSegment_t *segment = bus->curSegment;
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if (preInit) {
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// Prepare the init structure for the next segment to reduce inter-segment interval
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segment++;
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if(segment->len == 0) {
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// There's no following segment
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return;
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}
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}
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uint8_t *txData = segment->txData;
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uint8_t *rxData = segment->rxData;
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int len = segment->len;
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DMA_InitTypeDef *initTx = bus->initTx;
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DMA_InitTypeDef *initRx = bus->initRx;
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if (txData) {
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initTx->DMA_Memory0BaseAddr = (uint32_t)txData;
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initTx->DMA_MemoryInc = DMA_MemoryInc_Enable;
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} else {
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dummyTxByte = 0xff;
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initTx->DMA_Memory0BaseAddr = (uint32_t)&dummyTxByte;
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initTx->DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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initTx->DMA_BufferSize = len;
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if (rxData) {
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initRx->DMA_Memory0BaseAddr = (uint32_t)rxData;
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initRx->DMA_MemoryInc = DMA_MemoryInc_Enable;
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} else {
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initRx->DMA_Memory0BaseAddr = (uint32_t)&dummyRxByte;
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initRx->DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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// If possible use 16 bit memory writes to prevent atomic access issues on gyro data
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if ((initRx->DMA_Memory0BaseAddr & 0x1) || (len & 0x1))
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{
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initRx->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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} else {
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initRx->DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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}
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initRx->DMA_BufferSize = len;
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}
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void spiInternalStartDMA(const extDevice_t *dev)
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{
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// Assert Chip Select
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IOLo(dev->busType_u.spi.csnPin);
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dmaChannelDescriptor_t *dmaTx = dev->bus->dmaTx;
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dmaChannelDescriptor_t *dmaRx = dev->bus->dmaRx;
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DMA_Stream_TypeDef *streamRegsTx = (DMA_Stream_TypeDef *)dmaTx->ref;
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DMA_Stream_TypeDef *streamRegsRx = (DMA_Stream_TypeDef *)dmaRx->ref;
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// Use the correct callback argument
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dmaRx->userParam = (uint32_t)dev;
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// Clear transfer flags
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DMA_CLEAR_FLAG(dmaTx, DMA_IT_HTIF | DMA_IT_TEIF | DMA_IT_TCIF);
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DMA_CLEAR_FLAG(dmaRx, DMA_IT_HTIF | DMA_IT_TEIF | DMA_IT_TCIF);
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// Disable streams to enable update
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streamRegsTx->CR = 0U;
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streamRegsRx->CR = 0U;
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/* Use the Rx interrupt as this occurs once the SPI operation is complete whereas the Tx interrupt
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* occurs earlier when the Tx FIFO is empty, but the SPI operation is still in progress
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*/
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DMA_ITConfig(streamRegsRx, DMA_IT_TC, ENABLE);
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// Update streams
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DMA_Init(streamRegsTx, dev->bus->initTx);
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DMA_Init(streamRegsRx, dev->bus->initRx);
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/* Note from AN4031
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*
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* If the user enables the used peripheral before the corresponding DMA stream, a “FEIF”
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* (FIFO Error Interrupt Flag) may be set due to the fact the DMA is not ready to provide
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* the first required data to the peripheral (in case of memory-to-peripheral transfer).
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*/
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// Enable streams
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DMA_Cmd(streamRegsTx, ENABLE);
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DMA_Cmd(streamRegsRx, ENABLE);
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/* Enable the SPI DMA Tx & Rx requests */
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SPI_I2S_DMACmd(dev->bus->busType_u.spi.instance, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
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}
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void spiInternalStopDMA (const extDevice_t *dev)
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{
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dmaChannelDescriptor_t *dmaTx = dev->bus->dmaTx;
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dmaChannelDescriptor_t *dmaRx = dev->bus->dmaRx;
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DMA_Stream_TypeDef *streamRegsTx = (DMA_Stream_TypeDef *)dmaTx->ref;
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DMA_Stream_TypeDef *streamRegsRx = (DMA_Stream_TypeDef *)dmaRx->ref;
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SPI_TypeDef *instance = dev->bus->busType_u.spi.instance;
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// Disable streams
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streamRegsTx->CR = 0U;
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streamRegsRx->CR = 0U;
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SPI_I2S_DMACmd(instance, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, DISABLE);
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}
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// DMA transfer setup and start
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void spiSequence(const extDevice_t *dev, busSegment_t *segments)
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{
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busDevice_t *bus = dev->bus;
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SPI_TypeDef *instance = bus->busType_u.spi.instance;
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bool dmaSafe = dev->useDMA;
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uint32_t xferLen = 0;
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uint32_t segmentCount = 0;
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dev->bus->initSegment = true;
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dev->bus->curSegment = segments;
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SPI_Cmd(instance, DISABLE);
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spiSetDivisorBRreg(instance, divisor);
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// Switch bus speed
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if (dev->busType_u.spi.speed != bus->busType_u.spi.speed) {
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spiSetDivisorBRreg(bus->busType_u.spi.instance, dev->busType_u.spi.speed);
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bus->busType_u.spi.speed = dev->busType_u.spi.speed;
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}
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if (dev->busType_u.spi.leadingEdge != bus->busType_u.spi.leadingEdge) {
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// Switch SPI clock polarity/phase
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instance->CR1 &= ~(SPI_CPOL_High | SPI_CPHA_2Edge);
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// Apply setting
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if (dev->busType_u.spi.leadingEdge) {
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instance->CR1 |= SPI_CPOL_Low | SPI_CPHA_1Edge;
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} else
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{
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instance->CR1 |= SPI_CPOL_High | SPI_CPHA_2Edge;
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}
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bus->busType_u.spi.leadingEdge = dev->busType_u.spi.leadingEdge;
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}
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SPI_Cmd(instance, ENABLE);
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}
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#ifdef USE_SPI_TRANSACTION
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void spiBusTransactionInit(busDevice_t *bus, SPIMode_e mode, uint16_t divider)
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{
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switch (mode) {
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case SPI_MODE0_POL_LOW_EDGE_1ST:
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defaultInit.SPI_CPOL = SPI_CPOL_Low;
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defaultInit.SPI_CPHA = SPI_CPHA_1Edge;
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break;
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case SPI_MODE1_POL_LOW_EDGE_2ND:
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defaultInit.SPI_CPOL = SPI_CPOL_Low;
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defaultInit.SPI_CPHA = SPI_CPHA_2Edge;
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break;
|
||||
case SPI_MODE2_POL_HIGH_EDGE_1ST:
|
||||
defaultInit.SPI_CPOL = SPI_CPOL_High;
|
||||
defaultInit.SPI_CPHA = SPI_CPHA_1Edge;
|
||||
break;
|
||||
case SPI_MODE3_POL_HIGH_EDGE_2ND:
|
||||
defaultInit.SPI_CPOL = SPI_CPOL_High;
|
||||
defaultInit.SPI_CPHA = SPI_CPHA_2Edge;
|
||||
break;
|
||||
// Check that any there are no attempts to DMA to/from CCD SRAM
|
||||
for (busSegment_t *checkSegment = bus->curSegment; checkSegment->len; checkSegment++) {
|
||||
if (((checkSegment->rxData) && IS_CCM(checkSegment->rxData)) ||
|
||||
((checkSegment->txData) && IS_CCM(checkSegment->txData))) {
|
||||
dmaSafe = false;
|
||||
break;
|
||||
}
|
||||
// Note that these counts are only valid if dmaSafe is true
|
||||
segmentCount++;
|
||||
xferLen += checkSegment->len;
|
||||
}
|
||||
// Use DMA if possible
|
||||
if (bus->useDMA && dmaSafe && ((segmentCount > 1) || (xferLen > 8))) {
|
||||
// Intialise the init structures for the first transfer
|
||||
spiInternalInitStream(dev, false);
|
||||
|
||||
// Initialize the SPI instance to setup CR1
|
||||
// Start the transfers
|
||||
spiInternalStartDMA(dev);
|
||||
} else {
|
||||
// Manually work through the segment list performing a transfer for each
|
||||
while (bus->curSegment->len) {
|
||||
// Assert Chip Select
|
||||
IOLo(dev->busType_u.spi.csnPin);
|
||||
|
||||
SPI_Init(bus->busdev_u.spi.instance, &defaultInit);
|
||||
spiSetDivisorBRreg(bus->busdev_u.spi.instance, divider);
|
||||
#ifdef STM32F303xC
|
||||
// Configure for 8-bit reads.
|
||||
SPI_RxFIFOThresholdConfig(bus->busdev_u.spi.instance, SPI_RxFIFOThreshold_QF);
|
||||
#endif
|
||||
spiInternalReadWriteBufPolled(
|
||||
bus->busType_u.spi.instance,
|
||||
bus->curSegment->txData,
|
||||
bus->curSegment->rxData,
|
||||
bus->curSegment->len);
|
||||
|
||||
bus->busdev_u.spi.modeCache = bus->busdev_u.spi.instance->CR1;
|
||||
bus->busdev_u.spi.device = &spiDevice[spiDeviceByInstance(bus->busdev_u.spi.instance)];
|
||||
}
|
||||
if (bus->curSegment->negateCS) {
|
||||
// Negate Chip Select
|
||||
IOHi(dev->busType_u.spi.csnPin);
|
||||
}
|
||||
|
||||
void spiBusTransactionSetup(const busDevice_t *bus)
|
||||
{
|
||||
// We rely on MSTR bit to detect valid modeCache
|
||||
if (bus->curSegment->callback) {
|
||||
switch(bus->curSegment->callback(dev->callbackArg)) {
|
||||
case BUS_BUSY:
|
||||
// Repeat the last DMA segment
|
||||
bus->curSegment--;
|
||||
break;
|
||||
|
||||
if (bus->busdev_u.spi.modeCache && bus->busdev_u.spi.modeCache != bus->busdev_u.spi.device->cr1SoftCopy) {
|
||||
bus->busdev_u.spi.instance->CR1 = bus->busdev_u.spi.modeCache;
|
||||
bus->busdev_u.spi.device->cr1SoftCopy = bus->busdev_u.spi.modeCache;
|
||||
case BUS_ABORT:
|
||||
bus->curSegment = (busSegment_t *)NULL;
|
||||
return;
|
||||
|
||||
// SCK seems to require some time to switch to a new initial level after CR1 is written.
|
||||
// Here we buy some time in addition to the software copy save above.
|
||||
__asm__("nop");
|
||||
case BUS_READY:
|
||||
default:
|
||||
// Advance to the next DMA segment
|
||||
break;
|
||||
}
|
||||
}
|
||||
bus->curSegment++;
|
||||
}
|
||||
|
||||
bus->curSegment = (busSegment_t *)NULL;
|
||||
}
|
||||
}
|
||||
#endif // USE_SPI_TRANSACTION
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue