mirror of
https://github.com/betaflight/betaflight.git
synced 2025-07-26 01:35:41 +03:00
New SPI API supporting DMA
Call targetConfiguration() once before config is loaded and again afterwards in case the config needs to be changed to load from SD card etc Drop SPI clock during binding Remove debug Add per device SPI DMA enable Fix sdioPinConfigure() declaration warning Reduce clock speed during SPI RX initialisation
This commit is contained in:
Steve Evans
Michael Keller
parent
6d286e25f1
commit
87c8847c13
136 changed files with 3585 additions and 2721 deletions
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@ -133,11 +133,6 @@ typedef struct bblut_s {
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uint16_t lba;
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} bblut_t;
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// These will be gone
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#define DISABLE(busdev) IOHi((busdev)->busdev_u.spi.csnPin); __NOP()
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#define ENABLE(busdev) __NOP(); IOLo((busdev)->busdev_u.spi.csnPin)
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static bool w25n01g_waitForReady(flashDevice_t *fdevice);
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static void w25n01g_setTimeout(flashDevice_t *fdevice, uint32_t timeoutMillis)
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@ -152,12 +147,20 @@ static void w25n01g_setTimeout(flashDevice_t *fdevice, uint32_t timeoutMillis)
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static void w25n01g_performOneByteCommand(flashDeviceIO_t *io, uint8_t command)
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{
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if (io->mode == FLASHIO_SPI) {
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busDevice_t *busdev = io->handle.busdev;
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extDevice_t *dev = io->handle.dev;
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ENABLE(busdev);
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spiTransferByte(busdev->busdev_u.spi.instance, command);
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DISABLE(busdev);
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busSegment_t segments[] = {
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{&command, NULL, sizeof (command), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWait(dev);
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spiSequence(dev, &segments[0]);
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// Block pending completion of SPI access
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spiWait(dev);
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}
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#ifdef USE_QUADSPI
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else if (io->mode == FLASHIO_QUADSPI) {
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@ -170,13 +173,22 @@ static void w25n01g_performOneByteCommand(flashDeviceIO_t *io, uint8_t command)
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static void w25n01g_performCommandWithPageAddress(flashDeviceIO_t *io, uint8_t command, uint32_t pageAddress)
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{
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if (io->mode == FLASHIO_SPI) {
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busDevice_t *busdev = io->handle.busdev;
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extDevice_t *dev = io->handle.dev;
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const uint8_t cmd[] = { command, 0, (pageAddress >> 8) & 0xff, (pageAddress >> 0) & 0xff};
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uint8_t cmd[] = { command, 0, (pageAddress >> 8) & 0xff, (pageAddress >> 0) & 0xff};
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ENABLE(busdev);
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spiTransfer(busdev->busdev_u.spi.instance, cmd, NULL, sizeof(cmd));
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DISABLE(busdev);
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busSegment_t segments[] = {
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{cmd, NULL, sizeof (cmd), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWait(dev);
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spiSequence(dev, &segments[0]);
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// Block pending completion of SPI access
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spiWait(dev);
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}
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#ifdef USE_QUADSPI
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else if (io->mode == FLASHIO_QUADSPI) {
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@ -190,14 +202,23 @@ static void w25n01g_performCommandWithPageAddress(flashDeviceIO_t *io, uint8_t c
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static uint8_t w25n01g_readRegister(flashDeviceIO_t *io, uint8_t reg)
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{
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if (io->mode == FLASHIO_SPI) {
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busDevice_t *busdev = io->handle.busdev;
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extDevice_t *dev = io->handle.dev;
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ENABLE(busdev);
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const uint8_t cmd[3] = { W25N01G_INSTRUCTION_READ_STATUS_REG, reg, 0 };
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uint8_t cmd[3] = { W25N01G_INSTRUCTION_READ_STATUS_REG, reg, 0 };
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uint8_t in[3];
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spiTransfer(busdev->busdev_u.spi.instance, cmd, in, sizeof(cmd));
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DISABLE(busdev);
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busSegment_t segments[] = {
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{cmd, in, sizeof (cmd), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWait(dev);
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spiSequence(dev, &segments[0]);
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// Block pending completion of SPI access
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spiWait(dev);
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return in[2];
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}
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@ -218,12 +239,21 @@ static uint8_t w25n01g_readRegister(flashDeviceIO_t *io, uint8_t reg)
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static void w25n01g_writeRegister(flashDeviceIO_t *io, uint8_t reg, uint8_t data)
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{
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if (io->mode == FLASHIO_SPI) {
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busDevice_t *busdev = io->handle.busdev;
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const uint8_t cmd[3] = { W25N01G_INSTRUCTION_WRITE_STATUS_REG, reg, data };
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extDevice_t *dev = io->handle.dev;
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uint8_t cmd[3] = { W25N01G_INSTRUCTION_WRITE_STATUS_REG, reg, data };
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ENABLE(busdev);
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spiTransfer(busdev->busdev_u.spi.instance, cmd, NULL, sizeof(cmd));
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DISABLE(busdev);
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busSegment_t segments[] = {
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{cmd, NULL, sizeof (cmd), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWait(dev);
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spiSequence(dev, &segments[0]);
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// Block pending completion of SPI access
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spiWait(dev);
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}
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#ifdef USE_QUADSPI
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else if (io->mode == FLASHIO_QUADSPI) {
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@ -246,7 +276,7 @@ static void w25n01g_deviceReset(flashDevice_t *fdevice)
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// Protection for upper 1/32 (BP[3:0] = 0101, TB=0), WP-E on; to protect bad block replacement area
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// DON'T DO THIS. This will prevent writes through the bblut as well.
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// w25n01g_writeRegister(busdev, W25N01G_PROT_REG, W25N01G_PROT_PB0_ENABLE|W25N01G_PROT_PB2_ENABLE|W25N01G_PROT_WP_E_ENABLE);
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// w25n01g_writeRegister(dev, W25N01G_PROT_REG, W25N01G_PROT_PB0_ENABLE|W25N01G_PROT_PB2_ENABLE|W25N01G_PROT_WP_E_ENABLE);
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// No protection, WP-E off, WP-E prevents use of IO2
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w25n01g_writeRegister(io, W25N01G_PROT_REG, W25N01G_PROT_CLEAR);
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@ -380,13 +410,22 @@ static void w25n01g_programDataLoad(flashDevice_t *fdevice, uint16_t columnAddre
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w25n01g_waitForReady(fdevice);
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if (fdevice->io.mode == FLASHIO_SPI) {
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busDevice_t *busdev = fdevice->io.handle.busdev;
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const uint8_t cmd[] = { W25N01G_INSTRUCTION_PROGRAM_DATA_LOAD, columnAddress >> 8, columnAddress & 0xff };
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extDevice_t *dev = fdevice->io.handle.dev;
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uint8_t cmd[] = { W25N01G_INSTRUCTION_PROGRAM_DATA_LOAD, columnAddress >> 8, columnAddress & 0xff };
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ENABLE(busdev);
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spiTransfer(busdev->busdev_u.spi.instance, cmd, NULL, sizeof(cmd));
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spiTransfer(busdev->busdev_u.spi.instance, data, NULL, length);
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DISABLE(busdev);
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busSegment_t segments[] = {
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{cmd, NULL, sizeof (cmd), true, NULL},
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{(uint8_t *)data, NULL, length, true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWait(dev);
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spiSequence(dev, &segments[0]);
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// Block pending completion of SPI access
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spiWait(dev);
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}
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#ifdef USE_QUADSPI
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else if (fdevice->io.mode == FLASHIO_QUADSPI) {
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@ -401,18 +440,26 @@ static void w25n01g_programDataLoad(flashDevice_t *fdevice, uint16_t columnAddre
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static void w25n01g_randomProgramDataLoad(flashDevice_t *fdevice, uint16_t columnAddress, const uint8_t *data, int length)
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{
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const uint8_t cmd[] = { W25N01G_INSTRUCTION_RANDOM_PROGRAM_DATA_LOAD, columnAddress >> 8, columnAddress & 0xff };
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uint8_t cmd[] = { W25N01G_INSTRUCTION_RANDOM_PROGRAM_DATA_LOAD, columnAddress >> 8, columnAddress & 0xff };
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w25n01g_waitForReady(fdevice);
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if (fdevice->io.mode == FLASHIO_SPI) {
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busDevice_t *busdev = fdevice->io.handle.busdev;
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extDevice_t *dev = fdevice->io.handle.dev;
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ENABLE(busdev);
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spiTransfer(busdev->busdev_u.spi.instance, cmd, NULL, sizeof(cmd));
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spiTransfer(busdev->busdev_u.spi.instance, data, NULL, length);
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DISABLE(busdev);
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busSegment_t segments[] = {
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{cmd, NULL, sizeof (cmd), true, NULL},
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{(uint8_t *)data, NULL, length, true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWait(dev);
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spiSequence(dev, &segments[0]);
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// Block pending completion of SPI access
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spiWait(dev);
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}
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#ifdef USE_QUADSPI
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else if (fdevice->io.mode == FLASHIO_QUADSPI) {
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@ -496,8 +543,6 @@ void w25n01g_pageProgramBegin(flashDevice_t *fdevice, uint32_t address)
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void w25n01g_pageProgramContinue(flashDevice_t *fdevice, const uint8_t *data, int length)
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{
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// Check for page boundary overrun
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w25n01g_waitForReady(fdevice);
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w25n01g_writeEnable(fdevice);
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@ -617,7 +662,7 @@ int w25n01g_readBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer,
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currentPage = targetPage;
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}
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uint16_t column = W25N01G_LINEAR_TO_COLUMN(address);
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int column = W25N01G_LINEAR_TO_COLUMN(address);
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uint16_t transferLength;
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if (length > W25N01G_PAGE_SIZE - column) {
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@ -627,7 +672,7 @@ int w25n01g_readBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer,
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}
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if (fdevice->io.mode == FLASHIO_SPI) {
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busDevice_t *busdev = fdevice->io.handle.busdev;
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extDevice_t *dev = fdevice->io.handle.dev;
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uint8_t cmd[4];
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cmd[0] = W25N01G_INSTRUCTION_READ_DATA;
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@ -635,11 +680,19 @@ int w25n01g_readBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer,
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cmd[2] = (column >> 0) & 0xff;
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cmd[3] = 0;
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ENABLE(busdev);
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spiTransfer(busdev->busdev_u.spi.instance, cmd, NULL, sizeof(cmd));
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spiTransfer(busdev->busdev_u.spi.instance, NULL, buffer, length);
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DISABLE(busdev);
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busSegment_t segments[] = {
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{cmd, NULL, sizeof (cmd), false, NULL},
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{NULL, buffer, length, true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWait(dev);
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spiSequence(dev, &segments[0]);
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// Block pending completion of SPI access
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spiWait(dev);
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}
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#ifdef USE_QUADSPI
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else if (fdevice->io.mode == FLASHIO_QUADSPI) {
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@ -687,7 +740,7 @@ int w25n01g_readExtensionBytes(flashDevice_t *fdevice, uint32_t address, uint8_t
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uint32_t column = 2048;
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if (fdevice->io.mode == FLASHIO_SPI) {
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busDevice_t *busdev = fdevice->io.handle.busdev;
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extDevice_t *dev = fdevice->io.handle.dev;
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uint8_t cmd[4];
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cmd[0] = W25N01G_INSTRUCTION_READ_DATA;
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@ -695,10 +748,19 @@ int w25n01g_readExtensionBytes(flashDevice_t *fdevice, uint32_t address, uint8_t
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cmd[2] = (column >> 0) & 0xff;
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cmd[3] = 0;
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ENABLE(busdev);
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spiTransfer(busdev->busdev_u.spi.instance, cmd, NULL, sizeof(cmd));
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spiTransfer(busdev->busdev_u.spi.instance, NULL, buffer, length);
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DISABLE(busdev);
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busSegment_t segments[] = {
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{cmd, NULL, sizeof (cmd), false, NULL},
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{NULL, buffer, length, true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWait(dev);
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spiSequence(dev, &segments[0]);
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// Block pending completion of SPI access
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spiWait(dev);
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}
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#ifdef USE_QUADSPI
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@ -740,28 +802,35 @@ const flashVTable_t w25n01g_vTable = {
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void w25n01g_readBBLUT(flashDevice_t *fdevice, bblut_t *bblut, int lutsize)
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{
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uint8_t in[4];
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if (fdevice->io.mode == FLASHIO_SPI) {
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busDevice_t *busdev = fdevice->io.handle.busdev;
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extDevice_t *dev = fdevice->io.handle.dev;
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uint8_t cmd[4];
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cmd[0] = W25N01G_INSTRUCTION_READ_BBM_LUT;
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cmd[1] = 0;
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ENABLE(busdev);
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busSegment_t segments[] = {
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{cmd, NULL, sizeof (cmd), false, NULL},
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{NULL, in, sizeof (in), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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spiTransfer(busdev->busdev_u.spi.instance, cmd, NULL, 2);
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// Ensure any prior DMA has completed before continuing
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spiWait(dev);
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spiSequence(dev, &segments[0]);
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// Block pending completion of SPI access
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spiWait(dev);
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for (int i = 0 ; i < lutsize ; i++) {
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spiTransfer(busdev->busdev_u.spi.instance, NULL, in, 4);
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spiReadWriteBuf(dev, NULL, in, 4);
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bblut[i].pba = (in[0] << 16)|in[1];
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bblut[i].lba = (in[2] << 16)|in[3];
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}
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DISABLE(busdev);
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}
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#ifdef USE_QUADSPI
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else if (fdevice->io.mode == FLASHIO_QUADSPI) {
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@ -788,13 +857,22 @@ void w25n01g_writeBBLUT(flashDevice_t *fdevice, uint16_t lba, uint16_t pba)
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w25n01g_waitForReady(fdevice);
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if (fdevice->io.mode == FLASHIO_SPI) {
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busDevice_t *busdev = fdevice->io.handle.busdev;
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extDevice_t *dev = fdevice->io.handle.dev;
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uint8_t cmd[5] = { W25N01G_INSTRUCTION_BB_MANAGEMENT, lba >> 8, lba, pba >> 8, pba };
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ENABLE(busdev);
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spiTransfer(busdev->busdev_u.spi.instance, cmd, NULL, sizeof(cmd));
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DISABLE(busdev);
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busSegment_t segments[] = {
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{cmd, NULL, sizeof (cmd), true, NULL},
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{NULL, NULL, 0, true, NULL},
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};
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// Ensure any prior DMA has completed before continuing
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spiWait(dev);
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spiSequence(dev, &segments[0]);
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// Block pending completion of SPI access
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spiWait(dev);
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}
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#ifdef USE_QUADSPI
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else if (fdevice->io.mode == FLASHIO_QUADSPI) {
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