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update to gcc 8.3.1 (#9061)

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update to gcc 8.3.1
This commit is contained in:
Michael Keller 2019-11-25 18:45:27 +13:00 • committed by GitHub
commit 8d107fab99
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8 changed files with 33 additions and 19 deletions
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7
src/link/stm32_flash_h750_exst.ld
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@ -52,7 +52,7 @@ possible.
*/
/* see .exst section below */
_exst_hash_size = 64;
_exst_hash_size = 64;
/* Specify the memory areas */
MEMORY
@ -61,7 +61,10 @@ MEMORY
DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
RAM (rwx) : ORIGIN = 0x24000000, LENGTH = 64K
CODE_RAM (rx) : ORIGIN = 0x24010000, LENGTH = 448K - _exst_hash_size /* hard coded start address, as required by SPRACINGH7 boot loader, don't change! */
EXST_HASH (rx) : ORIGIN = 0x24010000 + LENGTH(CODE_RAM), LENGTH = _exst_hash_size
/*EXST_HASH (rx) : ORIGIN = 0x24010000 + LENGTH(CODE_RAM), LENGTH = _exst_hash_size*/
/* Workaround for https://sourceware.org/bugzilla/show_bug.cgi?id=24289,
* revert after this has been fixed in the ARM gcc. */
EXST_HASH (rx) : ORIGIN = 0x2407FFC0, LENGTH = _exst_hash_size
D2_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 256K /* SRAM1 + SRAM2 */

7
src/main/build/atomic.h
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@ -137,13 +137,6 @@ static inline uint8_t __basepriSetRetVal(uint8_t prio)
// On gcc 5 and higher, this protects only memory passed as parameter (any type can be used)
// this macro can be used only ONCE PER LINE, but multiple uses per block are fine
#if (__GNUC__ > 7)
# warning "Please verify that ATOMIC_BARRIER works as intended"
// increment version number if BARRIER works
// TODO - use flag to disable ATOMIC_BARRIER and use full barrier instead
// you should check that local variable scope with cleanup spans entire block
#endif
#ifndef __UNIQL
# define __UNIQL_CONCAT2(x,y) x ## y
# define __UNIQL_CONCAT(x,y) __UNIQL_CONCAT2(x,y)

2
src/main/drivers/memprot_stm32h7xx.c
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@ -33,7 +33,7 @@ mpuRegion_t mpuRegions[] = {
#ifdef USE_ITCM_RAM
{
// Mark ITCM-RAM as read-only
// "For Cortex®-M7, TCMs memories always behave as Non-cacheable, Non-shared normal memories, irrespectiveof the memory type attributes defined in the MPU for a memory region containing addresses held in the TCM"
// "For Cortex®-M7, TCMs memories always behave as Non-cacheable, Non-shared normal memories, irrespective of the memory type attributes defined in the MPU for a memory region containing addresses held in the TCM"
// See AN4838
.start = 0x00000000,
.end = 0, // Size defined by "size"

4
src/main/sensors/boardalignment.c
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@ -64,12 +64,12 @@ void initBoardAlignment(const boardAlignment_t *boardAlignment)
buildRotationMatrix(&rotationAngles, &boardRotation);
}
FAST_CODE static void alignBoard(float *vec)
static FAST_CODE void alignBoard(float *vec)
{
applyRotation(vec, &boardRotation);
}
FAST_CODE void alignSensorViaMatrix(float *dest, fp_rotationMatrix_t* sensorRotationMatrix)
FAST_CODE_NOINLINE void alignSensorViaMatrix(float *dest, fp_rotationMatrix_t* sensorRotationMatrix)
{
applyRotation(dest, sensorRotationMatrix);