diff --git a/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_gpio.c b/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_gpio.c
new file mode 100644
index 0000000000..bf7e117ec6
--- /dev/null
+++ b/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_gpio.c
@@ -0,0 +1,535 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_gpio.c
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 04-April-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the GPIO peripheral:
+ * + Initialization and Configuration functions
+ * + GPIO Read and Write functions
+ * + GPIO Alternate functions configuration functions
+ *
+ * @verbatim
+
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
+ (#) Configure the GPIO pin(s) using GPIO_Init()
+ Four possible configuration are available for each pin:
+ (++) Input: Floating, Pull-up, Pull-down.
+ (++) Output: Push-Pull (Pull-up, Pull-down or no Pull),
+ Open Drain (Pull-up, Pull-down or no Pull).
+ In output mode, the speed is configurable: Low, Medium, Fast or High.
+ (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull),
+ Open Drain (Pull-up, Pull-down or no Pull).
+ (++) Analog: required mode when a pin is to be used as ADC channel,
+ DAC output or comparator input.
+ (#) Peripherals alternate function:
+ (++) For ADC, DAC and comparators, configure the desired pin in
+ analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
+ (++) For other peripherals (TIM, USART...):
+ (+++) Connect the pin to the desired peripherals' Alternate
+ Function (AF) using GPIO_PinAFConfig() function.
+ (+++) Configure the desired pin in alternate function mode using
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+ (+++) Select the type, pull-up/pull-down and output speed via
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+ (+++) Call GPIO_Init() function.
+ (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+ (#) To set/reset the level of a pin configured in output mode use
+ GPIO_SetBits()/GPIO_ResetBits()
+ (#) During and just after reset, the alternate functions are not active
+ and the GPIO pins are configured in input floating mode (except JTAG pins).
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
+ general-purpose (PC14 and PC15, respectively) when the LSE
+ oscillator is off. The LSE has priority over the GPIO function.
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose
+ (PF0 and PF1 respectively) when the HSE oscillator is off. The HSE has
+ the priority over the GPIO function.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2014 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_gpio.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Group1 Initialization and Configuration
+ * @brief Initialization and Configuration
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset
+ * values.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @retval None
+ */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ if(GPIOx == GPIOA)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
+ }
+ else if(GPIOx == GPIOB)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
+ }
+ else if(GPIOx == GPIOC)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
+ }
+ else if(GPIOx == GPIOD)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
+ }
+ else if(GPIOx == GPIOE)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
+ }
+ else
+ {
+ if(GPIOx == GPIOF)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified
+ * parameters in the GPIO_InitStruct.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+ * contains the configuration information for the specified GPIO
+ * peripheral.
+ * @note GPIO_Pin: selects the pin to be configured:
+ * GPIO_Pin_0->GPIO_Pin_15 for GPIOA, GPIOB, GPIOC, GPIOD and GPIOE;
+ * GPIO_Pin_0->GPIO_Pin_2, GPIO_Pin_4, GPIO_Pin_6, GPIO_Pin_9
+ * and GPIO_Pin_10 for GPIOF.
+ * @retval None
+ */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+ uint32_t tmpreg = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+ /*-------------------------- Configure the port pins -----------------------*/
+ /*-- GPIO Mode Configuration --*/
+ for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+
+ /* Get the port pins position */
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+ if (currentpin == pos)
+ {
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+ {
+ /* Check Speed mode parameters */
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+
+ /* Speed mode configuration */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
+ GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+
+ /* Check Output mode parameters */
+ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
+
+ /* Output mode configuration */
+ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
+ GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+ }
+
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+
+ GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+ /* Use temporary variable to update PUPDR register configuration, to avoid
+ unexpected transition in the GPIO pin configuration. */
+ tmpreg = GPIOx->PUPDR;
+ tmpreg &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+ tmpreg |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+ GPIOx->PUPDR = tmpreg;
+ }
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
+ GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx: where x can be (A or B or D) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ tmp |= GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKK bit */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit */
+ tmp = GPIOx->LCKR;
+ /* Read LCKK bit */
+ tmp = GPIOx->LCKR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Group2 GPIO Read and Write
+ * @brief GPIO Read and Write
+ *
+@verbatim
+ ===============================================================================
+ ##### GPIO Read and Write #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @retval The input port pin value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: Specifies the port bit to read.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @retval GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval None
+ */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval None
+ */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @param BitVal: specifies the value to be written to the selected bit.
+ * This parameter can be one of the BitAction enumeration values:
+ * @arg Bit_RESET: to clear the port pin
+ * @arg Bit_SET: to set the port pin
+ * @retval None
+ */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+ if (BitVal != Bit_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = GPIO_Pin ;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param PortVal: specifies the value to be written to the port output data
+ * register.
+ * @retval None
+ */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->ODR = PortVal;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
+ * @brief GPIO Alternate functions configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### GPIO Alternate functions configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_PinSource: specifies the pin for the Alternate function.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @param GPIO_AF: selects the pin to be used as Alternate function.
+ * This parameter can be one of the following value:
+ * @arg GPIO_AF_0: JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT, MCO, NJTRST,
+ * TRACED, TRACECK.
+ * @arg GPIO_AF_1: OUT, TIM2, TIM15, TIM16, TIM17.
+ * @arg GPIO_AF_2: COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16.
+ * @arg GPIO_AF_3: COMP7_OUT, TIM8, TIM15, Touch, HRTIM.
+ * @arg GPIO_AF_4: I2C1, I2C2, TIM1, TIM8, TIM16, TIM17.
+ * @arg GPIO_AF_5: IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5
+ * @arg GPIO_AF_6: IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8
+ * @arg GPIO_AF_7: AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT, USART1,
+ * USART2, USART3.
+ * @arg GPIO_AF_8: COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT, COMP5_OUT,
+ * COMP6_OUT.
+ * @arg GPIO_AF_9: AOP4_OUT, CAN, TIM1, TIM8, TIM15.
+ * @arg GPIO_AF_10: AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17.
+ * @arg GPIO_AF_11: TIM1, TIM8.
+ * @arg GPIO_AF_12: TIM1, HRTIM.
+ * @arg GPIO_AF_13: HRTIM, AOP2_OUT.
+ * @arg GPIO_AF_14: USBDM, USBDP.
+ * @arg GPIO_AF_15: OUT.
+ * @note The pin should already been configured in Alternate Function mode(AF)
+ * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+ * @note Refer to the Alternate function mapping table in the device datasheet
+ * for the detailed mapping of the system and peripherals alternate
+ * function I/O pins.
+ * @retval None
+ */
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+ uint32_t temp = 0x00;
+ uint32_t temp_2 = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+ assert_param(IS_GPIO_AF(GPIO_AF));
+
+ temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+ GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+ temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+ GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_gpio.h b/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_gpio.h
new file mode 100644
index 0000000000..033a64f318
--- /dev/null
+++ b/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_gpio.h
@@ -0,0 +1,400 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_gpio.h
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 04-April-2014
+ * @brief This file contains all the functions prototypes for the GPIO
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2014 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_GPIO_H
+#define __STM32F30x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOC) || \
+ ((PERIPH) == GPIOD) || \
+ ((PERIPH) == GPIOE) || \
+ ((PERIPH) == GPIOF))
+
+#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOD))
+/** @defgroup Configuration_Mode_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
+ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
+ GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
+ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+/**
+ * @}
+ */
+
+/** @defgroup Output_type_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_OType_PP = 0x00,
+ GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+/**
+ * @}
+ */
+
+/** @defgroup Output_Maximum_frequency_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */
+ GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */
+ GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
+}GPIOSpeed_TypeDef;
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
+ ((SPEED) == GPIO_Speed_Level_3))
+/**
+ * @}
+ */
+
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_PuPd_NOPULL = 0x00,
+ GPIO_PuPd_UP = 0x01,
+ GPIO_PuPd_DOWN = 0x02
+}GPIOPuPd_TypeDef;
+
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+ ((PUPD) == GPIO_PuPd_DOWN))
+/**
+ * @}
+ */
+
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration
+ * @{
+ */
+typedef enum
+{
+ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+/**
+ * @}
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIOMode_TypeDef */
+
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIOOType_TypeDef */
+
+ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIOPuPd_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+ ((PIN) == GPIO_Pin_1) || \
+ ((PIN) == GPIO_Pin_2) || \
+ ((PIN) == GPIO_Pin_3) || \
+ ((PIN) == GPIO_Pin_4) || \
+ ((PIN) == GPIO_Pin_5) || \
+ ((PIN) == GPIO_Pin_6) || \
+ ((PIN) == GPIO_Pin_7) || \
+ ((PIN) == GPIO_Pin_8) || \
+ ((PIN) == GPIO_Pin_9) || \
+ ((PIN) == GPIO_Pin_10) || \
+ ((PIN) == GPIO_Pin_11) || \
+ ((PIN) == GPIO_Pin_12) || \
+ ((PIN) == GPIO_Pin_13) || \
+ ((PIN) == GPIO_Pin_14) || \
+ ((PIN) == GPIO_Pin_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Pin_sources
+ * @{
+ */
+#define GPIO_PinSource0 ((uint8_t)0x00)
+#define GPIO_PinSource1 ((uint8_t)0x01)
+#define GPIO_PinSource2 ((uint8_t)0x02)
+#define GPIO_PinSource3 ((uint8_t)0x03)
+#define GPIO_PinSource4 ((uint8_t)0x04)
+#define GPIO_PinSource5 ((uint8_t)0x05)
+#define GPIO_PinSource6 ((uint8_t)0x06)
+#define GPIO_PinSource7 ((uint8_t)0x07)
+#define GPIO_PinSource8 ((uint8_t)0x08)
+#define GPIO_PinSource9 ((uint8_t)0x09)
+#define GPIO_PinSource10 ((uint8_t)0x0A)
+#define GPIO_PinSource11 ((uint8_t)0x0B)
+#define GPIO_PinSource12 ((uint8_t)0x0C)
+#define GPIO_PinSource13 ((uint8_t)0x0D)
+#define GPIO_PinSource14 ((uint8_t)0x0E)
+#define GPIO_PinSource15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+ ((PINSOURCE) == GPIO_PinSource1) || \
+ ((PINSOURCE) == GPIO_PinSource2) || \
+ ((PINSOURCE) == GPIO_PinSource3) || \
+ ((PINSOURCE) == GPIO_PinSource4) || \
+ ((PINSOURCE) == GPIO_PinSource5) || \
+ ((PINSOURCE) == GPIO_PinSource6) || \
+ ((PINSOURCE) == GPIO_PinSource7) || \
+ ((PINSOURCE) == GPIO_PinSource8) || \
+ ((PINSOURCE) == GPIO_PinSource9) || \
+ ((PINSOURCE) == GPIO_PinSource10) || \
+ ((PINSOURCE) == GPIO_PinSource11) || \
+ ((PINSOURCE) == GPIO_PinSource12) || \
+ ((PINSOURCE) == GPIO_PinSource13) || \
+ ((PINSOURCE) == GPIO_PinSource14) || \
+ ((PINSOURCE) == GPIO_PinSource15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Alternate_function_selection_define
+ * @{
+ */
+
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,
+ MCO, NJTRST, TRACED, TRACECK */
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch, HRTIM1 */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT,
+ USART1, USART2, USART3 */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT,
+ COMP5_OUT, COMP6_OUT */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF_12 ((uint8_t)0x0C) /* TIM1, HRTIM1 */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF_13 ((uint8_t)0x0D) /* HRTIM1, AOP2_OUT */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
+ ((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
+ ((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
+ ((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
+ ((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
+ ((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
+ ((AF) == GPIO_AF_12)||((AF) == GPIO_AF_13)||\
+ ((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Speed_Legacy
+ * @{
+ */
+
+#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
+#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
+#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the GPIO configuration to the default reset state *****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+
+/* GPIO Alternate functions configuration functions ***************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_GPIO_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_rcc.c b/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_rcc.c
new file mode 100644
index 0000000000..a0c1ecccfc
--- /dev/null
+++ b/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_rcc.c
@@ -0,0 +1,1951 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_rcc.c
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 04-April-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Reset and clock control (RCC) peripheral:
+ * + Internal/external clocks, PLL, CSS and MCO configuration
+ * + System, AHB and APB busses clocks configuration
+ * + Peripheral clocks configuration
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### RCC specific features #####
+ ===============================================================================
+ [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
+ all peripherals are off except internal SRAM, Flash and SWD.
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+ all peripherals mapped on these busses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+ (+) All GPIOs are in input floating state, except the SWD pins which
+ are assigned to be used for debug purpose.
+ [..] Once the device starts from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance).
+ (+) Configure the System clock frequency and Flash settings.
+ (+) Configure the AHB and APB busses prescalers.
+ (+) Enable the clock for the peripheral(s) to be used.
+ (+) Configure the clock source(s) for peripherals which clocks are not
+ derived from the System clock (ADC, TIM, I2C, USART, RTC and IWDG).
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2014 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of HSION bit */
+#define CR_OFFSET (RCC_OFFSET + 0x00)
+#define HSION_BitNumber 0x00
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber 0x18
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber 0x13
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of USBPRE bit */
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)
+#define USBPRE_BitNumber 0x16
+#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
+/* Alias word address of I2SSRC bit */
+#define I2SSRC_BitNumber 0x17
+#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
+
+/* --- BDCR Register ---*/
+
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber 0x0F
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber 0x10
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of LSION bit */
+#define CSR_OFFSET (RCC_OFFSET + 0x24)
+#define LSION_BitNumber 0x00
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+/* RCC Flag Mask */
+#define FLAG_MASK ((uint8_t)0x1F)
+
+/* CFGR register byte 3 (Bits[31:23]) base address */
+#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint16_t ADCPrescTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 };
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Private_Functions
+ * @{
+ */
+
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
+ * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to configure the internal/external
+ clocks, PLL, CSS and MCO.
+ (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
+ or through the PLL as System clock source.
+ The HSI clock can be used also to clock the USART and I2C peripherals.
+ (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+ (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also as RTC clock source.
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+ LSE can be used also to clock the USART peripherals.
+ (#) PLL (clocked by HSI or HSE), for System clock.
+ (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
+ (HSE used directly or through PLL as System clock source), the System clock
+ is automatically switched to HSI and an interrupt is generated if enabled.
+ The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
+ exception vector.
+ (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE,
+ PLL clock on PA8 pin.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * @note HSI ON and used as system clock source
+ * @note HSE and PLL OFF
+ * @note AHB, APB1 and APB2 prescalers set to 1.
+ * @note CSS and MCO OFF
+ * @note All interrupts disabled
+ * @note However, this function doesn't modify the configuration of the
+ * @note Peripheral clocks
+ * @note LSI, LSE and RTC clocks
+ * @param None
+ * @retval None
+ */
+void RCC_DeInit(void)
+{
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
+ RCC->CFGR &= (uint32_t)0xF8FFC000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+ /* Reset PREDIV1[3:0] and ADCPRE[13:4] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFC000;
+
+ /* Reset USARTSW[1:0], I2CSW and TIMSW bits */
+ RCC->CFGR3 &= (uint32_t)0xF00ECCC;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+}
+
+/**
+ * @brief Configures the External High Speed oscillator (HSE).
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function resets the CSSON bit, so if the Clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param RCC_HSE: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_HSEConfig(uint8_t RCC_HSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_HSE));
+
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
+
+ /* Set the new HSE configuration -------------------------------------------*/
+ *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
+
+}
+
+/**
+ * @brief Waits for HSE start-up.
+ * @note This function waits on HSERDY flag to be set and return SUCCESS if
+ * this flag is set, otherwise returns ERROR if the timeout is reached
+ * and this flag is not set. The timeout value is defined by the constant
+ * HSE_STARTUP_TIMEOUT in stm32f30x.h file. You can tailor it depending
+ * on the HSE crystal used in your application.
+ * @param None
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSEStatus = RESET;
+
+ /* Wait till HSE is ready and if timeout is reached exit */
+ do
+ {
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+ StartUpCounter++;
+ } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * Refer to the Application Note AN3300 for more details on how to
+ * calibrate the HSI.
+ * @param HSICalibrationValue: specifies the HSI calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ * @retval None
+ */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
+
+ tmpreg = RCC->CR;
+
+ /* Clear HSITRIM[4:0] bits */
+ tmpreg &= ~RCC_CR_HSITRIM;
+
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;
+
+ /* Store the new value */
+ RCC->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).
+ * @note After enabling the HSI, the application software should wait on
+ * HSIRDY flag to be set indicating that HSI clock is stable and can
+ * be used to clock the PLL and/or system clock.
+ * @note HSI can not be stopped if it is used directly or through the PLL
+ * as system clock. In this case, you have to select another source
+ * of the system clock then stop the HSI.
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ * @param NewState: new state of the HSI.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_HSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE).
+ * @note As the LSE is in the Backup domain and write access is denied to this
+ * domain after reset, you have to enable write access using
+ * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
+ * software should wait on LSERDY flag to be set indicating that LSE clock
+ * is stable and can be used to clock the RTC.
+ * @param RCC_LSE: specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+ * 6 LSE oscillator clock cycles.
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_LSEConfig(uint32_t RCC_LSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_LSE));
+
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+ /* Reset LSEON bit */
+ RCC->BDCR &= ~(RCC_BDCR_LSEON);
+
+ /* Reset LSEBYP bit */
+ RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
+
+ /* Configure LSE */
+ RCC->BDCR |= RCC_LSE;
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE) drive capability.
+ * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
+ * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
+ * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
+ * @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
+ * @retval None
+ */
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
+
+ /* Clear LSEDRV[1:0] bits */
+ RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
+
+ /* Set the LSE Drive */
+ RCC->BDCR |= RCC_LSEDrive;
+}
+
+/**
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ * @param NewState: new state of the LSI.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_LSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the PLL clock source and multiplication factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
+ * PLL source).
+ * @param RCC_PLLSource: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as
+ * PLL clock entry
+ * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock source
+ * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
+ * This parameter can be RCC_PLLMul_x where x:[2,16]
+ *
+ * @retval None
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+ /* Clear PLL Source [16] and Multiplier [21:18] bits */
+ RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
+
+ /* Set the PLL Source and Multiplier */
+ RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
+}
+
+/**
+ * @brief Enables or disables the PLL.
+ * @note After enabling the PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The PLL can not be disabled if it is used as system clock source
+ * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
+ * @param NewState: new state of the PLL.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the PREDIV1 division factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
+ * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
+ * @retval None
+ */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PREDIV1[3:0] bits */
+ tmpreg &= ~(RCC_CFGR2_PREDIV1);
+
+ /* Set the PREDIV1 division factor */
+ tmpreg |= RCC_PREDIV1_Div;
+
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+ * @param NewState: new state of the Clock Security System.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
+}
+
+#ifdef STM32F303xC
+/**
+ * @brief Selects the clock source to output on MCO pin (PA8).
+ * @note PA8 should be configured in alternate function mode.
+ * @param RCC_MCOSource: specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCOSource_NoClock: No clock selected.
+ * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
+ * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
+ * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
+ * @arg RCC_MCOSource_SYSCLK: System clock selected.
+ * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
+ * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
+ * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
+ * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
+ * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
+ * @retval None
+ */
+void RCC_MCOConfig(uint8_t RCC_MCOSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
+
+ /* Get CFGR value */
+ tmpreg = RCC->CFGR;
+ /* Clear MCO[3:0] bits */
+ tmpreg &= ~(RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
+ /* Set the RCC_MCOSource */
+ tmpreg |= RCC_MCOSource<<24;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+#else
+
+/**
+ * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding
+ * prescsaler.
+ * @note PA8 should be configured in alternate function mode.
+ * @param RCC_MCOSource: specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCOSource_NoClock: No clock selected.
+ * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
+ * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
+ * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
+ * @arg RCC_MCOSource_SYSCLK: System clock selected.
+ * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
+ * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
+ * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
+ * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
+ * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
+ * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
+ * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
+ * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
+ * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
+ * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
+ * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
+ * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
+ * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
+ * @retval None
+ */
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
+ assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
+
+ /* Get CFGR value */
+ tmpreg = RCC->CFGR;
+ /* Clear MCOPRE[2:0] bits */
+ tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
+ /* Set the RCC_MCOSource and RCC_MCOPrescaler */
+ tmpreg |= (RCC_MCOPrescaler | RCC_MCOSource<<24);
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+#endif /* STM32F303xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Group2 System AHB, APB1 and APB2 busses clocks configuration functions
+ * @brief System, AHB and APB busses clocks configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### System, AHB, APB1 and APB2 busses clocks configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the System, AHB, APB1 and
+ APB2 busses clocks.
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ HSE and PLL.
+ The AHB clock (HCLK) is derived from System clock through configurable prescaler
+ and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
+ APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
+ configurable prescalers and used to clock the peripherals mapped on these busses.
+ You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
+
+ (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz.
+ Depending on the maximum frequency, the FLASH wait states (WS) should be
+ adapted accordingly:
+ +---------------------------------+
+ | Wait states | HCLK clock |
+ | (Latency) | frequency (MHz) |
+ |-------------- |-----------------|
+ |0WS(1CPU cycle)| 0 < HCLK <= 24 |
+ |---------------|-----------------|
+ |1WS(2CPU cycle)|24 < HCLK <=48 |
+ |---------------|-----------------|
+ |2WS(3CPU cycle)|48 < HCLK <= 72 |
+ +---------------------------------+
+
+ (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
+ prefetch is disabled.
+ [..]
+ (@) All the peripheral clocks are derived from the System clock (SYSCLK)
+ except:
+ (+@) The FLASH program/erase clock which is always HSI 8MHz clock.
+ (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
+ (+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
+ (+@) The I2C clock which can be derived as well from HSI 8MHz clock.
+ (+@) The ADC clock which is derived from PLL output.
+ (+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
+ (HSE divided by a programmable prescaler). The System clock (SYSCLK)
+ frequency must be higher or equal to the RTC clock frequency.
+ (+@) IWDG clock which is always the LSI clock.
+ [..] It is recommended to use the following software sequences to tune the number
+ of wait states needed to access the Flash memory with the CPU frequency (HCLK).
+ (+) Increasing the CPU frequency
+ (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
+ function
+ (++) Check that Flash Prefetch buffer activation is taken into account by
+ reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
+ (++) Program Flash WS to 1 or 2, using "FLASH_SetLatency()" function
+ (++) Check that the new number of WS is taken into account by reading FLASH_ACR
+ (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
+ (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
+ (++) Check that the new CPU clock source is taken into account by reading
+ the clock source status, using "RCC_GetSYSCLKSource()" function
+ (+) Decreasing the CPU frequency
+ (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
+ (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
+ (++) Check that the new CPU clock source is taken into account by reading
+ the clock source status, using "RCC_GetSYSCLKSource()" function
+ (++) Program the new number of WS, using "FLASH_SetLatency()" function
+ (++) Check that the new number of WS is taken into account by reading FLASH_ACR
+ (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
+ function
+ (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
+ using the FLASH_GetPrefetchBufferStatus() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the system clock (SYSCLK).
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ * You can use RCC_GetSYSCLKSource() function to know which clock is
+ * currently used as system clock source.
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock source
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
+ * @retval None
+ */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear SW[1:0] bits */
+ tmpreg &= ~RCC_CFGR_SW;
+
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpreg |= RCC_SYSCLKSource;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Returns the clock source used as system clock.
+ * @param None
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following values:
+ * - 0x00: HSI used as system clock
+ * - 0x04: HSE used as system clock
+ * - 0x08: PLL used as system clock
+ */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+ return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
+}
+
+/**
+ * @brief Configures the AHB clock (HCLK).
+ * @note Depending on the device voltage range, the software has to set correctly
+ * these bits to ensure that the system frequency does not exceed the
+ * maximum allowed frequency (for more details refer to section above
+ * "CPU, AHB and APB busses clocks configuration functions").
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
+ * the system clock (SYSCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+ * @retval None
+ */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear HPRE[3:0] bits */
+ tmpreg &= ~RCC_CFGR_HPRE;
+
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+ tmpreg |= RCC_SYSCLK;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE1[2:0] bits */
+ tmpreg &= ~RCC_CFGR_PPRE1;
+
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE2[2:0] bits */
+ tmpreg &= ~RCC_CFGR_PPRE2;
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK << 3;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks.
+ *
+ * @note This function returns the frequencies of :
+ * System, AHB, APB2 and APB1 busses clocks, ADC1/2/3/4 clocks,
+ * USART1/2/3/4/5 clocks, I2C1/2 clocks and TIM1/8 Clocks.
+ *
+ * @note The frequency returned by this function is not the real frequency
+ * in the chip. It is calculated based on the predefined constant and
+ * the source selected by RCC_SYSCLKConfig().
+ *
+ * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
+ *
+ * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
+ *
+ * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * @note (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
+ *
+ * @note (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * return wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
+ * the clocks frequencies.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+ * must be called to update the structure's field. Otherwise, any
+ * configuration based on this function will be incorrect.
+ *
+ * @retval None
+ */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
+ uint32_t apb2presc = 0, ahbpresc = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ pllclk = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ pllclk = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ RCC_Clocks->SYSCLK_Frequency = pllclk;
+ break;
+ default: /* HSI used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = RCC->CFGR & RCC_CFGR_HPRE;
+ tmp = tmp >> 4;
+ ahbpresc = APBAHBPrescTable[tmp];
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> ahbpresc;
+
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFGR & RCC_CFGR_PPRE1;
+ tmp = tmp >> 8;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFGR & RCC_CFGR_PPRE2;
+ tmp = tmp >> 11;
+ apb2presc = APBAHBPrescTable[tmp];
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> apb2presc;
+
+ /* Get ADC12CLK prescaler */
+ tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE12;
+ tmp = tmp >> 4;
+ presc = ADCPrescTable[tmp & 0x0F];
+ if (((tmp & 0x10) != 0) && (presc != 0))
+ {
+ /* ADC12CLK clock frequency is derived from PLL clock */
+ RCC_Clocks->ADC12CLK_Frequency = pllclk / presc;
+ }
+ else
+ {
+ /* ADC12CLK clock frequency is AHB clock */
+ RCC_Clocks->ADC12CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+
+ /* Get ADC34CLK prescaler */
+ tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE34;
+ tmp = tmp >> 9;
+ presc = ADCPrescTable[tmp & 0x0F];
+ if (((tmp & 0x10) != 0) && (presc != 0))
+ {
+ /* ADC34CLK clock frequency is derived from PLL clock */
+ RCC_Clocks->ADC34CLK_Frequency = pllclk / presc;
+ }
+ else
+ {
+ /* ADC34CLK clock frequency is AHB clock */
+ RCC_Clocks->ADC34CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+
+ /* I2C1CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
+ {
+ /* I2C1 Clock is HSI Osc. */
+ RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* I2C1 Clock is System Clock */
+ RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+
+ /* I2C2CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_I2C2SW) != RCC_CFGR3_I2C2SW)
+ {
+ /* I2C2 Clock is HSI Osc. */
+ RCC_Clocks->I2C2CLK_Frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* I2C2 Clock is System Clock */
+ RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+
+ /* I2C3CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_I2C3SW) != RCC_CFGR3_I2C3SW)
+ {
+ /* I2C3 Clock is HSI Osc. */
+ RCC_Clocks->I2C3CLK_Frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* I2C3 Clock is System Clock */
+ RCC_Clocks->I2C3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+
+ /* TIM1CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_TIM1SW) == RCC_CFGR3_TIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* TIM1 Clock is 2 * pllclk */
+ RCC_Clocks->TIM1CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* TIM1 Clock is APB2 clock. */
+ RCC_Clocks->TIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* TIM1CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_HRTIM1SW) == RCC_CFGR3_HRTIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* HRTIM1 Clock is 2 * pllclk */
+ RCC_Clocks->HRTIM1CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* HRTIM1 Clock is APB2 clock. */
+ RCC_Clocks->HRTIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* TIM8CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_TIM8SW) == RCC_CFGR3_TIM8SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* TIM8 Clock is 2 * pllclk */
+ RCC_Clocks->TIM8CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* TIM8 Clock is APB2 clock. */
+ RCC_Clocks->TIM8CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* TIM15CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_TIM15SW) == RCC_CFGR3_TIM15SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* TIM15 Clock is 2 * pllclk */
+ RCC_Clocks->TIM15CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* TIM15 Clock is APB2 clock. */
+ RCC_Clocks->TIM15CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* TIM16CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_TIM16SW) == RCC_CFGR3_TIM16SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* TIM16 Clock is 2 * pllclk */
+ RCC_Clocks->TIM16CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* TIM16 Clock is APB2 clock. */
+ RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* TIM17CLK clock frequency */
+ if(((RCC->CFGR3 & RCC_CFGR3_TIM17SW) == RCC_CFGR3_TIM17SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
+ && (apb2presc == ahbpresc))
+ {
+ /* TIM17 Clock is 2 * pllclk */
+ RCC_Clocks->TIM17CLK_Frequency = pllclk * 2;
+ }
+ else
+ {
+ /* TIM17 Clock is APB2 clock. */
+ RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+ }
+
+ /* USART1CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
+ {
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F301x8) || defined(STM32F302x8)
+ /* USART1 Clock is PCLK1 instead of PCLK2 (limitation described in the
+ STM32F302/01/34 x4/x6/x8 respective erratasheets) */
+ RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+#else
+ /* USART Clock is PCLK2 */
+ RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+#endif
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
+ {
+ /* USART Clock is System Clock */
+ RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
+ {
+ /* USART Clock is LSE Osc. */
+ RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
+ {
+ /* USART Clock is HSI Osc. */
+ RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
+ }
+
+ /* USART2CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
+ {
+ /* USART Clock is PCLK */
+ RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
+ {
+ /* USART Clock is System Clock */
+ RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
+ {
+ /* USART Clock is LSE Osc. */
+ RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
+ {
+ /* USART Clock is HSI Osc. */
+ RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
+ }
+
+ /* USART3CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0)
+ {
+ /* USART Clock is PCLK */
+ RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0)
+ {
+ /* USART Clock is System Clock */
+ RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1)
+ {
+ /* USART Clock is LSE Osc. */
+ RCC_Clocks->USART3CLK_Frequency = LSE_VALUE;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW)
+ {
+ /* USART Clock is HSI Osc. */
+ RCC_Clocks->USART3CLK_Frequency = HSI_VALUE;
+ }
+
+ /* UART4CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == 0x0)
+ {
+ /* USART Clock is PCLK */
+ RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_0)
+ {
+ /* USART Clock is System Clock */
+ RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_1)
+ {
+ /* USART Clock is LSE Osc. */
+ RCC_Clocks->UART4CLK_Frequency = LSE_VALUE;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW)
+ {
+ /* USART Clock is HSI Osc. */
+ RCC_Clocks->UART4CLK_Frequency = HSI_VALUE;
+ }
+
+ /* UART5CLK clock frequency */
+ if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == 0x0)
+ {
+ /* USART Clock is PCLK */
+ RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_0)
+ {
+ /* USART Clock is System Clock */
+ RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_1)
+ {
+ /* USART Clock is LSE Osc. */
+ RCC_Clocks->UART5CLK_Frequency = LSE_VALUE;
+ }
+ else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW)
+ {
+ /* USART Clock is HSI Osc. */
+ RCC_Clocks->UART5CLK_Frequency = HSI_VALUE;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions
+ * @brief Peripheral clocks configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral clocks configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the Peripheral clocks.
+ (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32
+ (HSE divided by 32).
+ (#) After restart from Reset or wakeup from STANDBY, all peripherals are
+ off except internal SRAM, Flash and SWD. Before to start using
+ a peripheral you have to enable its interface clock. You can do this
+ using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd()
+ and RCC_APB1PeriphClockCmd() functions.
+ (#) To reset the peripherals configuration (to the default state after
+ device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd()
+ and RCC_APB1PeriphResetCmd() functions.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the ADC clock (ADCCLK).
+ * @param RCC_PLLCLK: defines the ADC clock divider. This clock is derived from
+ * the PLL Clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_ADC12PLLCLK_OFF: ADC12 clock disabled
+ * @arg RCC_ADC12PLLCLK_Div1: ADC12 clock = PLLCLK/1
+ * @arg RCC_ADC12PLLCLK_Div2: ADC12 clock = PLLCLK/2
+ * @arg RCC_ADC12PLLCLK_Div4: ADC12 clock = PLLCLK/4
+ * @arg RCC_ADC12PLLCLK_Div6: ADC12 clock = PLLCLK/6
+ * @arg RCC_ADC12PLLCLK_Div8: ADC12 clock = PLLCLK/8
+ * @arg RCC_ADC12PLLCLK_Div10: ADC12 clock = PLLCLK/10
+ * @arg RCC_ADC12PLLCLK_Div12: ADC12 clock = PLLCLK/12
+ * @arg RCC_ADC12PLLCLK_Div16: ADC12 clock = PLLCLK/16
+ * @arg RCC_ADC12PLLCLK_Div32: ADC12 clock = PLLCLK/32
+ * @arg RCC_ADC12PLLCLK_Div64: ADC12 clock = PLLCLK/64
+ * @arg RCC_ADC12PLLCLK_Div128: ADC12 clock = PLLCLK/128
+ * @arg RCC_ADC12PLLCLK_Div256: ADC12 clock = PLLCLK/256
+ * @arg RCC_ADC34PLLCLK_OFF: ADC34 clock disabled
+ * @arg RCC_ADC34PLLCLK_Div1: ADC34 clock = PLLCLK/1
+ * @arg RCC_ADC34PLLCLK_Div2: ADC34 clock = PLLCLK/2
+ * @arg RCC_ADC34PLLCLK_Div4: ADC34 clock = PLLCLK/4
+ * @arg RCC_ADC34PLLCLK_Div6: ADC34 clock = PLLCLK/6
+ * @arg RCC_ADC34PLLCLK_Div8: ADC34 clock = PLLCLK/8
+ * @arg RCC_ADC34PLLCLK_Div10: ADC34 clock = PLLCLK/10
+ * @arg RCC_ADC34PLLCLK_Div12: ADC34 clock = PLLCLK/12
+ * @arg RCC_ADC34PLLCLK_Div16: ADC34 clock = PLLCLK/16
+ * @arg RCC_ADC34PLLCLK_Div32: ADC34 clock = PLLCLK/32
+ * @arg RCC_ADC34PLLCLK_Div64: ADC34 clock = PLLCLK/64
+ * @arg RCC_ADC34PLLCLK_Div128: ADC34 clock = PLLCLK/128
+ * @arg RCC_ADC34PLLCLK_Div256: ADC34 clock = PLLCLK/256
+ * @retval None
+ */
+void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCCLK(RCC_PLLCLK));
+
+ tmp = (RCC_PLLCLK >> 28);
+
+ /* Clears ADCPRE34 bits */
+ if (tmp != 0)
+ {
+ RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE34;
+ }
+ /* Clears ADCPRE12 bits */
+ else
+ {
+ RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE12;
+ }
+ /* Set ADCPRE bits according to RCC_PLLCLK value */
+ RCC->CFGR2 |= RCC_PLLCLK;
+}
+
+/**
+ * @brief Configures the I2C clock (I2CCLK).
+ * @param RCC_I2CCLK: defines the I2C clock source. This clock is derived
+ * from the HSI or System clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2CxCLK_HSI: I2Cx clock = HSI
+ * @arg RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock
+ * (x can be 1 or 2 or 3).
+ * @retval None
+ */
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
+
+ tmp = (RCC_I2CCLK >> 28);
+
+ /* Clear I2CSW bit */
+ switch (tmp)
+ {
+ case 0x00:
+ RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
+ break;
+ case 0x01:
+ RCC->CFGR3 &= ~RCC_CFGR3_I2C2SW;
+ break;
+ case 0x02:
+ RCC->CFGR3 &= ~RCC_CFGR3_I2C3SW;
+ break;
+ default:
+ break;
+ }
+
+ /* Set I2CSW bits according to RCC_I2CCLK value */
+ RCC->CFGR3 |= RCC_I2CCLK;
+}
+
+/**
+ * @brief Configures the TIMx clock sources(TIMCLK).
+ * @note The configuration of the TIMx clock source is only possible when the
+ * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
+ * @note If one of the previous conditions is missed, the TIM clock source
+ * configuration is lost and calling again this function becomes mandatory.
+ * @param RCC_TIMCLK: defines the TIMx clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIMxCLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
+ * when prescaled)
+ * @arg RCC_TIMxCLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
+ * (x can be 1, 8, 15, 16, 17).
+ * @retval None
+ */
+void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_TIMCLK(RCC_TIMCLK));
+
+ tmp = (RCC_TIMCLK >> 28);
+
+ /* Clear TIMSW bit */
+
+ switch (tmp)
+ {
+ case 0x00:
+ RCC->CFGR3 &= ~RCC_CFGR3_TIM1SW;
+ break;
+ case 0x01:
+ RCC->CFGR3 &= ~RCC_CFGR3_TIM8SW;
+ break;
+ case 0x02:
+ RCC->CFGR3 &= ~RCC_CFGR3_TIM15SW;
+ break;
+ case 0x03:
+ RCC->CFGR3 &= ~RCC_CFGR3_TIM16SW;
+ break;
+ case 0x04:
+ RCC->CFGR3 &= ~RCC_CFGR3_TIM17SW;
+ break;
+ default:
+ break;
+ }
+
+ /* Set I2CSW bits according to RCC_TIMCLK value */
+ RCC->CFGR3 |= RCC_TIMCLK;
+}
+
+/**
+ * @brief Configures the HRTIM1 clock sources(HRTIM1CLK).
+ * @note The configuration of the HRTIM1 clock source is only possible when the
+ * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
+ * @note If one of the previous conditions is missed, the TIM clock source
+ * configuration is lost and calling again this function becomes mandatory.
+ * @param RCC_HRTIMCLK: defines the TIMx clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_HRTIM1CLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
+ * when prescaled)
+ * @arg RCC_HRTIM1CLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
+ * (x can be 1 or 8).
+ * @retval None
+ */
+void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HRTIMCLK(RCC_HRTIMCLK));
+
+ /* Clear HRTIMSW bit */
+ RCC->CFGR3 &= ~RCC_CFGR3_HRTIM1SW;
+
+ /* Set HRTIMSW bits according to RCC_HRTIMCLK value */
+ RCC->CFGR3 |= RCC_HRTIMCLK;
+}
+
+/**
+ * @brief Configures the USART clock (USARTCLK).
+ * @param RCC_USARTCLK: defines the USART clock source. This clock is derived
+ * from the HSI or System clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK)
+ * @arg RCC_USARTxCLK_SYSCLK: USART clock = System Clock
+ * @arg RCC_USARTxCLK_LSE: USART clock = LSE Clock
+ * @arg RCC_USARTxCLK_HSI: USART clock = HSI Clock
+ * (x can be 1, 2, 3, 4 or 5).
+ * @retval None
+ */
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
+
+ tmp = (RCC_USARTCLK >> 28);
+
+ /* Clear USARTSW[1:0] bit */
+ switch (tmp)
+ {
+ case 0x01: /* clear USART1SW */
+ RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
+ break;
+ case 0x02: /* clear USART2SW */
+ RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
+ break;
+ case 0x03: /* clear USART3SW */
+ RCC->CFGR3 &= ~RCC_CFGR3_USART3SW;
+ break;
+ case 0x04: /* clear UART4SW */
+ RCC->CFGR3 &= ~RCC_CFGR3_UART4SW;
+ break;
+ case 0x05: /* clear UART5SW */
+ RCC->CFGR3 &= ~RCC_CFGR3_UART5SW;
+ break;
+ default:
+ break;
+ }
+
+ /* Set USARTSW bits according to RCC_USARTCLK value */
+ RCC->CFGR3 |= RCC_USARTCLK;
+}
+
+/**
+ * @brief Configures the USB clock (USBCLK).
+ * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
+ * derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
+ * clock source
+ * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+ * @retval None
+ */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
+
+ *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
+}
+
+/**
+ * @brief Configures the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using PWR_BackupAccessCmd(ENABLE) function before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the RTC
+ * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
+ *
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
+ *
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the HSE clock is used as RTC clock source, the RTC
+ * cannot be used in STOP and STANDBY modes.
+ * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as
+ * RTC clock source).
+ * @retval None
+ */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+
+ /* Select the RTC clock source */
+ RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/**
+ * @brief Configures the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the SPI2 and SPI3 clocks.
+ * @param RCC_I2SCLKSource: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S2CLKSource_SYSCLK: SYSCLK clock used as I2S clock source
+ * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ * @retval None
+ */
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
+
+ *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
+}
+
+/**
+ * @brief Enables or disables the RTC clock.
+ * @note This function must be used only after the RTC clock source was selected
+ * using the RCC_RTCCLKConfig function.
+ * @param NewState: new state of the RTC clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Forces or releases the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_BDCR register.
+ * @param NewState: new state of the Backup domain reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHBPeriph_GPIOA
+ * @arg RCC_AHBPeriph_GPIOB
+ * @arg RCC_AHBPeriph_GPIOC
+ * @arg RCC_AHBPeriph_GPIOD
+ * @arg RCC_AHBPeriph_GPIOE
+ * @arg RCC_AHBPeriph_GPIOF
+ * @arg RCC_AHBPeriph_TS
+ * @arg RCC_AHBPeriph_CRC
+ * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
+ * @arg RCC_AHBPeriph_SRAM
+ * @arg RCC_AHBPeriph_DMA2
+ * @arg RCC_AHBPeriph_DMA1
+ * @arg RCC_AHBPeriph_ADC34
+ * @arg RCC_AHBPeriph_ADC12
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBENR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBENR &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_SYSCFG
+ * @arg RCC_APB2Periph_SPI1
+ * @arg RCC_APB2Periph_USART1
+ * @arg RCC_APB2Periph_TIM15
+ * @arg RCC_APB2Periph_TIM16
+ * @arg RCC_APB2Periph_TIM17
+ * @arg RCC_APB2Periph_TIM1
+ * @arg RCC_APB2Periph_TIM8
+ * @arg RCC_APB2Periph_HRTIM1
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB2ENR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2ENR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2
+ * @arg RCC_APB1Periph_TIM3
+ * @arg RCC_APB1Periph_TIM4
+ * @arg RCC_APB1Periph_TIM6
+ * @arg RCC_APB1Periph_TIM7
+ * @arg RCC_APB1Periph_WWDG
+ * @arg RCC_APB1Periph_SPI2
+ * @arg RCC_APB1Periph_SPI3
+ * @arg RCC_APB1Periph_USART2
+ * @arg RCC_APB1Periph_USART3
+ * @arg RCC_APB1Periph_UART4
+ * @arg RCC_APB1Periph_UART5
+ * @arg RCC_APB1Periph_I2C1
+ * @arg RCC_APB1Periph_I2C2
+ * @arg RCC_APB1Periph_USB
+ * @arg RCC_APB1Periph_CAN1
+ * @arg RCC_APB1Periph_PWR
+ * @arg RCC_APB1Periph_DAC1
+ * @arg RCC_APB1Periph_DAC2
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB1ENR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1ENR &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases AHB peripheral reset.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHBPeriph_GPIOA
+ * @arg RCC_AHBPeriph_GPIOB
+ * @arg RCC_AHBPeriph_GPIOC
+ * @arg RCC_AHBPeriph_GPIOD
+ * @arg RCC_AHBPeriph_GPIOE
+ * @arg RCC_AHBPeriph_GPIOF
+ * @arg RCC_AHBPeriph_TS
+ * @arg RCC_AHBPeriph_ADC34
+ * @arg RCC_AHBPeriph_ADC12
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBRSTR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_SYSCFG
+ * @arg RCC_APB2Periph_SPI1
+ * @arg RCC_APB2Periph_USART1
+ * @arg RCC_APB2Periph_TIM15
+ * @arg RCC_APB2Periph_TIM16
+ * @arg RCC_APB2Periph_TIM17
+ * @arg RCC_APB2Periph_TIM1
+ * @arg RCC_APB2Periph_TIM8
+ * @arg RCC_APB2Periph_HRTIM1
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB2RSTR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2RSTR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2
+ * @arg RCC_APB1Periph_TIM3
+ * @arg RCC_APB1Periph_TIM4
+ * @arg RCC_APB1Periph_TIM6
+ * @arg RCC_APB1Periph_TIM7
+ * @arg RCC_APB1Periph_WWDG
+ * @arg RCC_APB1Periph_SPI2
+ * @arg RCC_APB1Periph_SPI3
+ * @arg RCC_APB1Periph_USART2
+ * @arg RCC_APB1Periph_USART3
+ * @arg RCC_APB1Periph_UART4
+ * @arg RCC_APB1Periph_UART5
+ * @arg RCC_APB1Periph_I2C1
+ * @arg RCC_APB1Periph_I2C2
+ * @arg RCC_APB1Periph_I2C3
+ * @arg RCC_APB1Periph_USB
+ * @arg RCC_APB1Periph_CAN1
+ * @arg RCC_APB1Periph_PWR
+ * @arg RCC_APB1Periph_DAC
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB1RSTR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1RSTR &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Group4 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RCC interrupts.
+ * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
+ * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
+ * automatically generated. The NMI will be executed indefinitely, and
+ * since NMI has higher priority than any other IRQ (and main program)
+ * the application will be stacked in the NMI ISR unless the CSS interrupt
+ * pending bit is cleared.
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @param NewState: new state of the specified RCC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_IT(RCC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * @arg RCC_FLAG_MCOF: MCO Flag
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ * @retval The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+ uint32_t tmp = 0;
+ uint32_t statusreg = 0;
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+
+ if (tmp == 0) /* The flag to check is in CR register */
+ {
+ statusreg = RCC->CR;
+ }
+ else if (tmp == 1) /* The flag to check is in BDCR register */
+ {
+ statusreg = RCC->BDCR;
+ }
+ else if (tmp == 4) /* The flag to check is in CFGR register */
+ {
+ statusreg = RCC->CFGR;
+ }
+ else /* The flag to check is in CSR register */
+ {
+ statusreg = RCC->CSR;
+ }
+
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_MASK;
+
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC reset flags.
+ * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
+ * @param None
+ * @retval None
+ */
+void RCC_ClearFlag(void)
+{
+ /* Set RMVF bit to clear the reset flags */
+ RCC->CSR |= RCC_CSR_RMVF;
+}
+
+/**
+ * @brief Checks whether the specified RCC interrupt has occurred or not.
+ * @param RCC_IT: specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval The new state of RCC_IT (SET or RESET).
+ */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_GET_IT(RCC_IT));
+
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the RCC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC's interrupt pending bits.
+ * @param RCC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval None
+ */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+ pending bits */
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_rcc.h b/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_rcc.h
new file mode 100644
index 0000000000..2885390e26
--- /dev/null
+++ b/lib/CMSIS/CM1/DeviceSupport/ST/STM32F30x/stm32f30x_rcc.h
@@ -0,0 +1,699 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_rcc.h
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 04-April-2014
+ * @brief This file contains all the functions prototypes for the RCC
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2014 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_RCC_H
+#define __STM32F30x_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+typedef struct
+{
+ uint32_t SYSCLK_Frequency;
+ uint32_t HCLK_Frequency;
+ uint32_t PCLK1_Frequency;
+ uint32_t PCLK2_Frequency;
+ uint32_t ADC12CLK_Frequency;
+ uint32_t ADC34CLK_Frequency;
+ uint32_t I2C1CLK_Frequency;
+ uint32_t I2C2CLK_Frequency;
+ uint32_t I2C3CLK_Frequency;
+ uint32_t TIM1CLK_Frequency;
+ uint32_t HRTIM1CLK_Frequency;
+ uint32_t TIM8CLK_Frequency;
+ uint32_t USART1CLK_Frequency;
+ uint32_t USART2CLK_Frequency;
+ uint32_t USART3CLK_Frequency;
+ uint32_t UART4CLK_Frequency;
+ uint32_t UART5CLK_Frequency;
+ uint32_t TIM15CLK_Frequency;
+ uint32_t TIM16CLK_Frequency;
+ uint32_t TIM17CLK_Frequency;
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RCC_HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_OFF ((uint8_t)0x00)
+#define RCC_HSE_ON ((uint8_t)0x01)
+#define RCC_HSE_Bypass ((uint8_t)0x05)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_Bypass))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source
+ * @{
+ */
+
+#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
+#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
+
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+ ((SOURCE) == RCC_PLLSource_PREDIV1))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Multiplication_Factor
+ * @{
+ */
+
+#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
+#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
+#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
+#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
+#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
+#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
+#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
+#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
+#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
+#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
+#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
+#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
+#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
+#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
+#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+ ((MUL) == RCC_PLLMul_16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PREDIV1_division_factor
+ * @{
+ */
+#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
+#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
+#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
+#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
+#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
+#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
+#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
+#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
+#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
+#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
+#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
+#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
+#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
+#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
+#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
+#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
+
+#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source
+ * @{
+ */
+
+#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source
+ * @{
+ */
+
+#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+ ((HCLK) == RCC_SYSCLK_Div512))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_clock_source
+ * @{
+ */
+
+#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+ ((PCLK) == RCC_HCLK_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_ADC_clock_source
+ * @{
+ */
+
+/* ADC1 & ADC2 */
+#define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
+#define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
+#define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
+#define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
+#define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
+#define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
+#define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
+#define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)
+#define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170)
+#define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180)
+#define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190)
+#define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0)
+#define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0)
+
+/* ADC3 & ADC4 */
+#define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000)
+#define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000)
+#define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200)
+#define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400)
+#define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600)
+#define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800)
+#define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00)
+#define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00)
+#define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00)
+#define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000)
+#define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200)
+#define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400)
+#define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600)
+
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_TIM_clock_source
+ * @{
+ */
+
+#define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000)
+#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW
+
+#define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000)
+#define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200)
+
+#define RCC_TIM15CLK_HCLK ((uint32_t)0x20000000)
+#define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400)
+
+#define RCC_TIM16CLK_HCLK ((uint32_t)0x30000000)
+#define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800)
+
+#define RCC_TIM17CLK_HCLK ((uint32_t)0x40000000)
+#define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000)
+
+#define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
+ ((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
+ ((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
+ ((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
+ ((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HRTIM_clock_source
+ * @{
+ */
+
+#define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000)
+#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW
+
+#define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2C_clock_source
+ * @{
+ */
+
+#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
+#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
+
+#define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
+#define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
+
+#define RCC_I2C3CLK_HSI ((uint32_t)0x20000000)
+#define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040)
+
+#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
+ ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
+ ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_USART_clock_source
+ * @{
+ */
+
+#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
+#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
+#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
+#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
+
+#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
+#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
+#define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
+#define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
+
+#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
+#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
+#define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
+#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
+
+#define RCC_UART4CLK_PCLK ((uint32_t)0x40000000)
+#define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000)
+#define RCC_UART4CLK_LSE ((uint32_t)0x40200000)
+#define RCC_UART4CLK_HSI ((uint32_t)0x40300000)
+
+#define RCC_UART5CLK_PCLK ((uint32_t)0x50000000)
+#define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000)
+#define RCC_UART5CLK_LSE ((uint32_t)0x50800000)
+#define RCC_UART5CLK_HSI ((uint32_t)0x50C00000)
+
+#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
+ ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
+ ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
+ ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
+ ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt_Source
+ * @{
+ */
+
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_CSS ((uint8_t)0x80)
+
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
+
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
+
+
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_configuration
+ * @{
+ */
+
+#define RCC_LSE_OFF ((uint32_t)0x00000000)
+#define RCC_LSE_ON RCC_BDCR_LSEON
+#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_Bypass))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source
+ * @{
+ */
+
+#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
+#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
+#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
+
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2S_Clock_Source
+ * @{
+ */
+#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
+#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
+
+#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
+
+/** @defgroup RCC_LSE_Drive_Configuration
+ * @{
+ */
+
+#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
+#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
+#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
+#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
+#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
+ ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Peripherals
+ * @{
+ */
+
+#define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
+#define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
+#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
+#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
+#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
+#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
+#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
+#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
+#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
+#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
+#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
+#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
+#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
+#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Peripherals
+ * @{
+ */
+
+#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
+#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
+#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
+#define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN
+#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
+#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
+#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
+#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
+#define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Peripherals
+ * @{
+ */
+#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
+#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
+#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
+#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
+#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
+#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
+#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
+#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
+#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
+#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
+#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
+#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
+#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
+#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
+#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
+#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN
+#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
+#define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN
+#define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN
+#define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN
+#define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1
+
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Clock_Source
+ * @{
+ */
+
+#define RCC_MCOSource_NoClock ((uint8_t)0x00)
+#define RCC_MCOSource_LSI ((uint8_t)0x02)
+#define RCC_MCOSource_LSE ((uint8_t)0x03)
+#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
+#define RCC_MCOSource_HSI ((uint8_t)0x05)
+#define RCC_MCOSource_HSE ((uint8_t)0x06)
+#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
+
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
+ ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
+ ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
+ ((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOPrescaler
+ * @{
+ */
+
+#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
+#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
+#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
+#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
+#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
+#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
+#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
+#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
+
+#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
+ ((PRESCALER) == RCC_MCOPrescaler_2) || \
+ ((PRESCALER) == RCC_MCOPrescaler_4) || \
+ ((PRESCALER) == RCC_MCOPrescaler_8) || \
+ ((PRESCALER) == RCC_MCOPrescaler_16) || \
+ ((PRESCALER) == RCC_MCOPrescaler_32) || \
+ ((PRESCALER) == RCC_MCOPrescaler_64) || \
+ ((PRESCALER) == RCC_MCOPrescaler_128))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_USB_Device_clock_source
+ * @{
+ */
+
+#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
+#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
+
+#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
+ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag
+ * @{
+ */
+#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
+#define RCC_FLAG_HSERDY ((uint8_t)0x11)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
+#define RCC_FLAG_MCOF ((uint8_t)0x9C)
+#define RCC_FLAG_LSERDY ((uint8_t)0x21)
+#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
+#define RCC_FLAG_OBLRST ((uint8_t)0x59)
+#define RCC_FLAG_PINRST ((uint8_t)0x5A)
+#define RCC_FLAG_PORRST ((uint8_t)0x5B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
+
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
+ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
+ ((FLAG) == RCC_FLAG_MCOF))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the RCC clock configuration to the default reset state */
+void RCC_DeInit(void);
+
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
+void RCC_HSEConfig(uint8_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_LSEConfig(uint32_t RCC_LSE);
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+#ifdef STM32F303xC
+ void RCC_MCOConfig(uint8_t RCC_MCOSource);
+#else
+ void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
+#endif /* STM32F303xC */
+
+/* System, AHB and APB busses clocks configuration functions ******************/
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+
+/* Peripheral clocks configuration functions **********************************/
+void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
+void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
+void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK);
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_RCC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/drivers/gpio_common.h b/src/drivers/gpio_common.h
index ec0a9f5a17..ad219c2147 100644
--- a/src/drivers/gpio_common.h
+++ b/src/drivers/gpio_common.h
@@ -1,5 +1,6 @@
#pragma once
+#ifdef STM32F10X_MD
typedef enum
{
Mode_AIN = 0x0,
@@ -11,6 +12,45 @@ typedef enum
Mode_AF_OD = 0x1C,
Mode_AF_PP = 0x18
} GPIO_Mode;
+#endif
+
+#ifdef STM32F303xC
+
+/*
+typedef enum
+{
+ GPIO_Mode_IN = 0x00, // GPIO Input Mode
+ GPIO_Mode_OUT = 0x01, // GPIO Output Mode
+ GPIO_Mode_AF = 0x02, // GPIO Alternate function Mode
+ GPIO_Mode_AN = 0x03 // GPIO Analog In/Out Mode
+}GPIOMode_TypeDef;
+
+typedef enum
+{
+ GPIO_OType_PP = 0x00,
+ GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+
+typedef enum
+{
+ GPIO_PuPd_NOPULL = 0x00,
+ GPIO_PuPd_UP = 0x01,
+ GPIO_PuPd_DOWN = 0x02
+}GPIOPuPd_TypeDef;
+*/
+
+typedef enum
+{
+ Mode_AIN = (GPIO_PuPd_NOPULL << 2) | GPIO_Mode_AN,
+ Mode_IN_FLOATING = (GPIO_PuPd_NOPULL << 2) | GPIO_Mode_IN,
+ Mode_IPD = (GPIO_PuPd_DOWN << 2) | GPIO_Mode_IN,
+ Mode_IPU = (GPIO_PuPd_UP << 2) | GPIO_Mode_IN,
+ Mode_Out_OD = (GPIO_OType_OD << 4) | GPIO_Mode_OUT,
+ Mode_Out_PP = (GPIO_OType_PP << 4) | GPIO_Mode_OUT,
+ Mode_AF_OD = (GPIO_OType_OD << 4) | GPIO_Mode_AF,
+ Mode_AF_PP = (GPIO_OType_PP << 4) | GPIO_Mode_AF
+} GPIO_Mode;
+#endif
typedef enum
{
diff --git a/src/drivers/gpio_stm32f30x.c b/src/drivers/gpio_stm32f30x.c
index b6a1e6338b..a25fb88f1e 100644
--- a/src/drivers/gpio_stm32f30x.c
+++ b/src/drivers/gpio_stm32f30x.c
@@ -6,9 +6,66 @@
#include "gpio_common.h"
+#define MODE_OFFSET 0
+#define PUPD_OFFSET 2
+#define OUTPUT_OFFSET 4
+
+#define MODE_MASK ((1|2) << MODE_OFFSET)
+#define PUPD_MASK ((1|2) << PUPD_OFFSET)
+#define OUTPUT_MASK ((1|2) << OUTPUT_OFFSET)
+/*
+typedef enum
+{
+ Mode_AIN = (GPIO_PuPd_NOPULL << 2) | GPIO_Mode_AN,
+ Mode_IN_FLOATING = (GPIO_PuPd_NOPULL << 2) | GPIO_Mode_IN,
+ Mode_IPD = (GPIO_PuPd_DOWN << 2) | GPIO_Mode_IN,
+ Mode_IPU = (GPIO_PuPd_UP << 2) | GPIO_Mode_IN,
+ Mode_Out_OD = (GPIO_OType_OD << 4) | GPIO_Mode_OUT,
+ Mode_Out_PP = (GPIO_OType_PP << 4) | GPIO_Mode_OUT,
+ Mode_AF_OD = (GPIO_OType_OD << 4) | GPIO_Mode_AF,
+ Mode_AF_PP = (GPIO_OType_PP << 4) | GPIO_Mode_AF
+} GPIO_Mode;
+
+*/
+
+//#define GPIO_Speed_10MHz GPIO_Speed_Level_1 Fast Speed:10MHz
+//#define GPIO_Speed_2MHz GPIO_Speed_Level_2 Medium Speed:2MHz
+//#define GPIO_Speed_50MHz GPIO_Speed_Level_3 High Speed:50MHz
+
void gpioInit(GPIO_TypeDef *gpio, gpio_config_t *config)
{
// FIXME implement
+
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ uint32_t pinIndex;
+ for (pinIndex = 0; pinIndex < 16; pinIndex++) {
+ // are we doing this pin?
+ uint32_t pinMask = (0x1 << pinIndex);
+ if (config->pin & pinMask) {
+
+ GPIO_InitStructure.GPIO_Pin = pinMask;
+ GPIO_InitStructure.GPIO_Mode = (config->mode >> MODE_OFFSET) & MODE_MASK;
+
+ GPIOSpeed_TypeDef speed = GPIO_Speed_10MHz;
+ switch (config->speed) {
+ case Speed_10MHz:
+ speed = GPIO_Speed_Level_1;
+ break;
+ case Speed_2MHz:
+ speed = GPIO_Speed_Level_2;
+ break;
+ case Speed_50MHz:
+ speed = GPIO_Speed_Level_3;
+ break;
+ }
+
+ GPIO_InitStructure.GPIO_Speed = speed;
+ GPIO_InitStructure.GPIO_OType = (config->mode >> OUTPUT_OFFSET) & OUTPUT_MASK;
+ GPIO_InitStructure.GPIO_PuPd = (config->mode >> PUPD_OFFSET) & PUPD_MASK;
+ GPIO_Init(gpio, &GPIO_InitStructure);
+ }
+ }
}
void gpioExtiLineConfig(uint8_t portsrc, uint8_t pinsrc)
diff --git a/src/drivers/serial_uart_stm32f30x.c b/src/drivers/serial_uart_stm32f30x.c
index 6fc4b6a98b..057a2d7e03 100644
--- a/src/drivers/serial_uart_stm32f30x.c
+++ b/src/drivers/serial_uart_stm32f30x.c
@@ -25,7 +25,6 @@ uartPort_t *serialUSART1(uint32_t baudRate, portMode_t mode)
uartPort_t *s;
static volatile uint8_t rx1Buffer[UART1_RX_BUFFER_SIZE];
static volatile uint8_t tx1Buffer[UART1_TX_BUFFER_SIZE];
- gpio_config_t gpio;
NVIC_InitTypeDef NVIC_InitStructure;
s = &uartPort1;
@@ -42,8 +41,34 @@ uartPort_t *serialUSART1(uint32_t baudRate, portMode_t mode)
s->txDMAChannel = DMA1_Channel4;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+
// USART1_TX PA9
// USART1_RX PA10
+
+#ifdef STM32F303xC
+
+#define UART1_TX_PIN GPIO_Pin_9
+#define UART1_RX_PIN GPIO_Pin_10
+#define UART1_GPIO GPIOA
+#define UART1_TX_PINSOURCE GPIO_PinSource9
+#define UART1_RX_PINSOURCE GPIO_PinSource10
+
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ GPIO_InitStructure.GPIO_Pin = UART1_TX_PIN | UART1_RX_PIN;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+
+ GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PINSOURCE, GPIO_AF_7);
+ GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PINSOURCE, GPIO_AF_7);
+
+ GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
+#endif
+
+#ifdef STM32F10X_MD
+ gpio_config_t gpio;
gpio.speed = Speed_2MHz;
gpio.pin = Pin_9;
gpio.mode = Mode_AF_PP;
@@ -53,6 +78,7 @@ uartPort_t *serialUSART1(uint32_t baudRate, portMode_t mode)
gpio.mode = Mode_IPU;
if (mode & MODE_RX)
gpioInit(GPIOA, &gpio);
+#endif
// DMA TX Interrupt
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel4_IRQn;
@@ -146,7 +172,6 @@ serialPort_t *uartOpen(USART_TypeDef *USARTx, serialReceiveCallbackPtr callback,
if (mode & MODE_TX)
USART_InitStructure.USART_Mode |= USART_Mode_Tx;
USART_Init(USARTx, &USART_InitStructure);
- USART_Cmd(USARTx, ENABLE);
DMA_StructInit(&DMA_InitStructure);
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&USARTx->RDR;
@@ -200,6 +225,8 @@ serialPort_t *uartOpen(USART_TypeDef *USARTx, serialReceiveCallbackPtr callback,
}
}
+ USART_Cmd(USARTx, ENABLE);
+
return (serialPort_t *)s;
}
diff --git a/src/drivers/system_common.c b/src/drivers/system_common.c
index 3e34fe7990..a20e1ce821 100755
--- a/src/drivers/system_common.c
+++ b/src/drivers/system_common.c
@@ -110,9 +110,15 @@ void systemInit(bool overclock)
RCC_ClearFlag();
// Make all GPIO in by default to save power and reduce noise
- gpio.pin = Pin_All;
gpio.mode = Mode_AIN;
+ gpio.pin = Pin_All;
+#ifdef STM32F3DISCOVERY
+ gpio.pin = Pin_All & ~(Pin_13|Pin_14);
gpioInit(GPIOA, &gpio);
+ gpio.pin = Pin_All;
+#else
+ gpioInit(GPIOA, &gpio);
+#endif
gpioInit(GPIOB, &gpio);
gpioInit(GPIOC, &gpio);
diff --git a/src/platform.h b/src/platform.h
index f489ec087b..5e3762ab8d 100644
--- a/src/platform.h
+++ b/src/platform.h
@@ -4,6 +4,8 @@
#ifdef STM32F3DISCOVERY
#include "stm32f30x_conf.h"
+#include "stm32f30x_rcc.h"
+#include "stm32f30x_gpio.h"
#include "core_cm4.h"
// FIXME use correct ID