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https://github.com/betaflight/betaflight.git
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Moved hardware specific parts into 'transponder_ir.c'.
This commit is contained in:
mikeller
parent
46d77e3316
commit
9ad094f9aa
9 changed files with 169 additions and 291 deletions
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@ -24,7 +24,12 @@
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#include "dma.h"
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#include "nvic.h"
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#include "io.h"
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#include "rcc.h"
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#include "timer.h"
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#if defined(STM32F4)
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#include "timer_stm32f4xx.h"
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#endif
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#include "transponder_ir.h"
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/*
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@ -39,6 +44,135 @@ uint8_t transponderIrDMABuffer[TRANSPONDER_DMA_BUFFER_SIZE];
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volatile uint8_t transponderIrDataTransferInProgress = 0;
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static IO_t transponderIO = IO_NONE;
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static TIM_TypeDef *timer = NULL;
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#if defined(STM32F3)
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static DMA_Channel_TypeDef *dmaChannel = NULL;
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#elif defined(STM32F4)
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static DMA_Stream_TypeDef *stream = NULL;
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#else
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#error "Transponder not supported on this MCU."
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#endif
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static void TRANSPONDER_DMA_IRQHandler(dmaChannelDescriptor_t* descriptor)
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{
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if (DMA_GET_FLAG_STATUS(descriptor, DMA_IT_TCIF)) {
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transponderIrDataTransferInProgress = 0;
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#if defined(STM32F3)
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DMA_Cmd(descriptor->channel, DISABLE);
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#elif defined(STM32F4)
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DMA_Cmd(descriptor->stream, DISABLE);
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#endif
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DMA_CLEAR_FLAG(descriptor, DMA_IT_TCIF);
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}
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}
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void transponderIrHardwareInit(ioTag_t ioTag)
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{
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if (!ioTag) {
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return;
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}
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TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
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TIM_OCInitTypeDef TIM_OCInitStructure;
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DMA_InitTypeDef DMA_InitStructure;
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const timerHardware_t *timerHardware = timerGetByTag(ioTag, TIM_USE_ANY);
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timer = timerHardware->tim;
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#if defined(STM32F3)
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if (timerHardware->dmaChannel == NULL) {
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return;
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}
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#elif defined(STM32F4)
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if (timerHardware->dmaStream == NULL) {
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return;
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}
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#endif
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transponderIO = IOGetByTag(ioTag);
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IOInit(transponderIO, OWNER_TRANSPONDER, 0);
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IOConfigGPIOAF(transponderIO, IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_DOWN), timerHardware->alternateFunction);
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dmaInit(timerHardware->dmaIrqHandler, OWNER_TRANSPONDER, 0);
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dmaSetHandler(timerHardware->dmaIrqHandler, TRANSPONDER_DMA_IRQHandler, NVIC_PRIO_TRANSPONDER_DMA, 0);
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RCC_ClockCmd(timerRCC(timer), ENABLE);
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/* Time base configuration */
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TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
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TIM_TimeBaseStructure.TIM_Period = 156;
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TIM_TimeBaseStructure.TIM_Prescaler = 0;
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TIM_TimeBaseStructure.TIM_ClockDivision = 0;
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TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
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TIM_TimeBaseInit(timer, &TIM_TimeBaseStructure);
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/* PWM1 Mode configuration: Channel1 */
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TIM_OCStructInit(&TIM_OCInitStructure);
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TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
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if (timerHardware->output & TIMER_OUTPUT_N_CHANNEL) {
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TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
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TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset;
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} else {
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TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
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TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
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}
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TIM_OCInitStructure.TIM_OCPolarity = (timerHardware->output & TIMER_OUTPUT_INVERTED) ? TIM_OCPolarity_Low : TIM_OCPolarity_High;
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TIM_OCInitStructure.TIM_Pulse = 0;
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#if defined(STM32F3)
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TIM_OC1Init(timer, &TIM_OCInitStructure);
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TIM_OC1PreloadConfig(timer, TIM_OCPreload_Enable);
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#elif defined(STM32F4)
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timerOCInit(timer, timerHardware->channel, &TIM_OCInitStructure);
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timerOCPreloadConfig(timer, timerHardware->channel, TIM_OCPreload_Enable);
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#endif
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TIM_CtrlPWMOutputs(timer, ENABLE);
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/* configure DMA */
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#if defined(STM32F3)
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dmaChannel = timerHardware->dmaChannel;
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DMA_DeInit(dmaChannel);
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#elif defined(STM32F4)
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stream = timerHardware->dmaStream;
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DMA_Cmd(stream, DISABLE);
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DMA_DeInit(stream);
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#endif
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DMA_StructInit(&DMA_InitStructure);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)timerCCR(timer, timerHardware->channel);
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#if defined(STM32F3)
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DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)transponderIrDMABuffer;
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#elif defined(STM32F4)
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DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)transponderIrDMABuffer;
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#endif
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DMA_InitStructure.DMA_BufferSize = TRANSPONDER_DMA_BUFFER_SIZE;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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#if defined(STM32F3)
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(dmaChannel, &DMA_InitStructure);
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#elif defined(STM32F4)
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DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
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DMA_Init(stream, &DMA_InitStructure);
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#endif
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TIM_DMACmd(timer, timerDmaSource(timerHardware->channel), ENABLE);
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#if defined(STM32F3)
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DMA_ITConfig(dmaChannel, DMA_IT_TC, ENABLE);
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#elif defined(STM32F4)
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DMA_ITConfig(stream, DMA_IT_TC, ENABLE);
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#endif
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}
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bool transponderIrInit(void)
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{
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memset(&transponderIrDMABuffer, 0, TRANSPONDER_DMA_BUFFER_SIZE);
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@ -57,6 +191,7 @@ bool transponderIrInit(void)
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transponderIrHardwareInit(ioTag);
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return true;
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}
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@ -119,6 +254,40 @@ void transponderIrUpdateData(const uint8_t* transponderData)
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updateTransponderDMABuffer(transponderData);
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}
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void transponderIrDMAEnable(void)
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{
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#if defined(STM32F3)
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DMA_SetCurrDataCounter(dmaChannel, TRANSPONDER_DMA_BUFFER_SIZE); // load number of bytes to be transferred
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#elif defined(STM32F4)
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DMA_SetCurrDataCounter(stream, TRANSPONDER_DMA_BUFFER_SIZE); // load number of bytes to be transferred
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#endif
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TIM_SetCounter(timer, 0);
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TIM_Cmd(timer, ENABLE);
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#if defined(STM32F3)
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DMA_Cmd(dmaChannel, ENABLE);
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#elif defined(STM32F4)
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DMA_Cmd(stream, ENABLE);
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#endif
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}
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void transponderIrDisable(void)
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{
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#if defined(STM32F3)
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DMA_Cmd(dmaChannel, DISABLE);
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#elif defined(STM32F4)
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DMA_Cmd(stream, DISABLE);
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#endif
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TIM_Cmd(timer, DISABLE);
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IOInit(transponderIO, OWNER_TRANSPONDER, 0);
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IOConfigGPIOAF(transponderIO, IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_DOWN), timerHardware->alternateFunction);
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#ifdef TRANSPONDER_INVERTED
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IOHi(transponderIO);
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#else
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IOLo(transponderIO);
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#endif
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}
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void transponderIrTransmit(void)
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{
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