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Merge pull request #10875 from hydra/bf-fix-bitbang-dshot
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parent
ac4170cbc7
commit
9c84c4f398
2 changed files with 5 additions and 6 deletions
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@ -548,22 +548,21 @@ static void bbUpdateComplete(void)
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}
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}
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}
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}
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#ifdef USE_DSHOT_TELEMETRY
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for (int i = 0; i < usedMotorPorts; i++) {
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for (int i = 0; i < usedMotorPorts; i++) {
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bbPort_t *bbPort = &bbPorts[i];
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bbPort_t *bbPort = &bbPorts[i];
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#ifdef USE_DSHOT_TELEMETRY
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if (useDshotTelemetry) {
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if (useDshotTelemetry) {
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if (bbPort->direction == DSHOT_BITBANG_DIRECTION_INPUT) {
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if (bbPort->direction == DSHOT_BITBANG_DIRECTION_INPUT) {
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bbPort->inputActive = false;
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bbPort->inputActive = false;
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bbSwitchToOutput(bbPort);
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bbSwitchToOutput(bbPort);
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}
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}
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bbDMA_Cmd(bbPort, ENABLE);
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}
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}
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}
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#endif
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#endif
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bbDMA_Cmd(bbPort, ENABLE);
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}
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lastSendUs = micros();
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lastSendUs = micros();
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for (int i = 0; i < usedMotorPacers; i++) {
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for (int i = 0; i < usedMotorPacers; i++) {
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bbPacer_t *bbPacer = &bbPacers[i];
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bbPacer_t *bbPacer = &bbPacers[i];
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@ -45,6 +45,7 @@ mpuRegion_t mpuRegions[] = {
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.bufferable = MPU_ACCESS_BUFFERABLE,
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.bufferable = MPU_ACCESS_BUFFERABLE,
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},
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},
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#endif
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#endif
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#ifdef USE_DMA_RAM
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{
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{
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// DMA transmit buffer in D2 SRAM1
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// DMA transmit buffer in D2 SRAM1
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// Reading needs cache coherence operation
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// Reading needs cache coherence operation
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@ -57,7 +58,6 @@ mpuRegion_t mpuRegions[] = {
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.cacheable = MPU_ACCESS_CACHEABLE,
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.cacheable = MPU_ACCESS_CACHEABLE,
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.bufferable = MPU_ACCESS_NOT_BUFFERABLE,
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.bufferable = MPU_ACCESS_NOT_BUFFERABLE,
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},
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},
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#ifdef USE_SDCARD_SDIO
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{
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{
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// A region in AXI RAM accessible from SDIO internal DMA
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// A region in AXI RAM accessible from SDIO internal DMA
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.start = (uint32_t)&dmarwaxi_start,
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.start = (uint32_t)&dmarwaxi_start,
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